{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T19:10:31Z","timestamp":1761419431080,"version":"3.37.3"},"reference-count":30,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2020,9,2]],"date-time":"2020-09-02T00:00:00Z","timestamp":1599004800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2020,9,2]],"date-time":"2020-09-02T00:00:00Z","timestamp":1599004800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2021,3]]},"DOI":"10.1007\/s00034-020-01532-5","type":"journal-article","created":{"date-parts":[[2020,9,2]],"date-time":"2020-09-02T12:02:39Z","timestamp":1599048159000},"page":"1383-1396","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Ultra-High-Performance Magnetic Nonvolatile Level Converter Flip-Flop with Spin-Hall Assistance for Dual-Supply Systems with Power Gating Architecture"],"prefix":"10.1007","volume":"40","author":[{"given":"Mehrdad","family":"Morsali","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9711-7923","authenticated-orcid":false,"given":"Mohammad Hossein","family":"Moaiyeri","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2020,9,2]]},"reference":[{"key":"1532_CR1","doi-asserted-by":"publisher","unstructured":"K. Ali, F. Li, S. Y. H. Lua and C. Heng, Compact spin transfer torque non-volatile flip flop design for power-gating architecture. 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, pp. 119-122 (2016). https:\/\/doi.org\/10.1109\/APCCAS.2016.7803911","DOI":"10.1109\/APCCAS.2016.7803911"},{"key":"1532_CR2","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/LMAG.2019.2958813","volume":"10","author":"A Amirany","year":"2019","unstructured":"A. Amirany, M.H. Moaiyeri, K. Jafari, Process-in-memory using a magnetic-tunnel-junction synapse and a neuron based on a carbon nanotube field-effect transistor. IEEE Magnet. Lett. 10, 1\u20135 (2019). https:\/\/doi.org\/10.1109\/LMAG.2019.2958813","journal-title":"IEEE Magnet. Lett."},{"issue":"12","key":"1532_CR3","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/TMAG.2018.2869811","volume":"54","author":"A Amirany","year":"2018","unstructured":"A. Amirany, R. Rajaei, Fully nonvolatile and low power full adder based on spin transfer torque magnetic tunnel junction with spin-hall effect assistance. IEEE Trans. Magnet. 54(12), 1\u20137 (2018). https:\/\/doi.org\/10.1109\/TMAG.2018.2869811","journal-title":"IEEE Trans. Magnet."},{"issue":"5","key":"1532_CR4","doi-asserted-by":"publisher","first-page":"1123","DOI":"10.1109\/TCAD.2019.2907886","volume":"39","author":"S Angizi","year":"2019","unstructured":"S. Angizi, Z. He, A. Awad, D. Fan, MRIMA: an MRAM-based in-memory accelerator. IEEE Trans. Comput. Aid. Des. Integr. Circuit. Syst. 39(5), 1123\u20131136 (2019). https:\/\/doi.org\/10.1109\/TCAD.2019.2907886","journal-title":"IEEE Trans. Comput. Aid. Des. Integr. Circuit. Syst."},{"issue":"2","key":"1532_CR5","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/TMAG.2019.2955626","volume":"56","author":"S Angizi","year":"2020","unstructured":"S. Angizi, Z. He, A. Chen, D. Fan, Hybrid spin-CMOS polymorphic logic gate with application in in-memory computing. IEEE Trans. Magnet. 56(2), 1\u201315 (2020). https:\/\/doi.org\/10.1109\/TMAG.2019.2955626","journal-title":"IEEE Trans. Magnet."},{"issue":"6","key":"1532_CR6","doi-asserted-by":"publisher","first-page":"1755","DOI":"10.1109\/TCSI.2013.2295026","volume":"61","author":"D Chabi","year":"2014","unstructured":"D. Chabi et al., Ultra low power magnetic flip-flop based on checkpointing\/power gating and self-enable mechanisms. IEEE Trans. Circuit. Syst. I: Regul. Pap. 61(6), 1755\u20131765 (2014). https:\/\/doi.org\/10.1109\/TCSI.2013.2295026","journal-title":"IEEE Trans. Circuit. Syst. I: Regul. Pap."},{"key":"1532_CR7","doi-asserted-by":"publisher","first-page":"105","DOI":"10.1016\/j.mejo.2016.04.006","volume":"53","author":"LT Clark","year":"2016","unstructured":"L.T. Clark, V. Vashishtha, L. Shifren, A. Gujja, S. Sinha, B. Cline, C. Ramamurthy, G. Yeric, ASAP7:A7-nm finFET predictive process design kit. Microelectron. J. 53, 105\u2013115 (2016). https:\/\/doi.org\/10.1016\/j.mejo.2016.04.006","journal-title":"Microelectron. J."},{"key":"1532_CR8","doi-asserted-by":"publisher","first-page":"153128","DOI":"10.1016\/j.aeue.2020.153128","volume":"117","author":"Z DavariShalamzari","year":"2020","unstructured":"Z. DavariShalamzari, A. DabbaghiZarandi, M.R. Reshadinezhad, Newly multiplexer-based quaternary half-adder and multiplier using CNTFETs. AEU Int. J. Electron. Commun. 117, 153128 (2020). https:\/\/doi.org\/10.1016\/j.aeue.2020.153128","journal-title":"AEU Int. J. Electron. Commun."},{"issue":"7","key":"1532_CR9","doi-asserted-by":"publisher","first-page":"1757","DOI":"10.1109\/TCSI.2015.2423751","volume":"62","author":"E Deng","year":"2015","unstructured":"E. Deng et al., Synchronous 8-bit non-volatile full-adder based on spin transfer torque magnetic tunnel junction. IEEE Trans. Circuit. Syst. I Reg. Pap. 62(7), 1757\u20131765 (2015). https:\/\/doi.org\/10.1109\/TCSI.2015.2423751","journal-title":"IEEE Trans. Circuit. Syst. I Reg. Pap."},{"issue":"4","key":"1532_CR10","doi-asserted-by":"publisher","first-page":"878","DOI":"10.1109\/TED.2011.2182053","volume":"59","author":"R Dorrance","year":"2012","unstructured":"R. Dorrance, F. Ren, Y. Toriyama, A.A. Hafez, C.-K.K. Yang, D. Markovic, Scalability and design-space analysis of a 1 T-1 MTJ memory cell for STT-RAMs. IEEE Trans. Electron Dev. 59(4), 878\u2013887 (2012). https:\/\/doi.org\/10.1109\/TED.2011.2182053","journal-title":"IEEE Trans. Electron Dev."},{"key":"1532_CR11","doi-asserted-by":"publisher","unstructured":"E. Eken et al, Spin-hall assisted STT-RAM design and discussion, in 2016 ACM\/IEEE International Workshop on System Level Interconnect Prediction (SLIP), Austin, TX, pp. 1-4 (2016). https:\/\/doi.org\/10.1145\/2947357.2947360","DOI":"10.1145\/2947357.2947360"},{"issue":"12","key":"1532_CR12","doi-asserted-by":"publisher","first-page":"5606","DOI":"10.1007\/s00034-019-01132-y","volume":"38","author":"D Esposito","year":"2019","unstructured":"D. Esposito, D. De Caro, G. Di Meo, E. Napoli, A.G.M. Strollo, Low-power hardware implementation of least-mean-square adaptive filters using approximate arithmetic. Circuit. Syst. Signal Process. 38(12), 5606\u20135622 (2019). https:\/\/doi.org\/10.1007\/s00034-019-01132-y","journal-title":"Circuit. Syst. Signal Process."},{"key":"1532_CR13","doi-asserted-by":"publisher","unstructured":"F. Ishihara, F. Sheikh, B. Nikolic, Level Conversion for Dual-Supply Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12(2), 185-195 (2004). https:\/\/doi.org\/10.1109\/TVLSI.2003.821548","DOI":"10.1109\/TVLSI.2003.821548"},{"key":"1532_CR14","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/LMAG.2018.2829676","volume":"9","author":"A Jaiswal","year":"2018","unstructured":"A. Jaiswal, R. Andrawis, K. Roy, Area-efficient nonvolatile flip-flop based on spin hall effect. IEEE Magnet. Lett. 9, 1\u20134 (2018). https:\/\/doi.org\/10.1109\/LMAG.2018.2829676","journal-title":"IEEE Magnet. Lett."},{"issue":"3","key":"1532_CR15","doi-asserted-by":"publisher","first-page":"1175","DOI":"10.1007\/s10825-020-01516-3","volume":"19","author":"AA Javadi","year":"2020","unstructured":"A.A. Javadi, M. Morsali, M.H. Moaiyeri, Magnetic nonvolatile flip-flops with spin-hall assistance for power gating in ternary systems. J. Comput. Electron. 19(3), 1175\u20131186 (2020). https:\/\/doi.org\/10.1007\/s10825-020-01516-3","journal-title":"J. Comput. Electron."},{"issue":"4","key":"1532_CR16","doi-asserted-by":"publisher","first-page":"488","DOI":"10.1109\/LED.2014.2304683","volume":"35","author":"KW Kwon","year":"2014","unstructured":"K.W. Kwon, S.H. Choday, Y. Kim, X. Fong, S.P. Park, K. Roy, SHE-NVFF: spin hall effect based nonvolatile flip-flop for power gating architecture. IEEE Electron Dev. Lett. 35(4), 488\u2013490 (2014). https:\/\/doi.org\/10.1109\/LED.2014.2304683","journal-title":"IEEE Electron Dev. Lett."},{"key":"1532_CR17","doi-asserted-by":"publisher","unstructured":"M. Lanuzza, P. Corsonello and S. Perri, Fast and wide range voltage conversion in multisupply voltage designs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23(2), 388\u2013391 (2015). https:\/\/doi.org\/10.1109\/TVLSI.2014.2308400","DOI":"10.1109\/TVLSI.2014.2308400"},{"issue":"5","key":"1532_CR18","doi-asserted-by":"publisher","first-page":"1164","DOI":"10.1109\/TCSI.2016.2633430","volume":"64","author":"E Maghsoudloo","year":"2017","unstructured":"E. Maghsoudloo, M. Rezaei, M. Sawan, B. Gosselin, A high-speed and ultra low-power subthreshold signal level shifter. IEEE Trans. Circuit. Syst. I Reg. Pap. 64(5), 1164\u20131172 (2017). https:\/\/doi.org\/10.1109\/TCSI.2016.2633430","journal-title":"IEEE Trans. Circuit. Syst. I Reg. Pap."},{"issue":"6","key":"1532_CR19","doi-asserted-by":"publisher","first-page":"2841","DOI":"10.1007\/s00034-019-01309-5","volume":"39","author":"M Morsali","year":"2020","unstructured":"M. Morsali, M.H. Moaiyeri, NVLCFF: an energy-efficient magnetic nonvolatile level converter flip-flop for ultra-low-power design. Circuit. Syst. Signal Process. 39(6), 2841\u20132859 (2020). https:\/\/doi.org\/10.1007\/s00034-019-01309-5","journal-title":"Circuit. Syst. Signal Process."},{"issue":"1","key":"1532_CR20","doi-asserted-by":"publisher","first-page":"598","DOI":"10.1109\/TNANO.2019.2918198","volume":"18","author":"F Razi","year":"2019","unstructured":"F. Razi, M.H. Moaiyeri, R. Rajaei, S. Mohammadi, A variation-aware ternary spin-hall assisted STT-RAM based on hybrid MTJ\/GAA-CNTFET logic. IEEE Trans. Nanotechnol. 18(1), 598\u2013605 (2019). https:\/\/doi.org\/10.1109\/TNANO.2019.2918198","journal-title":"IEEE Trans. Nanotechnol."},{"issue":"11","key":"1532_CR21","doi-asserted-by":"publisher","first-page":"4200","DOI":"10.1109\/TCSI.2019.2918241","volume":"66","author":"F Sabetzadeh","year":"2019","unstructured":"F. Sabetzadeh, M.H. Moaiyeri, M. Ahmadinejad, A majority-based imprecise multiplier for ultra-efficient approximate image multiplication. IEEE Trans. Circuit. Syst. I Reg. Pap. 66(11), 4200\u20134208 (2019). https:\/\/doi.org\/10.1109\/TCSI.2019.2918241","journal-title":"IEEE Trans. Circuit. Syst. I Reg. Pap."},{"key":"1532_CR22","doi-asserted-by":"publisher","unstructured":"Y. Seo, X. Fong, K. Roy, Fast and disturb-free nonvolatile flip-flop using complementary polarizer MTJ. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(4), 1573\u20131577 (2017). https:\/\/doi.org\/10.1109\/TVLSI.2016.2631981","DOI":"10.1109\/TVLSI.2016.2631981"},{"key":"1532_CR23","doi-asserted-by":"crossref","unstructured":"F. Sharifi, M.H. Moaiyeri, K. Navi, N. Bagherzadeh, Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach. Microelectron. J. 46(12), 1333\u20131342 (2015)","DOI":"10.1016\/j.mejo.2015.09.018"},{"key":"1532_CR24","doi-asserted-by":"publisher","unstructured":"Y. Shih et al., Logic process compatible 40-nm 16-Mb, embedded perpendicular-MRAM with hybrid-resistance reference, sub-\u00b5A sensing resolution, and 17.5-nS read access time. IEEE J. Solid-State Circuit. 54(4), 1029\u20131038 (2019). https:\/\/doi.org\/10.1109\/VLSIC.2018.8502260","DOI":"10.1109\/VLSIC.2018.8502260"},{"key":"1532_CR25","doi-asserted-by":"publisher","unstructured":"S. Shirinabadi Farahani, M. R. Reshadinezhad, A new twelve-transistor approximate 4: 2 compressor in CNTFET technology. Int. J. Electron. 106(5), 691\u2013706 (2019). https:\/\/doi.org\/10.1080\/00207217.2018.1545930","DOI":"10.1080\/00207217.2018.1545930"},{"issue":"11","key":"1532_CR26","doi-asserted-by":"publisher","first-page":"4921","DOI":"10.1007\/s00034-019-01108-y","volume":"38","author":"A Udhayakumar","year":"2019","unstructured":"A. Udhayakumar, S. Padma, Low power magnetic non-volatile flip-flops with self-time logical writing for high-end processors. Circuit. Syst. Signal Process. 38(11), 4921\u20134932 (2019). https:\/\/doi.org\/10.1007\/s00034-019-01108-y","journal-title":"Circuit. Syst. Signal Process."},{"key":"1532_CR27","unstructured":"Z. Wang, Compact modeling and circuit design based on ferroelectric tunnel junction and spin-Hall-assisted spin-transfer torque. Ph.D. Dissertation, University of Paris-Saclay, France, (2015)"},{"key":"1532_CR28","doi-asserted-by":"crossref","unstructured":"Z. Wang, W. Zhao, E. Deng, J. O. Klein, C. Chappert, Perpendicular-anisotropy magnetic tunnel junction switched by Spin-Hall-assisted spin-transfer torque. J. Phys. D Appl. Phys. 48(6), (2015). http:\/\/dx.doi.org\/10.1088\/0022-3727\/48\/6\/065001","DOI":"10.1088\/0022-3727\/48\/6\/065001"},{"issue":"4","key":"1532_CR29","doi-asserted-by":"publisher","first-page":"195","DOI":"10.1109\/TMSCS.2015.2509960","volume":"1","author":"C Xu","year":"2015","unstructured":"C. Xu, Y. Zheng, D. Niu, X. Zhu, S.H. Kang, Y. Xie, Impact of write pulse and process variation on 22\u00a0nm FinFET-based STT-RAM design: a device-architecture co-optimization approach. IEEE Trans. Multi-Scale Comput. Syst. 1(4), 195\u2013206 (2015). https:\/\/doi.org\/10.1109\/TMSCS.2015.2509960","journal-title":"IEEE Trans. Multi-Scale Comput. Syst."},{"issue":"3","key":"1532_CR30","doi-asserted-by":"publisher","first-page":"819","DOI":"10.1109\/TED.2011.2178416","volume":"59","author":"Y Zhang","year":"2012","unstructured":"Y. Zhang, W. Zhao, Y. Lakys, J.O. Klein, J.V. Kim, D. Ravelosona, C. Chappert, Compact modeling of perpendicular-anisotropy CoFeB\/MgO magnetic tunnel junctions. IEEE Trans. Electron Dev. 59(3), 819\u2013826 (2012). https:\/\/doi.org\/10.1109\/TED.2011.2178416","journal-title":"IEEE Trans. Electron Dev."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-020-01532-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-020-01532-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-020-01532-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,9,1]],"date-time":"2021-09-01T23:16:31Z","timestamp":1630538191000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-020-01532-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,2]]},"references-count":30,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2021,3]]}},"alternative-id":["1532"],"URL":"https:\/\/doi.org\/10.1007\/s00034-020-01532-5","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2020,9,2]]},"assertion":[{"value":"28 February 2020","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"14 August 2020","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"21 August 2020","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"2 September 2020","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}