{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,22]],"date-time":"2025-04-22T05:47:33Z","timestamp":1745300853033,"version":"3.37.3"},"reference-count":54,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2020,9,24]],"date-time":"2020-09-24T00:00:00Z","timestamp":1600905600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2020,9,24]],"date-time":"2020-09-24T00:00:00Z","timestamp":1600905600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2021,4]]},"DOI":"10.1007\/s00034-020-01550-3","type":"journal-article","created":{"date-parts":[[2020,9,24]],"date-time":"2020-09-24T17:04:03Z","timestamp":1600967043000},"page":"1762-1787","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":10,"title":["Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique"],"prefix":"10.1007","volume":"40","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0431-2963","authenticated-orcid":false,"given":"Inamul","family":"Hussain","sequence":"first","affiliation":[]},{"given":"Saurabh","family":"Chaudhury","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2020,9,24]]},"reference":[{"key":"1550_CR1","doi-asserted-by":"crossref","unstructured":"S. Abbasalizadeh, B. Forouzandeh, Full adder design with GDI cell and independent double gate transistor, in 20th Iranian Conference on Electrical Engineering (ICEE2012) (Tehran 2012), pp. 130\u2013134","DOI":"10.1109\/IranianCEE.2012.6292338"},{"key":"1550_CR2","doi-asserted-by":"publisher","first-page":"2334","DOI":"10.1002\/cta.2540","volume":"46","author":"S Abed","year":"2018","unstructured":"S. Abed, Y. Khalil, M. Modhaffar, I. Ahmad, High-performance low-power approximate Wallace tree multiplier. Int. J. Circ. Theor. Appl. 46, 2334\u20132348 (2018)","journal-title":"Int. J. Circ. Theor. Appl."},{"key":"1550_CR3","first-page":"138","volume":"7","author":"AK Agrawal","year":"2009","unstructured":"A.K. Agrawal, S. Wairya, R.K. Nagaria, A new mixed gate diffusion input full adder topology for high speed low power digital circuits. World Appl. Sci. J. 7, 138\u2013144 (2009)","journal-title":"World Appl. Sci. J."},{"key":"1550_CR4","doi-asserted-by":"crossref","unstructured":"M. Aguirre-Hernandez, M. Linares-Aranda CMOS full-adders for energy-efficient arithmetic applications. IEEE Trans. Very Large Scale Integr. Syst. 19(4), 718\u2013721 (2011)","DOI":"10.1109\/TVLSI.2009.2038166"},{"key":"1550_CR5","doi-asserted-by":"publisher","first-page":"49","DOI":"10.1016\/j.mejo.2018.01.018","volume":"74","author":"M Amini-Valashani","year":"2018","unstructured":"M. Amini-Valashani, M. Ayat, S. Mirzakuchaki, Design and analysis of a novel low-power and energy-efficient 18\u00a0T hybrid full adder. Microelectron. J. 74, 49\u201359 (2018)","journal-title":"Microelectron. J."},{"key":"1550_CR6","doi-asserted-by":"publisher","first-page":"577","DOI":"10.1109\/TCSII.2002.805631","volume":"49","author":"M Anis","year":"2002","unstructured":"M. Anis, M. Allam, M. Elmasry, Impact of technology scaling on CMOS logic styles. IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process. 49, 577\u2013588 (2002)","journal-title":"IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process."},{"issue":"2","key":"1550_CR7","doi-asserted-by":"publisher","first-page":"273","DOI":"10.1109\/4.902768","volume":"36","author":"G Balamurugan","year":"2001","unstructured":"G. Balamurugan, N.R. Shanbhag, The twin-transistor noise-tolerant dynamic circuit technique. IEEE J. Solid-State Circuits 36(2), 273\u2013280 (2001)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"1550_CR8","doi-asserted-by":"crossref","unstructured":"P. Battacharyya, B. Kundu, S. Ghosh, V. Kumar, A. Dandapat, Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23(10), 2001\u20132008 (2015)","DOI":"10.1109\/TVLSI.2014.2357057"},{"issue":"1","key":"1550_CR9","doi-asserted-by":"publisher","first-page":"25","DOI":"10.1109\/82.996055","volume":"49","author":"HT Bui","year":"2002","unstructured":"H.T. Bui, Y. Wang, Y. Jiang, Design and analysis of low-power 10-transistor full adders using novel XOR\u2013XNOR gates. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. 49(1), 25\u201330 (2002)","journal-title":"IEEE Trans. Circuits Syst. II Analog Digit. Signal Process."},{"issue":"4","key":"1550_CR10","doi-asserted-by":"publisher","first-page":"482","DOI":"10.1166\/jolpe.2010.1097","volume":"6","author":"KK Chaddha","year":"2010","unstructured":"K.K. Chaddha, R. Chandel, Design and analysis of a modified low power CMOS full adder using gate-diffusion input technique. J. Low Power Electron. 6(4), 482\u2013490 (2010)","journal-title":"J. Low Power Electron."},{"issue":"6","key":"1550_CR11","doi-asserted-by":"publisher","first-page":"686","DOI":"10.1109\/TVLSI.2005.848806","volume":"13","author":"H Chang","year":"2005","unstructured":"H. Chang, J. Gu, M. Zhang, A review of 0.18-\/spl mu\/m full adder performances for tree structured arithmetic circuits. IEEE Trans. Very Large Scale Integr. Syst. 13(6), 686\u2013695 (2005)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"1550_CR12","doi-asserted-by":"publisher","first-page":"153","DOI":"10.1109\/TNANO.2004.842073","volume":"4","author":"R Chau","year":"2005","unstructured":"R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros et al., Benchmarking nanotechnology for high-performance and low-power logic transistor applications. IEEE Trans. Nanotechnol. 4, 153\u2013158 (2005)","journal-title":"IEEE Trans. Nanotechnol."},{"issue":"12","key":"1550_CR13","doi-asserted-by":"publisher","first-page":"3195","DOI":"10.1109\/TED.2007.909043","volume":"54","author":"J Deng","year":"2007","unstructured":"J. Deng, H.S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application\u2014part II: full device model and circuit performance benchmarking. IEEE Trans. Electron Dev. 54(12), 3195\u20133205 (2007)","journal-title":"IEEE Trans. Electron Dev."},{"issue":"12","key":"1550_CR14","doi-asserted-by":"publisher","first-page":"3186","DOI":"10.1109\/TED.2007.909030","volume":"54","author":"J Deng","year":"2007","unstructured":"J. Deng, H.S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application\u2014part I: model of the intrinsic channel region. IEEE Trans. Electron Dev. 54(12), 3186\u20133194 (2007)","journal-title":"IEEE Trans. Electron Dev."},{"issue":"1","key":"1550_CR15","doi-asserted-by":"publisher","first-page":"48","DOI":"10.1016\/j.vlsi.2013.05.001","volume":"47","author":"V Foroutan","year":"2013","unstructured":"V. Foroutan, M. Taheri, K. Navi, A.A. Mazreah, Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style. Integr. VLSI J. 47(1), 48\u201361 (2013)","journal-title":"Integr. VLSI J."},{"issue":"6","key":"1550_CR16","doi-asserted-by":"publisher","first-page":"537","DOI":"10.1049\/iet-cds:20080070","volume":"2","author":"F Frustaci","year":"2008","unstructured":"F. Frustaci, P. Corsonello, S. Perri, G. Cocorullo, High-performance noise-tolerant circuit techniques for CMOS dynamic logic. IET Circuits Dev. Syst. 2(6), 537\u2013548 (2008)","journal-title":"IET Circuits Dev. Syst."},{"issue":"12","key":"1550_CR17","doi-asserted-by":"publisher","first-page":"1309","DOI":"10.1109\/TVLSI.2006.887807","volume":"14","author":"S Goel","year":"2006","unstructured":"S. Goel, A. Kumar,  M.A. Bayoumi, Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style. IEEE Trans. Very Large Scale Integr. Syst. 14(12), 1309\u20131321 (2006)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"1550_CR18","doi-asserted-by":"publisher","unstructured":"M. Hasan, M.J. Hossein, M. Hossain, H.U. Zaman, S. Islam, Design of a scalable low-power 1-bit hybrid full adder for fast computation. IEEE Trans. Circuits Syst. II Express Briefs (2019). https:\/\/doi.org\/10.1109\/TCSII.2019.2940558","DOI":"10.1109\/TCSII.2019.2940558"},{"issue":"8","key":"1550_CR19","doi-asserted-by":"publisher","first-page":"2066","DOI":"10.1109\/TCSI.2008.2001367","volume":"57","author":"I Hassoune","year":"2010","unstructured":"I. Hassoune, D. Flandre, I. O\u2019Connor, J. Legat, ULPFA, A new efficient design of a power-aware full adder. IEEE Trans. Circuits Syst. I Reg. Pap. 57(8), 2066\u20132074 (2010)","journal-title":"IEEE Trans. Circuits Syst. I Reg. Pap."},{"issue":"1\/2","key":"1550_CR20","doi-asserted-by":"publisher","first-page":"122","DOI":"10.1504\/IJNP.2020.106004","volume":"12","author":"I Hussain","year":"2020","unstructured":"I. Hussain, S. Chaudhury, A comparative study on the effects of technology nodes and logic styles for low power high-speed VLSI applications. Int. J. Nanoparticles 12(1\/2), 122 (2020)","journal-title":"Int. J. Nanoparticles"},{"issue":"3\u20134","key":"1550_CR21","first-page":"173","volume":"12","author":"I Hussain","year":"2017","unstructured":"I. Hussain, M. Kumar, Design and performance analysis of a 3\u20132 compressor by using improved architecture. J. Active Passive Electron. Dev. 12(3\u20134), 173\u2013181 (2017)","journal-title":"J. Active Passive Electron. Dev."},{"issue":"1\u20132","key":"1550_CR22","first-page":"63","volume":"12","author":"I Hussain","year":"2017","unstructured":"I. Hussain, M. Kumar, A fast and reduced complexity wallace multiplier. J. Active Passive Electron. Dev. 12(1\u20132), 63\u201371 (2017)","journal-title":"J. Active Passive Electron. Dev."},{"key":"1550_CR23","doi-asserted-by":"crossref","unstructured":"I. Hussain, A. Singh, S. Chaudhury, A review on the effects of technology on CMOS and CPL logic style on performance, speed and power dissipation, in 2018 IEEE Electron Devices Kolkata Conference (EDKCON) (Kolkata, India, 2018), pp. 332\u2013336","DOI":"10.1109\/EDKCON.2018.8770506"},{"key":"1550_CR24","doi-asserted-by":"crossref","unstructured":"I. Hussain, C.K. Pandey S. Chaudhury, Design and analysis of high performance multiplier circuit, in 2019 Devices for Integrated Circuit (DevIC) (Kalyani, India, 2019), pp. 245\u2013247","DOI":"10.1109\/DEVIC.2019.8783322"},{"key":"1550_CR25","doi-asserted-by":"crossref","unstructured":"I. Hussain, S. Chaudhury, A new 4\u20132 compressor for VLSI circuits and systems, in Advances in Smart System Technologies. Advances in Intelligent Systems and Computing, eds. by P. Suresh, U. Saravanakumar, M. Hussein Al Salameh, vol. 1163 (Springer, Singapore, 2020)","DOI":"10.1007\/978-981-15-5029-4_33"},{"key":"1550_CR26","doi-asserted-by":"publisher","unstructured":"I. Hussain, S. Chaudhury, CNFET based low power full adder circuit for VLSI applications. Nanosci. Nanotechnol. (2020). https:\/\/doi.org\/10.2174\/2210681209666190220122553","DOI":"10.2174\/2210681209666190220122553"},{"key":"1550_CR27","doi-asserted-by":"crossref","unstructured":"I. Hussain, S. Chaudhury, Performance comparison of 1-bit conventional and hybrid full adder circuits, in Advances in Communication, Devices and Networking. Lecture Notes in Electrical Engineering, eds. by R. Bera, S. Sarkar, S. Chakraborty, vol. 462 (Springer, Singapore, 2018)","DOI":"10.1007\/978-981-10-7901-6_6"},{"key":"1550_CR28","doi-asserted-by":"publisher","first-page":"1468","DOI":"10.1109\/TED.2004.833965","volume":"51","author":"JJ Kim","year":"2004","unstructured":"J.J. Kim, K. Roy, Double gate-MOSFET sub-threshold circuit for ultralow power applications. IEEE Trans. Electron. Dev. 51, 1468\u20131470 (2004)","journal-title":"IEEE Trans. Electron. Dev."},{"issue":"5","key":"1550_CR29","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1142\/S0218126617500840","volume":"26","author":"P Kumar","year":"2017","unstructured":"P. Kumar, R.K. Sharma, An energy efficient logic approach to implement CMOS full adder. J. Circuits Syst. Comput. 26(5), 1\u201320 (2017)","journal-title":"J. Circuits Syst. Comput."},{"key":"1550_CR30","doi-asserted-by":"publisher","DOI":"10.1002\/cta.2696","author":"M Kumar","year":"2019","unstructured":"M. Kumar, J.S. Ubhi, Design and analysis of CNFET based 10\u00a0T SRAM for high performance at nanoscale. Int. J. Circ. Theor. Appl. (2019). https:\/\/doi.org\/10.1002\/cta.2696","journal-title":"Int. J. Circ. Theor. Appl."},{"issue":"7","key":"1550_CR31","doi-asserted-by":"publisher","first-page":"2654","DOI":"10.1007\/s00034-016-0442-0","volume":"36","author":"R Lorenzo","year":"2016","unstructured":"R. Lorenzo, S. Chaudhury, Dynamic threshold sleep transistor technique for high speed and low leakage in CMOS circuits. Circuit Syst. Signal Process. 36(7), 2654\u20132671 (2016)","journal-title":"Circuit Syst. Signal Process."},{"key":"1550_CR32","doi-asserted-by":"publisher","first-page":"79","DOI":"10.1016\/j.mejo.2017.01.009","volume":"61","author":"AT Mahani","year":"2017","unstructured":"A.T. Mahani, P. Keshavarzian, A novel energy-efficient and high speed full adder using CNFET. Microelectron. J. 61, 79\u201388 (2017)","journal-title":"Microelectron. J."},{"issue":"09","key":"1550_CR33","doi-asserted-by":"publisher","first-page":"1550130","DOI":"10.1142\/S0218126615501303","volume":"24","author":"YS Mehrabani","year":"2015","unstructured":"Y.S. Mehrabani, M. Eshghi, High-speed, high-frequency and low-PDP, CNFET full adder cells. J. Circuits Syst. Comput. 24(09), 1550130 (2015)","journal-title":"J. Circuits Syst. Comput."},{"key":"1550_CR34","doi-asserted-by":"crossref","unstructured":"M.H. Moaiyeri, R.F. Mirzaee K. Navi, et al., Efficient CNFET-based ternary full adder cells for nanoelectronics. Nano-Micro Lett. 3, 43 (2011)","DOI":"10.1007\/BF03353650"},{"issue":"5","key":"1550_CR35","doi-asserted-by":"publisher","first-page":"566","DOI":"10.1109\/TVLSI.2002.801578","volume":"10","author":"A Morgenshtein","year":"2002","unstructured":"A. Morgenshtein, A. Fish, I.A. Wagner, Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits. IEEE Trans. Very Large Scale Integr. Syst. 10(5), 566\u2013581 (2002)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"issue":"8","key":"1550_CR36","doi-asserted-by":"publisher","first-page":"847","DOI":"10.1109\/TVLSI.2004.831474","volume":"12","author":"A Morgenshtein","year":"2004","unstructured":"A. Morgenshtein, M. Moreinis, R. Ginosar, Asynchronous gate-diffusion-input (GDI) circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(8), 847\u2013856 (2004)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"issue":"8","key":"1550_CR37","doi-asserted-by":"publisher","first-page":"1481","DOI":"10.1109\/TVLSI.2018.2820999","volume":"26","author":"H Naseri","year":"2018","unstructured":"H. Naseri, S. Timarchi, Low-power and fast full adder by exploring new XOR and XNOR gates. IEEE Trans. Very Large Scale Integr. Syst. 26(8), 1481\u20131493 (2018)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"issue":"19","key":"1550_CR38","doi-asserted-by":"publisher","first-page":"1395","DOI":"10.1587\/elex.6.1395","volume":"6","author":"K Navi","year":"2009","unstructured":"K. Navi, A. Momeni, F. Sharifi, P. Keshavarzian, Two novel ultra high speed carbon nanotube full-adder cells\u2019. IEICE Electron. Express 6(19), 1395\u20131401 (2009)","journal-title":"IEICE Electron. Express"},{"key":"1550_CR39","doi-asserted-by":"publisher","first-page":"841","DOI":"10.1109\/4.509871","volume":"31","author":"P Ng","year":"1996","unstructured":"P. Ng, P.T. Balsara, D. Steiss, Performance of CMOS differential circuits. IEEE J. Solid-State Circuits 31, 841\u2013846 (1996)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"1","key":"1550_CR40","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1142\/S0218126617500141","volume":"26","author":"MC Parameshwara","year":"2017","unstructured":"M.C. Parameshwara, H.C. Srinivasaiah, Low-power hybrid 1-bit full adder circuit for energy efficient arithmetic applications. J. Circuits Syst. Comput. 26(1), 1\u201315 (2017)","journal-title":"J. Circuits Syst. Comput."},{"key":"1550_CR41","doi-asserted-by":"publisher","first-page":"731","DOI":"10.1002\/cta.1886","volume":"42","author":"S Perri","year":"2014","unstructured":"S. Perri, M. Lanuzza, P. Corsonello, Design of high-speed low-power parallel-prefix adder trees in nanometer technologies. Int. J. Circ. Theor. Appl. 42, 731\u2013743 (2014)","journal-title":"Int. J. Circ. Theor. Appl."},{"key":"1550_CR42","volume-title":"Digital Integrated Circuits: A Design Perspective","author":"JM Rabaey","year":"2003","unstructured":"J.M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd edn. (Pearson Education, Delhi, 2003)","edition":"2"},{"key":"1550_CR43","doi-asserted-by":"publisher","unstructured":"Radhakrishnan, Low-voltage low-power CMOS full adder, in IEE Proceedings\u2014Circuits, Devices and Systems (2001). https:\/\/doi.org\/10.1049\/ip-cds:20010170","DOI":"10.1049\/ip-cds:20010170"},{"key":"1550_CR44","doi-asserted-by":"publisher","first-page":"28","DOI":"10.1016\/j.mee.2019.04.015","volume":"214","author":"R Shanmuganathan","year":"2019","unstructured":"R. Shanmuganathan, K. Brindhadevi, Comparative analysis of various types of multipliers for effective low power. Microelectron. Eng. 214, 28\u201337 (2019)","journal-title":"Microelectron. Eng."},{"key":"1550_CR45","unstructured":"Stanford University, Stanford CNFET Model\u2014HSPICE. https:\/\/nano.stanford.edu\/stanford-cnfet-model. Accessed on August 2017 (2017)"},{"key":"1550_CR46","doi-asserted-by":"publisher","first-page":"654","DOI":"10.1109\/TED.2009.2039529","volume":"57","author":"R Vaddi","year":"2010","unstructured":"R. Vaddi, S. Dasgupta, R.P. Agarwal, Device and circuit co-design robustness studies in the sub-threshold logic for ultralow-power applications for 32\u00a0nm CMOS. IEEE Trans. Electron. Dev. 57, 654\u2013664 (2010)","journal-title":"IEEE Trans. Electron. Dev."},{"key":"1550_CR47","unstructured":"M. Vesterbacka, A 14-transistor CMOS full adder with full voltage-swing nodes, in 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No. 99TH8461) (Taipei, Taiwan, 1999), pp. 713\u2013722"},{"issue":"2","key":"1550_CR48","first-page":"190","volume":"2","author":"S Wairya","year":"2011","unstructured":"S. Wairya, R.K. Nagaria, S. Tiwari, New design methodologies for high-speed low-voltage 1 bit CMOS full adder circuits. Int. J. Comput. Technol. Appl. 2(2), 190\u2013198 (2011)","journal-title":"Int. J. Comput. Technol. Appl."},{"key":"1550_CR49","doi-asserted-by":"publisher","first-page":"780","DOI":"10.1109\/4.303715","volume":"29","author":"J-M Wang","year":"1994","unstructured":"J.-M. Wang, S.-C. Fang, W.-S. Feng, New efficient designs for XOR and XNOR functions on the transistor level. IEEE J. Solid-State Circuits 29, 780\u2013786 (1994)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"1550_CR50","doi-asserted-by":"crossref","unstructured":"I. Wegener,  The Complexity of Boolean Functions (Wiley and B. G. Teubner, London, 1987)","DOI":"10.1007\/3-540-18170-9_185"},{"key":"1550_CR51","unstructured":"M. Zhang, J. Gu, C.-H. Chang, A novel hybrid pass logic with static CMOS output drive full-adder cell, in Proceedings of the 2003 International Symposium on Circuits and Systems (Bangkok, Thailand, 2003), pp. 317\u2013320"},{"key":"1550_CR52","doi-asserted-by":"crossref","unstructured":"N. Zhu, W.L. Goh, W. Zhang, K.S. Yeo, Z.H. Kong, Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing. IEEE Trans. Very Large Scale Integr. Syst. 18(8), 1225\u20131229 (2010)","DOI":"10.1109\/TVLSI.2009.2020591"},{"key":"1550_CR53","unstructured":"R. Zimmermann, Binary adder architectures for cell-based VLSI and their synthesis. PhD. thesis, Dipl. Informatik-Ing. ETH (1996)"},{"key":"1550_CR54","doi-asserted-by":"publisher","unstructured":"R. Zimmermann, W. Fichtner, Low-power logic styles: CMOS versus pass-transistor logic. IEEE J. Solid-State Circuits (1997). https:\/\/doi.org\/10.1109\/4.597298","DOI":"10.1109\/4.597298"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-020-01550-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-020-01550-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-020-01550-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,9,24]],"date-time":"2021-09-24T06:45:27Z","timestamp":1632465927000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-020-01550-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,24]]},"references-count":54,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2021,4]]}},"alternative-id":["1550"],"URL":"https:\/\/doi.org\/10.1007\/s00034-020-01550-3","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2020,9,24]]},"assertion":[{"value":"21 November 2019","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"10 September 2020","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"13 September 2020","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"24 September 2020","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}