{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,7]],"date-time":"2026-05-07T10:45:12Z","timestamp":1778150712829,"version":"3.51.4"},"reference-count":26,"publisher":"Springer Science and Business Media LLC","issue":"5","license":[{"start":{"date-parts":[[2020,11,19]],"date-time":"2020-11-19T00:00:00Z","timestamp":1605744000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2020,11,19]],"date-time":"2020-11-19T00:00:00Z","timestamp":1605744000000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2021,5]]},"DOI":"10.1007\/s00034-020-01578-5","type":"journal-article","created":{"date-parts":[[2020,11,19]],"date-time":"2020-11-19T23:48:46Z","timestamp":1605829726000},"page":"2135-2158","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":11,"title":["Design and Analysis of SRAM cell using Body Bias Controller for Low Power Applications"],"prefix":"10.1007","volume":"40","author":[{"given":"Jitendra Kumar","family":"Mishra","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bharat Bhushan","family":"Upadhyay","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Prasanna Kumar","family":"Misra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manish","family":"Goswami","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2020,11,19]]},"reference":[{"issue":"5","key":"1578_CR1","doi-asserted-by":"publisher","first-page":"726","DOI":"10.1109\/4.918909","volume":"36","author":"KI Agawa","year":"2001","unstructured":"K.I. Agawa, H. Hara, T. Takayanagi, T. Kuroda, A bitline leakage compensation scheme for low-voltage SRAMs. IEEE J. Solid-State Circuits 36(5), 726\u2013734 (2001)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"1578_CR2","doi-asserted-by":"crossref","unstructured":"M. Blagojevi\u0107, M. Cochet, B. Keller, P. Flatresse, A. Vladimirescu, B. Nikoli\u0107, A fast, flexible, positive and negative adaptive body-bias generator in 28\u00a0nm FDSOI, in 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), Honolulu, HI, pp. 1\u20132 (2016)","DOI":"10.1109\/VLSIC.2016.7573479"},{"issue":"3","key":"1578_CR3","doi-asserted-by":"publisher","first-page":"680","DOI":"10.1109\/JSSC.2006.891726","volume":"42","author":"BH Calhoun","year":"2007","unstructured":"B.H. Calhoun, A.P. Chandrakasan, A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation. IEEE J. Solid-State Circuits 42(3), 680\u2013688 (2007)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"9","key":"1578_CR4","doi-asserted-by":"publisher","first-page":"2498","DOI":"10.1109\/JSSC.2017.2701547","volume":"52","author":"MF Chang","year":"2017","unstructured":"M.F. Chang, C.F. Chen, T.H. Chang, C.C. Shuai, Y.Y. Wang, Y.J. Chen, H. Yamauchi, A compact-area low-VDD min 6T SRAM with improvement in cell stability, read speed and write margin using a dual-split-control-assist scheme. IEEE J. Solid-State Circuits 52(9), 2498\u20132514 (2017)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"1578_CR5","unstructured":"L. Chang, D.M. Fried, J. Hergenrother, J.W. Sleight, R.H. Dennard, R.K. Montoye, L. Sekaric, S.J. McNab, A.W. Topol, C.D. Adams, K.W. Guarini, Stable SRAM cell design for the 32\u00a0nm node and beyond, in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, IEEE, pp. 128\u2013129 (2005)"},{"issue":"5","key":"1578_CR6","doi-asserted-by":"publisher","first-page":"256","DOI":"10.1109\/JSSC.1974.1050511","volume":"9","author":"RH Dennard","year":"1974","unstructured":"R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Bassous, A.R. LeBlanc, Design of ion-implanted MOSFET\u2019s with very small physical dimensions. IEEE J. Solid-State Circuits 9(5), 256\u2013268 (1974)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"3","key":"1578_CR7","doi-asserted-by":"publisher","first-page":"734","DOI":"10.1587\/transfun.E97.A.734","volume":"97","author":"N Kamae","year":"2014","unstructured":"N. Kamae, A. Tsuchiya, H. Onodera, A body bias generator with low supply voltage for within-die variability compensation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97(3), 734\u2013740 (2014)","journal-title":"IEICE Trans. Fundam. Electron. Commun. Comput. Sci."},{"key":"1578_CR8","volume-title":"CMOS digital integrated circuit","author":"SM Kang","year":"2003","unstructured":"S.M. Kang, Y. Leblebici, CMOS digital integrated circuit (Tata Macgraw-Hill education, New York, 2003)"},{"issue":"25","key":"1578_CR9","doi-asserted-by":"publisher","first-page":"1423","DOI":"10.1049\/el.2018.7267","volume":"54","author":"CI Kumar","year":"2018","unstructured":"C.I. Kumar, B. Anand, Design of highly reliable energy-efficient SEU tolerant 10T SRAM cell. Electron. Lett. 54(25), 1423\u20131424 (2018)","journal-title":"Electron. Lett."},{"issue":"2","key":"1578_CR10","doi-asserted-by":"publisher","first-page":"385","DOI":"10.1007\/s00034-015-0086-5","volume":"35","author":"CB Kushwah","year":"2016","unstructured":"C.B. Kushwah, S.K. Vishvakarma, D. Dwivedi, Single-ended boost-less (SE-BL) 7T process tolerant SRAM design in sub-threshold regime for ultra-low-power applications. Circuits Syst. Signal Process. 35(2), 385\u2013407 (2016)","journal-title":"Circuits Syst. Signal Process."},{"issue":"9","key":"1578_CR11","doi-asserted-by":"publisher","first-page":"1964","DOI":"10.1109\/JSSC.2008.2001937","volume":"43","author":"YC Lai","year":"2008","unstructured":"Y.C. Lai, S.Y. Huang, X-calibration: a technique for combating excessive bitline leakage current in nanometer SRAM designs. IEEE J. Solid-State Circuits 43(9), 1964\u20131971 (2008)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"2","key":"1578_CR12","doi-asserted-by":"publisher","first-page":"315","DOI":"10.1007\/s10470-017-0997-0","volume":"92","author":"R Lorenzo","year":"2017","unstructured":"R. Lorenzo, S. Chaudhury, A novel 9T SRAM architecture for low leakage and high performance. Analog Integr. Circ. Sig. Process 92(2), 315\u2013325 (2017)","journal-title":"Analog Integr. Circ. Sig. Process"},{"issue":"1","key":"1578_CR13","doi-asserted-by":"publisher","first-page":"31","DOI":"10.1007\/s10470-019-01483-1","volume":"101","author":"JK Mishra","year":"2019","unstructured":"J.K. Mishra, H. Srivastava, P.K. Misra, M. Goswami, Analytical modeling and design of 9T SRAM cell with a leakage control technique. Analog Integr. Circ. Sig. Process 101(1), 31\u201343 (2019)","journal-title":"Analog Integr. Circ. Sig. Process"},{"key":"1578_CR14","doi-asserted-by":"crossref","unstructured":"J.K. Mishra, H. Srivastava, P.K. Misra, M. Goswami, A 40\u00a0nm low power high stable SRAM cell using separate read port and sleep transistor methodology, in IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Hyderabad, India (2018)","DOI":"10.1109\/iSES.2018.00011"},{"issue":"5","key":"1578_CR15","doi-asserted-by":"publisher","first-page":"1437","DOI":"10.1007\/s00034-015-0119-0","volume":"35","author":"M Moghaddam","year":"2016","unstructured":"M. Moghaddam, S. Timarchi, M.H. Moaiyeri, M. Eshghi, An ultra-low-power 9T SRAM cell based on threshold voltage techniques. Circuits Syst. Signal Process. 35(5), 1437\u20131455 (2016)","journal-title":"Circuits Syst. Signal Process."},{"issue":"1","key":"1578_CR16","doi-asserted-by":"publisher","first-page":"287","DOI":"10.1007\/s00034-018-0858-9","volume":"38","author":"S Naghizadeh","year":"2019","unstructured":"S. Naghizadeh, M. Gholami, Two novel ultra-low-power SRAM cells with separate read and write path. Circuits Syst. Signal Process. 38(1), 287\u2013303 (2019)","journal-title":"Circuits Syst. Signal Process."},{"issue":"6","key":"1578_CR17","doi-asserted-by":"publisher","first-page":"873","DOI":"10.1049\/iet-cds.2018.5193","volume":"13","author":"M Nobakht","year":"2019","unstructured":"M. Nobakht, R. Niaraki, A new 7T SRAM cell in sub-threshold region with a high performance and small area with bit interleaving capability. IET Circuits Devices Syst. 13(6), 873\u2013878 (2019)","journal-title":"IET Circuits Devices Syst."},{"issue":"10","key":"1578_CR18","doi-asserted-by":"publisher","first-page":"3241","DOI":"10.1109\/TCSI.2018.2811504","volume":"65","author":"H Okuhara","year":"2018","unstructured":"H. Okuhara, A.B. Ahmed, H. Amano, Digitally assisted on-chip body bias tuning scheme for ultra-low-power VLSI systems. IEEE Trans. Circuits Syst. I Regul. Pap. 65(10), 3241\u20133254 (2018)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"issue":"4","key":"1578_CR19","doi-asserted-by":"publisher","first-page":"549","DOI":"10.1109\/TCAD.2015.2474408","volume":"35","author":"S Pal","year":"2015","unstructured":"S. Pal, A. Islam, Variation tolerant differential 8T SRAM cell for ultralow power applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(4), 549\u2013558 (2015)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"issue":"7","key":"1578_CR20","doi-asserted-by":"publisher","first-page":"2357","DOI":"10.1109\/TED.2014.2321295","volume":"61","author":"G Pasandi","year":"2014","unstructured":"G. Pasandi, S.M. Fakhraie, An 8T low-voltage and low-leakage half-selection disturb-free SRAM using bulk-CMOS and FinFETs. IEEE Trans. Electron Devices 61(7), 2357\u20132363 (2014)","journal-title":"IEEE Trans. Electron Devices"},{"issue":"2","key":"1578_CR21","doi-asserted-by":"publisher","first-page":"196","DOI":"10.1109\/TVLSI.2007.893584","volume":"15","author":"M Sharifkhani","year":"2007","unstructured":"M. Sharifkhani, M. Sachdev, Segmental virtual ground architecture for low power embedded SRAM. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 15(2), 196\u2013205 (2007)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"3","key":"1578_CR22","doi-asserted-by":"publisher","first-page":"447","DOI":"10.1109\/TETC.2017.2721932","volume":"7","author":"G Torrens","year":"2017","unstructured":"G. Torrens, B. Alorda, C. Carmona, D. Malagon-Perianez, J. Segura, S.A. Bota, A 65-nm reliable 6T CMOS SRAM cell with minimum size transistors. IEEE Trans. Emerg. Top. Comput. 7(3), 447\u2013465 (2017)","journal-title":"IEEE Trans. Emerg. Top. Comput."},{"issue":"2","key":"1578_CR23","doi-asserted-by":"publisher","first-page":"441","DOI":"10.1109\/TCSI.2014.2360760","volume":"62","author":"B Wang","year":"2014","unstructured":"B. Wang, T.Q. Nguyen, A.T. Do, J. Zhou, M. Je, T.T.H. Kim, Design of an ultra-low voltage 9T SRAM with equalized bitline leakage and CAM-assisted energy efficiency improvement. IEEE Trans. Circuits Syst. I Regul. Pap. 62(2), 441\u2013448 (2014)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"issue":"4","key":"1578_CR24","doi-asserted-by":"publisher","first-page":"1365","DOI":"10.1109\/TAC.2019.2924176","volume":"65","author":"Y Wu","year":"2019","unstructured":"Y. Wu, A. Isidori, R. Lu, H.K. Khalil, Performance recovery of dynamic feedback-linearization methods for multivariable nonlinear systems. IEEE Trans. Autom. Control 65(4), 1365\u20131380 (2019)","journal-title":"IEEE Trans. Autom. Control"},{"issue":"5","key":"1578_CR25","doi-asserted-by":"publisher","first-page":"839","DOI":"10.1109\/JSSC.2003.810057","volume":"38","author":"Y Ye","year":"2003","unstructured":"Y. Ye, M. Khellah, D. Somasekhar, A. Farhang, V. De, A 6-GHz 16-kB L1 cache in a 100-nm dual-V\/sub T\/technology using a bitline leakage reduction (BLR) technique. IEEE J. Solid-State Circuits 38(5), 839\u2013842 (2003)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"10","key":"1578_CR26","doi-asserted-by":"publisher","first-page":"2726","DOI":"10.1109\/TCSI.2017.2700818","volume":"64","author":"N Zheng","year":"2017","unstructured":"N. Zheng, P. Mazumder, Modeling and mitigation of static noise margin variation in sub-threshold SRAM cells. IEEE Trans. Circuits Syst. I Regul. Pap. 64(10), 2726\u20132736 (2017)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-020-01578-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-020-01578-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-020-01578-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,2]],"date-time":"2021-04-02T07:08:32Z","timestamp":1617347312000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-020-01578-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11,19]]},"references-count":26,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2021,5]]}},"alternative-id":["1578"],"URL":"https:\/\/doi.org\/10.1007\/s00034-020-01578-5","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,11,19]]},"assertion":[{"value":"4 May 2020","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"15 October 2020","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"17 October 2020","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"19 November 2020","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}