{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,14]],"date-time":"2025-10-14T23:00:27Z","timestamp":1760482827868,"version":"3.37.3"},"reference-count":31,"publisher":"Springer Science and Business Media LLC","issue":"5","license":[{"start":{"date-parts":[[2020,11,20]],"date-time":"2020-11-20T00:00:00Z","timestamp":1605830400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2020,11,20]],"date-time":"2020-11-20T00:00:00Z","timestamp":1605830400000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2021,5]]},"DOI":"10.1007\/s00034-020-01588-3","type":"journal-article","created":{"date-parts":[[2020,11,20]],"date-time":"2020-11-20T05:34:59Z","timestamp":1605850499000},"page":"2507-2534","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Reliability Estimation of Logic Circuits at the Transistor Level"],"prefix":"10.1007","volume":"40","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8586-6281","authenticated-orcid":false,"given":"H.","family":"Jahanirad","sequence":"first","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2020,11,20]]},"reference":[{"key":"1588_CR1","unstructured":"A. Abdollahi, Probabilistic decision diagrams for exact probabilistic analysis, in Proceedings of IEEE\/ACM International Conference on CAD (2007), pp. 266\u2013272"},{"key":"1588_CR2","unstructured":"D. Bhaduri, S. Shukla, Nanoprism: a tool for evaluating granularity versus reliability tradeoffs in nano architectures, in Proceedings of ACM GLSVLSI, Boston, MA, April (2004), pp. 109\u2013112"},{"issue":"6","key":"1588_CR3","doi-asserted-by":"publisher","first-page":"10","DOI":"10.1109\/MM.2005.110","volume":"25","author":"S Borkar","year":"2005","unstructured":"S. Borkar, Designing reliable systems from unreliable components: the challenges of transistor variability and degradation. IEEE Micro 25(6), 10\u201316 (2005)","journal-title":"IEEE Micro"},{"issue":"3","key":"1588_CR4","doi-asserted-by":"publisher","first-page":"216","DOI":"10.1109\/MDT.2004.8","volume":"21","author":"MA Breuer","year":"2004","unstructured":"M.A. Breuer, S.K. Gupta, T.M. Mak, Defect and error tolerance in the presence of massive numbers of defects. IEEE Des. Test. Comp. 21(3), 216\u2013227 (2004)","journal-title":"IEEE Des. Test. Comp."},{"key":"1588_CR5","unstructured":"H. Chen, J. Han, F. Lombardi, A transistor-level stochastic approach for evaluating the reliability of digital nanometric CMOS circuits, in Proceedings of IEEE International Symposium on DFT in VLSI and Nanotechnology Systems (2011), pp. 60\u201367"},{"key":"1588_CR6","doi-asserted-by":"publisher","first-page":"107","DOI":"10.1016\/j.vlsi.2015.02.005","volume":"50","author":"C Chen","year":"2015","unstructured":"C. Chen, R. Xiao, A fast model for analysis and improvement of gate-level circuit reliability. Integr. VLSI J. 50, 107\u2013115 (2015)","journal-title":"Integr. VLSI J."},{"issue":"3","key":"1588_CR7","doi-asserted-by":"publisher","first-page":"392","DOI":"10.1109\/TCAD.2009.2012530","volume":"28","author":"MR Choudhury","year":"2009","unstructured":"M.R. Choudhury, K. Mohanram, Reliability analysis of logic circuits. IEEE Trans. CAD 28(3), 392\u2013405 (2009)","journal-title":"IEEE Trans. CAD"},{"issue":"2\u20133","key":"1588_CR8","doi-asserted-by":"publisher","first-page":"393","DOI":"10.1016\/0004-3702(90)90060-D","volume":"42","author":"GF Cooper","year":"1990","unstructured":"G.F. Cooper, The computational complexity of probabilistic inference using Bayesian belief networks. Artif. Intell. 42(2\u20133), 393\u2013405 (1990)","journal-title":"Artif. Intell."},{"key":"1588_CR9","doi-asserted-by":"crossref","unstructured":"T. Cui, J. Li, A. Shafaei, S. Nazarian, M. Pedram, An efficient timing analysis model for 6T FinFET SRAM using current-based method, in 2016 17th International Symposium on Quality Electronic Design (ISQED),2016 (2016, March), pp. 263\u2013268","DOI":"10.1109\/ISQED.2016.7479211"},{"issue":"3","key":"1588_CR10","doi-asserted-by":"publisher","first-page":"935","DOI":"10.1109\/TR.2015.2440234","volume":"64","author":"AH El-Maleh","year":"2015","unstructured":"A.H. El-Maleh, K. Daud, Simulation-based method for synthesizing soft error tolerant combinational circuits. IEEE Trans. Reliab. 64(3), 935\u2013948 (2015)","journal-title":"IEEE Trans. Reliab."},{"issue":"6","key":"1588_CR11","doi-asserted-by":"publisher","first-page":"570","DOI":"10.1049\/iet-cdt.2008.0133","volume":"3","author":"AH El-Maleh","year":"2009","unstructured":"A.H. El-Maleh, B.M. Al-Hashemi, A. Melouki, F. Khan, Defect-tolerant N2-transistor structure for reliable nanoelectronic designs. IET Comput. Dig. Tech. 3(6), 570\u2013580 (2009)","journal-title":"IET Comput. Dig. Tech."},{"key":"1588_CR12","doi-asserted-by":"publisher","first-page":"1215","DOI":"10.1016\/j.microrel.2010.07.058","volume":"50","author":"JT Flaquer","year":"2010","unstructured":"J.T. Flaquer, J.M. Daveau, L. Naviner, P. Roche, Fast reliability analysis of combinatorial logic circuits using conditional probabilities. Micro Reliab. 50, 1215\u20131218 (2010)","journal-title":"Micro Reliab."},{"key":"1588_CR13","doi-asserted-by":"publisher","first-page":"1586","DOI":"10.1016\/j.microrel.2008.07.002","volume":"48","author":"DT Franco","year":"2008","unstructured":"D.T. Franco, M.C. Vasconcelos, L. Naviner, J.F. Naviner, Signal probability for reliability evaluation of logic circuits. Micro Reliab. 48, 1586\u20131591 (2008)","journal-title":"Micro Reliab."},{"issue":"2","key":"1588_CR14","doi-asserted-by":"publisher","first-page":"468","DOI":"10.1016\/j.microrel.2010.07.154","volume":"51","author":"J Han","year":"2011","unstructured":"J. Han, H. Chen, E. Boykin, J. Fortes, Reliability evaluation of logic circuits using probabilistic gate models. Micro Reliab. 51(2), 468\u2013476 (2011)","journal-title":"Micro Reliab."},{"issue":"3","key":"1588_CR15","doi-asserted-by":"publisher","first-page":"538","DOI":"10.1109\/TR.2011.2161032","volume":"60","author":"W Ibrahim","year":"2011","unstructured":"W. Ibrahim, V. Beiu, Using Bayesian networks to accurately calculate the reliability of complementary metal oxide semiconductor gates. IEEE Trans. Reliab. 60(3), 538\u2013549 (2011)","journal-title":"IEEE Trans. Reliab."},{"issue":"3","key":"1588_CR16","doi-asserted-by":"publisher","first-page":"675","DOI":"10.1109\/TR.2012.2206249","volume":"61","author":"W Ibrahim","year":"2012","unstructured":"W. Ibrahim, V. Beiu, A. Beg, Optimum reliability sizing for complementary metal oxide semiconductor gates. IEEE Trans. Reliab. 61(3), 675\u2013686 (2012)","journal-title":"IEEE Trans. Reliab."},{"issue":"5","key":"1588_CR17","doi-asserted-by":"publisher","first-page":"1217","DOI":"10.1109\/TC.2014.2315633","volume":"64","author":"W Ibrahim","year":"2014","unstructured":"W. Ibrahim, S. Marwa, J.W. Chinneck, Accurate and efficient estimation of logic circuits reliability bounds. IEEE Trans. Comput. 64(5), 1217\u20131229 (2014)","journal-title":"IEEE Trans. Comput."},{"issue":"1","key":"1588_CR18","doi-asserted-by":"publisher","first-page":"343","DOI":"10.1007\/s10825-018-1288-4","volume":"18","author":"H Jahanirad","year":"2019","unstructured":"H. Jahanirad, Efficient reliability evaluation of combinational and sequential logic circuits. J. Comput. Electron. 18(1), 343\u2013355 (2019)","journal-title":"J. Comput. Electron."},{"issue":"4","key":"1588_CR19","doi-asserted-by":"publisher","first-page":"927","DOI":"10.1109\/TVLSI.2018.2886027","volume":"27","author":"H Jahanirad","year":"2019","unstructured":"H. Jahanirad, CC-SPRA: correlation coefficients approach for signal probability-based reliability analysis. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 27(4), 927\u2013939 (2019)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"5","key":"1588_CR20","doi-asserted-by":"publisher","first-page":"1250040-(1-17)","DOI":"10.1142\/S0218126612500405","volume":"21","author":"H Jahanirad","year":"2012","unstructured":"H. Jahanirad, K. Mohammadi, Sequential logic circuits reliability analysis. J. Circuits Syst. Comput. 21(5), 1250040-(1-17) (2012)","journal-title":"J. Circuits Syst. Comput."},{"issue":"1","key":"1588_CR21","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1297666.1297674","volume":"13","author":"S Krishnaswamy","year":"2008","unstructured":"S. Krishnaswamy, G.V. Viamonets, I.L. Markov, J.P. Hayes, Probabilistic transfer matrices in symbolic reliability analysis of logic circuits. ACM Trans. Des. Autom. Electron. Syst. 13(1), 1\u201335 (2008)","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"key":"1588_CR22","unstructured":"J. Liang, J. Han, L. Chen, F. Lombardi, Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs, in Proceedings of IEEE\/ACM International Symposium on Nanoscale Architectures (2012), pp. 131\u2013138"},{"issue":"2","key":"1588_CR23","doi-asserted-by":"publisher","first-page":"217","DOI":"10.1109\/TNANO.2009.2036845","volume":"10","author":"S Lin","year":"2011","unstructured":"S. Lin, Y.B. Kim, F. Lombardi, CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol. 10(2), 217\u2013225 (2011)","journal-title":"IEEE Trans. Nanotechnol."},{"issue":"5537","key":"1588_CR24","doi-asserted-by":"publisher","first-page":"2044","DOI":"10.1126\/science.293.5537.2044","volume":"293","author":"JD Meindl","year":"2001","unstructured":"J.D. Meindl, Q. Chen, J.A. Davis, Limits on silicon nanoelectronics for terascale integration. Science 293(5537), 2044\u20132049 (2001)","journal-title":"Science"},{"key":"1588_CR25","unstructured":"N. Mohyudin, E. Pakbaznia, M. Pedam, Probabilistic error propagation in logic circuits using the Boolean difference calcules, in IEEE International Conference on Computer Design, Lake Tahoe, CA (2008), pp. 7\u201313"},{"key":"1588_CR26","unstructured":"K. Nicolic, A.S. Sadek, M. Forshaw, Architectures for reliable computing with unreliable nanodevices, in Proceedings of IEEE Conference on Nanotechnology, Maui, HI, USA (2001), pp. 254\u2013259"},{"issue":"1","key":"1588_CR27","doi-asserted-by":"publisher","first-page":"55","DOI":"10.1109\/TVLSI.2008.2003167","volume":"17","author":"T Rejimon","year":"2009","unstructured":"T. Rejimon, K. Lingasubramanian, S. Bhanja, Probabilistic error modeling for nano-domain logic circuits. IEEE Trans. VLSI 17(1), 55\u201365 (2009)","journal-title":"IEEE Trans. VLSI"},{"key":"1588_CR28","doi-asserted-by":"publisher","first-page":"113309","DOI":"10.1016\/j.eswa.2020.113309","volume":"149","author":"MA Savari","year":"2020","unstructured":"M.A. Savari, H. Jahanirad, NN-SSTA: a deep neural network approach for statistical static timing analysis. Expert Syst. Appl. 149, 113309 (2020)","journal-title":"Expert Syst. Appl."},{"issue":"4","key":"1588_CR29","doi-asserted-by":"publisher","first-page":"334","DOI":"10.1109\/MDT.2008.113","volume":"25","author":"NR Shanbhag","year":"2008","unstructured":"N.R. Shanbhag, S. Mitra, G. de Veciana, M. Orshansky, R. Marculescu, J. Roychowdhury, D. Jones, J.M. Rabaey, The search for alternative computational paradigms. IEEE Des. Test. Comput. 25(4), 334\u2013344 (2008)","journal-title":"IEEE Des. Test. Comput."},{"issue":"2","key":"1588_CR30","doi-asserted-by":"publisher","first-page":"440","DOI":"10.1109\/TR.2016.2642168","volume":"66","author":"B Srinivasu","year":"2017","unstructured":"B. Srinivasu, K. Siridharan, A transistor-level probabilistic approach for reliability analysis of arithmetic circuits with applications to emerging technologies. IEEE Trans. Reliab. 66(2), 440\u2013457 (2017)","journal-title":"IEEE Trans. Reliab."},{"key":"1588_CR31","doi-asserted-by":"crossref","first-page":"43","DOI":"10.1515\/9781400882618-003","volume-title":"Automata Studies","author":"J Von Neuman","year":"1956","unstructured":"J. Von Neuman, Probabilistic logics and synthesis of reliable organisms from unreliable components, in Automata Studies, ed. by C.E. Shannon, J. McCarthy (Princeton Press, Princeton, 1956), pp. 43\u201398"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-020-01588-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-020-01588-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-020-01588-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,14]],"date-time":"2021-04-14T22:17:01Z","timestamp":1618438621000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-020-01588-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11,20]]},"references-count":31,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2021,5]]}},"alternative-id":["1588"],"URL":"https:\/\/doi.org\/10.1007\/s00034-020-01588-3","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2020,11,20]]},"assertion":[{"value":"20 October 2019","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"23 October 2020","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"27 October 2020","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"20 November 2020","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}