{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,3]],"date-time":"2025-04-03T09:04:19Z","timestamp":1743671059942,"version":"3.37.3"},"reference-count":25,"publisher":"Springer Science and Business Media LLC","issue":"8","license":[{"start":{"date-parts":[[2021,2,16]],"date-time":"2021-02-16T00:00:00Z","timestamp":1613433600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,2,16]],"date-time":"2021-02-16T00:00:00Z","timestamp":1613433600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2021,8]]},"DOI":"10.1007\/s00034-021-01664-2","type":"journal-article","created":{"date-parts":[[2021,2,19]],"date-time":"2021-02-19T13:01:55Z","timestamp":1613739715000},"page":"4089-4105","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":6,"title":["CNFET-Based Ultra-Low-Power Dual-$$V_{DD}$$ Ternary Half Adder"],"prefix":"10.1007","volume":"40","author":[{"given":"Abhay S.","family":"Vidhyadharan","sequence":"first","affiliation":[]},{"given":"Kasthuri","family":"Bha","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1855-666X","authenticated-orcid":false,"given":"Sanjay","family":"Vidhyadharan","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2021,2,16]]},"reference":[{"key":"1664_CR1","doi-asserted-by":"crossref","unstructured":"N.H. Bastani, M.H. Moaiyeri, K. Navi, Circuits. Syst. Signal Process. 37(5), 1863 (2018)","DOI":"10.1007\/s00034-017-0627-1"},{"key":"1664_CR2","doi-asserted-by":"publisher","unstructured":"J. Deng, H.P. Wong, IEEE Trans. Electron. Devices 54(12), 3186 (2007). https:\/\/doi.org\/10.1109\/TED.2007.909030","DOI":"10.1109\/TED.2007.909030"},{"key":"1664_CR3","doi-asserted-by":"publisher","first-page":"3195","DOI":"10.1109\/TED.2007.909043","volume":"54","author":"J Deng","year":"2007","unstructured":"J. Deng, H.P. Wong, EIEEE Trans. Electron. Devices 54, 3195 (2007)","journal-title":"EIEEE Trans. Electron. Devices"},{"key":"1664_CR4","doi-asserted-by":"publisher","unstructured":"A.\u00a0Doostaregan, A.\u00a0Abrishamifar, Circuits Syst. Signal Process. (2020). https:\/\/doi.org\/10.1007\/s00034-020-01400-2","DOI":"10.1007\/s00034-020-01400-2"},{"key":"1664_CR5","doi-asserted-by":"crossref","unstructured":"O. Hashemipour, M.H. Moaiyeri, R.F. Mirzaee, A. Doostaregan, K. Navi, IET Comput. Digit. Tech. 7(4), 167 (2013)","DOI":"10.1049\/iet-cdt.2013.0023"},{"key":"1664_CR6","unstructured":"ITRS. International Technology Roadmap for Semiconductors. http:\/\/www.itrs2.net\/ (2005)"},{"key":"1664_CR7","doi-asserted-by":"publisher","unstructured":"Y.\u00a0Kang, J.\u00a0Kim, S.\u00a0Kim, S.\u00a0Shin, E.\u00a0Jang, J.W. Jeong, K.R. Kim, S.\u00a0Kang, in 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL), pp. 25\u201330 (2017). https:\/\/doi.org\/10.1109\/ISMVL.2017.52","DOI":"10.1109\/ISMVL.2017.52"},{"key":"1664_CR8","doi-asserted-by":"publisher","unstructured":"S.\u00a0Karmakar, J.A. Chandy, F.C. Jain, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21(5), 793 (2013). https:\/\/doi.org\/10.1109\/TVLSI.2012.2198248","DOI":"10.1109\/TVLSI.2012.2198248"},{"key":"1664_CR9","doi-asserted-by":"crossref","unstructured":"P. Keshavarzian, R. Sarikhani, Circuits. Syst. Signal Process. 33(3), 665 (2014)","DOI":"10.1007\/s00034-013-9672-6"},{"key":"1664_CR10","doi-asserted-by":"publisher","unstructured":"S.\u00a0Kim, T.\u00a0Lim, S.\u00a0Kang, in 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 476\u2013481 (2018). https:\/\/doi.org\/10.1109\/ASPDAC.2018.8297369","DOI":"10.1109\/ASPDAC.2018.8297369"},{"key":"1664_CR11","doi-asserted-by":"publisher","unstructured":"S. Lin, Y. Kim, F. Lombardi, IEEE Trans. Nanotechnol. 10(2), 217 (2011). https:\/\/doi.org\/10.1109\/TNANO.2009.2036845","DOI":"10.1109\/TNANO.2009.2036845"},{"key":"1664_CR12","doi-asserted-by":"crossref","unstructured":"M.H. Moaiyeri, S. Sedighiani, F. Sharifi, K. Navi, Front. Inf. Technol. Electron. Eng. 17(10), 1056 (2016)","DOI":"10.1631\/FITEE.1500214"},{"key":"1664_CR13","doi-asserted-by":"publisher","unstructured":"J.\u00a0Mounika, K.\u00a0Ramanujam, M.Z. Jahangir, in 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT), pp. 1\u20135 (2016). https:\/\/doi.org\/10.1109\/ICCPCT.2016.7530153","DOI":"10.1109\/ICCPCT.2016.7530153"},{"key":"1664_CR14","doi-asserted-by":"crossref","unstructured":"S.L. Murotiya, A. Gupta, Arab. J. Sci. Eng. 39(11), 7839 (2014)","DOI":"10.1007\/s13369-014-1350-x"},{"key":"1664_CR15","doi-asserted-by":"publisher","unstructured":"S.K. Sahoo, G. Akhilesh, R. Sahoo, M. Muglikar, IEEE Trans. Nanotechnol. 16(3), 368 (2017). https:\/\/doi.org\/10.1109\/TNANO.2017.2649548","DOI":"10.1109\/TNANO.2017.2649548"},{"key":"1664_CR16","doi-asserted-by":"crossref","unstructured":"T. Sharma, L. Kumre, Circuits. Syst. Signal Process. 38(10), 4640 (2019)","DOI":"10.1007\/s00034-019-01070-9"},{"key":"1664_CR17","doi-asserted-by":"publisher","unstructured":"S.\u00a0Shin, J.W. Jeong, E.\u00a0Jang, K.R. Kim, in 2017 IEEE 17th International Conference on Nanotechnology (IEEE-NANO), pp. 13\u201316 (2017). https:\/\/doi.org\/10.1109\/NANO.2017.8117372","DOI":"10.1109\/NANO.2017.8117372"},{"key":"1664_CR18","doi-asserted-by":"publisher","unstructured":"B. Srinivasu, K. Sridharan, IEEE Trans. Circuits Syst. I: Reg. Pap. 64(8), 2146 (2017). https:\/\/doi.org\/10.1109\/TCSI.2017.2686446","DOI":"10.1109\/TCSI.2017.2686446"},{"key":"1664_CR19","doi-asserted-by":"crossref","unstructured":"S. Tabrizchi, N. Azimi, K. Navi, Front. Inf. Technol. Electron. Eng. 18(3), 423 (2017)","DOI":"10.1631\/FITEE.1500366"},{"key":"1664_CR20","doi-asserted-by":"publisher","unstructured":"S.\u00a0Vidhyadharan, R.\u00a0Ramakant, A.S. Vidhyadharan, A.K. Shyam, M.P. Hirpara, S.S. Dan, in 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), pp. 401\u2013406 (2019). https:\/\/doi.org\/10.1109\/VLSID.2019.00087","DOI":"10.1109\/VLSID.2019.00087"},{"key":"1664_CR21","doi-asserted-by":"crossref","unstructured":"S.\u00a0Vidhyadharan, R.\u00a0Yadav, G.\u00a0Akhilesh, V.\u00a0Gupta, A.\u00a0Ravi, S.S. Dan, in The Physics of Semiconductor Devices, ed. by R.K. Sharma, D.\u00a0Rawal (Springer International Publishing, 2019), pp. 619\u2013628","DOI":"10.1007\/978-3-319-97604-4_96"},{"key":"1664_CR22","unstructured":"S. Vidhyadharan, R. Yadav, S. Hariprasad, S.S. Dan, Analog Integrated Circuits and Signal Processing (2019)"},{"key":"1664_CR23","doi-asserted-by":"publisher","unstructured":"S. Vidhyadharan, R. Yadav, S. Hariprasad, S.S. Dan, Springer Analog Integrated Circuits & Signal Processing (2019). https:\/\/doi.org\/10.1007\/s10470-019-01487-x","DOI":"10.1007\/s10470-019-01487-x"},{"key":"1664_CR24","doi-asserted-by":"publisher","unstructured":"C.K. Vudadha, M.\u00a0Srinivas, in 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), pp. 192\u2013197 (2018). https:\/\/doi.org\/10.1109\/ISMVL.2018.00041. ISSN: 2378-2226","DOI":"10.1109\/ISMVL.2018.00041"},{"issue":"12","key":"1664_CR25","doi-asserted-by":"publisher","first-page":"4313","DOI":"10.1109\/TCSI.2018.2838258","volume":"65","author":"C Vudadha","year":"2018","unstructured":"C. Vudadha, A. Surya, S. Agrawal, M.B. Srinivas, IEEE Trans. Circuits Syst. I: Reg. Pap. 65(12), 4313 (2018)","journal-title":"IEEE Trans. Circuits Syst. I: Reg. Pap."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-021-01664-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-021-01664-2\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-021-01664-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,7,12]],"date-time":"2021-07-12T11:11:40Z","timestamp":1626088300000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-021-01664-2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2,16]]},"references-count":25,"journal-issue":{"issue":"8","published-print":{"date-parts":[[2021,8]]}},"alternative-id":["1664"],"URL":"https:\/\/doi.org\/10.1007\/s00034-021-01664-2","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2021,2,16]]},"assertion":[{"value":"9 May 2020","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"24 January 2021","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"29 January 2021","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"16 February 2021","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}