{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,14]],"date-time":"2026-02-14T07:40:26Z","timestamp":1771054826598,"version":"3.50.1"},"reference-count":25,"publisher":"Springer Science and Business Media LLC","issue":"12","license":[{"start":{"date-parts":[[2021,6,28]],"date-time":"2021-06-28T00:00:00Z","timestamp":1624838400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,6,28]],"date-time":"2021-06-28T00:00:00Z","timestamp":1624838400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61771176, 61801154, 61271064"],"award-info":[{"award-number":["61771176, 61801154, 61271064"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2021,12]]},"DOI":"10.1007\/s00034-021-01770-1","type":"journal-article","created":{"date-parts":[[2021,6,28]],"date-time":"2021-06-28T16:04:10Z","timestamp":1624896250000},"page":"5825-5846","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":53,"title":["Design of Memristor-Based Combinational Logic Circuits"],"prefix":"10.1007","volume":"40","author":[{"given":"Gongzhi","family":"Liu","sequence":"first","affiliation":[]},{"given":"Shuhang","family":"Shen","sequence":"additional","affiliation":[]},{"given":"Peipei","family":"Jin","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6777-8234","authenticated-orcid":false,"given":"Guangyi","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Yan","family":"Liang","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2021,6,28]]},"reference":[{"key":"1770_CR1","first-page":"649","volume":"03","author":"GN Balaji","year":"2016","unstructured":"G.N. Balaji, V. Aathira, K. Ambhikavathi et al., Combinational circuits using transmission gate logic for power optimization. Int. Res. J. Eng. Technol. 03, 649\u2013654 (2016)","journal-title":"Int. Res. J. Eng. Technol."},{"key":"1770_CR2","doi-asserted-by":"publisher","first-page":"214","DOI":"10.1016\/j.mejo.2014.12.006","volume":"46","author":"K Cho","year":"2015","unstructured":"K. Cho, S.J. Lee, K. Eshraghian, Memristor-CMOS logic and digital computational components. Microelect. J. 46, 214\u2013220 (2015)","journal-title":"Microelect. J."},{"key":"1770_CR3","doi-asserted-by":"publisher","first-page":"507","DOI":"10.1109\/TCT.1971.1083337","volume":"18","author":"LO Chua","year":"1971","unstructured":"L.O. Chua, Memristor: the missing circuit element. IEEE Trans. Circuit Th. 18, 507\u2013519 (1971)","journal-title":"IEEE Trans. Circuit Th."},{"key":"1770_CR4","doi-asserted-by":"crossref","unstructured":"N. Z. B. Haron, S. Hamdioui, Why is CMOS scaling coming to an END? in The 3rd IEEE International Design and Test Workshop (2008), pp. 98\u2013103","DOI":"10.1109\/IDT.2008.4802475"},{"key":"1770_CR5","doi-asserted-by":"publisher","first-page":"254","DOI":"10.1109\/JSSC.2002.807409","volume":"38","author":"CH Huang","year":"2003","unstructured":"C.H. Huang, J.S. Wang, High-performance and power-efficient CMOS comparators. IEEE J. Solid State Circuit. 38, 254\u2013256 (2003)","journal-title":"IEEE J. Solid State Circuit."},{"issue":"61","key":"1770_CR6","doi-asserted-by":"crossref","first-page":"895","DOI":"10.1109\/TCSII.2014.2357292","volume":"II","author":"S Kvatinsky","year":"2014","unstructured":"S. Kvatinsky, D. Belousov, S. Liman et al., MAGIC-memristor-aided logic. IEEE Trans. Circuits Syst. II(61), 895\u2013899 (2014)","journal-title":"IEEE Trans. Circuits Syst."},{"key":"1770_CR7","doi-asserted-by":"crossref","unstructured":"S. Kvatinsky, N. Wald, G. Satat, et al., MRL\u2013Memristor Ratioed Logic, in 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications (2012), pp. 1\u20136","DOI":"10.1109\/CNNA.2012.6331426"},{"key":"1770_CR8","doi-asserted-by":"publisher","first-page":"2403","DOI":"10.1109\/JSSC.2004.835641","volume":"39","author":"M Meghelli","year":"2004","unstructured":"M. Meghelli, A 132-Gb\/s 4:1 multiplexer in 0.13-\u03bcm SiGe-bipolar technology. IEEE J. Solid State Circuits. 39, 2403\u20132407 (2004)","journal-title":"IEEE J. Solid State Circuits."},{"key":"1770_CR9","doi-asserted-by":"crossref","unstructured":"A. S. Oblea, A. Timilsina, D. Moore, et al., Silver chalcogenide based memristor devices, in 2010 International Joint Conference on Neural Networks (2010), pp. 1\u20133","DOI":"10.1109\/IJCNN.2010.5596775"},{"key":"1770_CR10","first-page":"168","volume":"1","author":"S Panda","year":"2012","unstructured":"S. Panda, A. Banerjee, B. Maji et al., Power and delay comparison in between different types of full adder circuits. Int. J. Adv. Res. Elect. Elect. Instrum. Eng. 1, 168\u2013172 (2012)","journal-title":"Int. J. Adv. Res. Elect. Elect. Instrum. Eng."},{"key":"1770_CR11","doi-asserted-by":"publisher","first-page":"35","DOI":"10.1038\/s41565-018-0302-0","volume":"14","author":"S Pi","year":"2019","unstructured":"S. Pi, C. Li, H. Jiang et al., Memristor crossbar arrays with 6-nm half-pitch and 2-nm critical dimension. Nat. Nanotechnol. 14, 35\u201340 (2019)","journal-title":"Nat. Nanotechnol."},{"key":"1770_CR12","doi-asserted-by":"crossref","unstructured":"S. G. Rohani, N. Taherinejad, D. Radakovits, A semiparallel full-adder in IMPLY logic. IEEE Trans. Very Large Scale Integ. Syst. 28, 297\u2013301 (2020)","DOI":"10.1109\/TVLSI.2019.2936873"},{"key":"1770_CR13","doi-asserted-by":"crossref","unstructured":"A. Singh, Memristor based XNOR for high speed area efficient 1-bit Full Adder, in 2017 IEEE International Conference on Computing, Communication and Automation (2017), pp. 1549\u20131553","DOI":"10.1109\/CCAA.2017.8230048"},{"key":"1770_CR14","first-page":"1","volume":"1506","author":"T Singh","year":"2015","unstructured":"T. Singh, Hybrid memristor-CMOS (MeMOS) based logic gates and adder circuits. Comput. Sci. 1506, 1\u201311 (2015)","journal-title":"Comput. Sci."},{"key":"1770_CR15","doi-asserted-by":"publisher","first-page":"182","DOI":"10.1080\/03772063.2018.1486741","volume":"33","author":"A Singh","year":"2020","unstructured":"A. Singh, Design and analysis of memristor-based combinational circuits. IETE J. Res. 33, 182\u2013191 (2020)","journal-title":"IETE J. Res."},{"key":"1770_CR16","doi-asserted-by":"publisher","first-page":"80","DOI":"10.1038\/nature06932","volume":"453","author":"DB Strukov","year":"2008","unstructured":"D.B. Strukov, G.S. Snider, D.R. Stewart, The missing memristor found. Nature 453, 80\u201383 (2008)","journal-title":"Nature"},{"key":"1770_CR17","doi-asserted-by":"crossref","unstructured":"M. Teimoory, A. Amirsoleimani, A. Ahmadi, et al., A hybrid memristor-CMOS multiplier design based on memristive universal logic gates, in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (2017), pp. 1422\u20131425","DOI":"10.1109\/MWSCAS.2017.8053199"},{"key":"1770_CR18","doi-asserted-by":"publisher","first-page":"2842","DOI":"10.1109\/TVLSI.2018.2816023","volume":"26","author":"HP Wang","year":"2018","unstructured":"H.P. Wang, C.C. Lin, C.C. Wu et al., On synthesizing memristor-based logic circuits with minimal operational pulses. IEEE T. VLSI Syst. 26, 2842\u20132852 (2018)","journal-title":"IEEE T. VLSI Syst."},{"key":"1770_CR19","doi-asserted-by":"crossref","unstructured":"X. P. Wang, R. Yang, Q. Chen, et al., An improved memristor-CMOS XOR logic gate and a novel full adder, in 2017 Ninth International Conference on Advanced Computational Intelligence (2017), pp. 7\u201311","DOI":"10.1109\/ICACI.2017.7974477"},{"key":"1770_CR20","doi-asserted-by":"crossref","unstructured":"L. Xie, H. A. D. Nguyen, M. Taoui, et al., A mapping methodology of boolean logic circuits on memristor crossbar. IEEE Trans. Comput. Aided Des. Integ. Circuits Syst. 37, 311\u2013323 (2018)","DOI":"10.1109\/TCAD.2017.2695880"},{"key":"1770_CR21","unstructured":"X. Y. Xu, X. L. Cui, M. Y. Luo, et al., Design of hybrid memristor-MOS XOR and XNOR logic gates, in 2017 International Conference on Electron Devices and Solid-State Circuits (2017), pp. 1\u20132"},{"key":"1770_CR22","doi-asserted-by":"publisher","first-page":"1201","DOI":"10.1109\/TCAD.2013.2252057","volume":"32","author":"C Yakopcic","year":"2013","unstructured":"C. Yakopcic, T.M. Taha, G. Subramanyam et al., Generalized memristive device SPICE model and its application in circuit design, IEEE Trans. Comput. Aided Des. Integ. Circuits Syst. 32, 1201\u20131214 (2013)","journal-title":"Comput. Aided Des. Integ. Circuits Syst."},{"key":"1770_CR23","doi-asserted-by":"crossref","unstructured":"X. H. Yang, A. Adeyemo, A. Bala, et al., Novel memristive logic architectures, in The Proceedings of 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (2016), pp. 196\u2013199","DOI":"10.1109\/PATMOS.2016.7833687"},{"key":"1770_CR24","doi-asserted-by":"crossref","unstructured":"L. Yao, P. Liu, J. Wu, et al. Integrating two logics into one crossbar array for logic gate design. IEEE Trans. Circuits Syst. II Exp. Briefs (2021)","DOI":"10.1109\/TCSII.2021.3071386"},{"key":"1770_CR25","doi-asserted-by":"crossref","unstructured":"Y. X. Zhou, Y. Li, L. Xu, et al., A hybrid memristor-CMOS XOR gate for nonvolatile logic computation. Phys. Status Solidi A Appl. Mater. Sci. 213, 1050\u20131054 (2016)","DOI":"10.1002\/pssa.201532872"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-021-01770-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-021-01770-1\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-021-01770-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T20:05:39Z","timestamp":1672603539000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-021-01770-1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6,28]]},"references-count":25,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2021,12]]}},"alternative-id":["1770"],"URL":"https:\/\/doi.org\/10.1007\/s00034-021-01770-1","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,6,28]]},"assertion":[{"value":"27 September 2020","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"12 June 2021","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"14 June 2021","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"28 June 2021","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}