{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,4]],"date-time":"2025-11-04T16:13:03Z","timestamp":1762272783715,"version":"3.37.3"},"reference-count":36,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2021,9,16]],"date-time":"2021-09-16T00:00:00Z","timestamp":1631750400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,9,16]],"date-time":"2021-09-16T00:00:00Z","timestamp":1631750400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/501100003593","name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003593","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004263","name":"Funda\u00e7\u00e3o de Amparo \u00e0 Pesquisa do Estado do Rio Grande do Sul","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004263","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002322","name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002322","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2022,3]]},"DOI":"10.1007\/s00034-021-01839-x","type":"journal-article","created":{"date-parts":[[2021,9,16]],"date-time":"2021-09-16T16:06:39Z","timestamp":1631808399000},"page":"1577-1595","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["The 4-2 Fused Adder\u2013Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures"],"prefix":"10.1007","volume":"41","author":[{"given":"Bianca","family":"Silveira","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7809-9563","authenticated-orcid":false,"given":"Guilherme","family":"Paim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Brunno Alves","family":"Abreu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rafael","family":"dos Santos Ferreira","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cl\u00e1udio Machado","family":"Diniz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eduardo Ant\u00f4nio C\u00e9sar","family":"da Costa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sergio","family":"Bampi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2021,9,16]]},"reference":[{"key":"1839_CR1","unstructured":"L.\u00a0Agostini, R.\u00a0Porto, J.L.\u00a0G\u00fcntzel, I.S.\u00a0Silva, S.\u00a0Bampi, High throughput multitransform and multiparallelism IP for H.264\/AVC video compression standard, in Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 4\u20135422 (2006)"},{"key":"1839_CR2","doi-asserted-by":"crossref","unstructured":"A.\u00a0Br\u00e4scher, I.\u00a0Seidel, J.\u00a0G\u00fcntzel, Improving the energy efficiency of a low-area SATD hardware architecture using fine grain PDE, in 30th Symposium on Integrated Circuits and Systems Design (SBCCI), pp. 155\u2013161 (2017)","DOI":"10.1145\/3109984.3110009"},{"key":"1839_CR3","unstructured":"Cadence EDA Tools. http:\/\/www.cadence.com"},{"key":"1839_CR4","doi-asserted-by":"crossref","unstructured":"L.H.\u00a0Cancellier, A.B.\u00a0Br\u00e4scher, I.\u00a0Seidel, J.L.\u00a0G\u00fcntzel, Energy-efficient Hadamard-based SATD architectures, in Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, pp. 36:1\u201336:6 (2014)","DOI":"10.1145\/2660540.2661004"},{"issue":"2","key":"1839_CR5","doi-asserted-by":"publisher","first-page":"113","DOI":"10.29292\/jics.v10i2.412","volume":"10","author":"L Cancellier","year":"2015","unstructured":"L. Cancellier, I. Seidel, A. Br\u00e4scher, J. G\u00fcntzel, Exploring optimized Hadamard methods to design energy-efficient SATD architectures. J. Integr. Circuits Syst. 10(2), 113\u2013122 (2015)","journal-title":"J. Integr. Circuits Syst."},{"issue":"10","key":"1839_CR6","doi-asserted-by":"publisher","first-page":"1985","DOI":"10.1109\/TCSI.2004.835683","volume":"51","author":"C Chang","year":"2004","unstructured":"C. Chang, J. Gu, M. Zhang, Ultra low-voltage low-power CMOS 4\u20132 and 5\u20132 compressors for fast arithmetic circuits. IEEE Trans. Circuits Syst. 51(10), 1985\u20131997 (2004)","journal-title":"IEEE Trans. Circuits Syst."},{"key":"1839_CR7","doi-asserted-by":"crossref","unstructured":"L.\u00a0Chen, K.\u00a0Li, C.\u00a0Huang, Y.\u00a0Lai, Analysis and architecture design of multi-transform architecture for H.264\/AVC intra frame coder, in Proceedings of the IEEE International Conference on Multimedia and Expo, pp. 145\u2013148 (2008)","DOI":"10.1109\/ICME.2008.4607392"},{"issue":"1","key":"1839_CR8","doi-asserted-by":"publisher","first-page":"247","DOI":"10.1007\/s11554-015-0492-8","volume":"12","author":"V Coutinho","year":"2016","unstructured":"V. Coutinho, R. Cintra, F. Bayer, S. Kulasekera, A. Madanayake, A multiplierless pruned DCT-like transformation for image and video compression that requires ten additions only. J. Real-Time Image Process. 12(1), 247\u2013255 (2016)","journal-title":"J. Real-Time Image Process."},{"issue":"1","key":"1839_CR9","doi-asserted-by":"publisher","first-page":"111","DOI":"10.1007\/s10470-016-0765-6","volume":"89","author":"CM Diniz","year":"2016","unstructured":"C.M. Diniz, M.B. Fonseca, E.A.C. Costa, S. Bampi, Evaluating the use of adder compressors for power-efficient HEVC interpolation filter architecture. Analog Integr. Circuits Signal Process. 89(1), 111\u2013120 (2016)","journal-title":"Analog Integr. Circuits Signal Process."},{"issue":"12","key":"1839_CR10","doi-asserted-by":"publisher","first-page":"3138","DOI":"10.1109\/TVLSI.2014.2386897","volume":"23","author":"G He","year":"2015","unstructured":"G. He, D. Zhou, Y. Li, Z. Chen, T. Zhang, S. Goto, High-throughput power-efficient VLSI architecture of fractional motion estimation for ultra-HD HEVC video encoding. IEEE Trans. Very Large Scale Integr. Syst. 23(12), 3138\u20133142 (2015)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"issue":"3","key":"1839_CR11","doi-asserted-by":"publisher","first-page":"157","DOI":"10.1109\/TMM.2010.2041099","volume":"12","author":"W Hwangbo","year":"2010","unstructured":"W. Hwangbo, C. Kyung, A multitransform architecture for H.264\/AVC high-profile coders. IEEE Trans. Multimed. 12(3), 157\u2013167 (2010)","journal-title":"IEEE Trans. Multimed."},{"key":"1839_CR12","unstructured":"ITU-T and ISO\/IEC. High Efficiency Video Coding. ITU-T Recommendation H.265 and ISO\/IEC 23008-2 (2013)"},{"key":"1839_CR13","unstructured":"JCT-VC. HEVC Test Model (HM) v. 16.7. https:\/\/hevc.hhi.fraunhofer.de\/"},{"issue":"4","key":"1839_CR14","doi-asserted-by":"publisher","first-page":"662","DOI":"10.1109\/TVLSI.2009.2013629","volume":"18","author":"CY Kao","year":"2010","unstructured":"C.Y. Kao, C.L. Wu, Y.L. Lin, A high-performance three-engine architecture for H.264\/AVC fractional motion estimation. IEEE Trans. Very Large Scale Integr. Syst. 18(4), 662\u2013666 (2010)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"issue":"3","key":"1839_CR15","doi-asserted-by":"publisher","first-page":"432","DOI":"10.1109\/TCSVT.2009.2013511","volume":"19","author":"YK Lin","year":"2009","unstructured":"Y.K. Lin, C.W. Ku, D.W. Li, T.S. Chang, A 140-MHz 94 K gates HD1080p 30-Frames\/s intra-only profile H.264 encoder. IEEE Trans. Circuits Syst. Video Technol. 19(3), 432\u2013436 (2009)","journal-title":"IEEE Trans. Circuits Syst. Video Technol."},{"key":"1839_CR16","doi-asserted-by":"crossref","unstructured":"J.\u00a0Liu, X.\u00a0Chen, Y.\u00a0Fan, X. Zeng, A full-mode FME VLSI architecture based on 8$$\\times $$8\/4$$\\times $$4 adaptive Hadamard Transform for QFHD H.264\/AVC encoder, in Proceedings of the IEEE\/IFIP 19th International Conference on VLSI and System-on-Chip, pp. 434\u2013439 (2011)","DOI":"10.1109\/VLSISoC.2011.6081622"},{"key":"1839_CR17","doi-asserted-by":"crossref","unstructured":"W.\u00a0Lu, N.\u00a0Yu, J.\u00a0Nan, D.\u00a0Wang, A hardware structure of HEVC intra prediction, in 2015 2nd International Conference on Information Science and Control Engineering, pp. 555\u2013559 (2015)","DOI":"10.1109\/ICISCE.2015.129"},{"key":"1839_CR18","doi-asserted-by":"crossref","unstructured":"M.\u00a0Monteiro, I.\u00a0Seidel, J.\u00a0G\u00fcntzel, On the calculation reuse in Hadamard-based SATD, in 9th IEEE Latin American Symposium on Circuits and Systems (LASCAS), pp. 1\u20134 (2018)","DOI":"10.1109\/LASCAS.2018.8399925"},{"key":"1839_CR19","unstructured":"MulticoreWare. HEVC x265 Encoder. https:\/\/bitbucket.org\/multicoreware\/x265\/"},{"key":"1839_CR20","unstructured":"Nangate. Nangate 45 nm Open Cell Library. http:\/\/www.nangate.com"},{"issue":"3","key":"1839_CR21","doi-asserted-by":"publisher","first-page":"294","DOI":"10.1109\/12.485568","volume":"45","author":"VG Oklobdzija","year":"1996","unstructured":"V.G. Oklobdzija, D. Villeger, S.S. Liu, A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach. IEEE Trans. Comput. 45(3), 294\u2013306 (1996)","journal-title":"IEEE Trans. Comput."},{"key":"1839_CR22","doi-asserted-by":"crossref","unstructured":"G.\u00a0Paim, M.\u00a0Fonseca, E.\u00a0Costa, S.\u00a0Almeida, Power efficient 2-d rounded cosine transform with adder compressors for image compression, in 2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 348\u2013351 (2015)","DOI":"10.1109\/ICECS.2015.7440320"},{"key":"1839_CR23","doi-asserted-by":"crossref","unstructured":"G.\u00a0Paim, E.\u00a0Costa, Using adder compressors for power-efficient 2-d approximate discrete Tchebichef transform, in 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), pp. 1\u20134 (2016)","DOI":"10.1109\/NEWCAS.2016.7604835"},{"issue":"1","key":"1839_CR24","first-page":"1","volume":"1","author":"G Paim","year":"2020","unstructured":"G. Paim, G.M. Santana, B.A. Abreu, L.M.G. Rocha, M. Grellert, E.A.C. Costa, S. Bampi, Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding. J. Real-Time Image Process. 1(1), 1\u201320 (2020)","journal-title":"J. Real-Time Image Process."},{"issue":"1","key":"1839_CR25","first-page":"517","volume":"12","author":"G Pastuszak","year":"2015","unstructured":"G. Pastuszak, M. Trochimiuk, Algorithm and architecture design of the motion estimation for the H.265\/HEVC 4K-UHD encoder. J. Real-Time Image Process. 12(1), 517\u2013529 (2015)","journal-title":"J. Real-Time Image Process."},{"issue":"1","key":"1839_CR26","doi-asserted-by":"publisher","first-page":"175","DOI":"10.1007\/s11554-018-0832-6","volume":"16","author":"W Penny","year":"2019","unstructured":"W. Penny, G. Jones, G. Paim, M. Porto, L. Agostini, B. Zatt, High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator. J. Real-Time Image Process. 16(1), 175\u2013192 (2019)","journal-title":"J. Real-Time Image Process."},{"key":"1839_CR27","doi-asserted-by":"crossref","unstructured":"E.\u00a0Quinnell, E.\u00a0E. Swartzlander, C.\u00a0Lemonds, Floating-point fused multiply-add architectures, in 2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers, pp. 331\u2013337 (2007)","DOI":"10.1109\/ACSSC.2007.4487224"},{"key":"1839_CR28","doi-asserted-by":"crossref","unstructured":"G.\u00a0Santana, G.\u00a0Paim, L.\u00a0Rocha, R.\u00a0Neuenfeld, M.\u00a0Fonseca, E.\u00a0Costa, S.\u00a0Bampi, Using efficient adder compressors with a split-radix butterfly hardware architecture for low-power IoT smart sensors. in 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 486\u2013489 (2016)","DOI":"10.1109\/ICECS.2017.8292075"},{"key":"1839_CR29","doi-asserted-by":"crossref","unstructured":"T.\u00a0Schiavon, G.\u00a0Paim, M.\u00a0Fonseca, E.\u00a0Costa, S.\u00a0Almeida, Exploiting adder compressors for power-efficient 2-d approximate DCT realization, in 2016 IEEE 7th Latin American Symposium on Circuits Systems (LASCAS), pp. 383\u2013386 (2016)","DOI":"10.1109\/LASCAS.2016.7451090"},{"key":"1839_CR30","doi-asserted-by":"crossref","unstructured":"I.\u00a0Seidel, A.\u00a0Beims Br\u00e4scher, J.L. G\u00fcntzel, L.\u00a0Agostini, Energy-efficient SATD for beyond HEVC, in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 802\u2013805 (2016)","DOI":"10.1109\/ISCAS.2016.7527362"},{"key":"1839_CR31","doi-asserted-by":"publisher","first-page":"2102","DOI":"10.1109\/TCSI.2019.2900004","volume":"66","author":"I Seidel","year":"2019","unstructured":"I. Seidel, M. Monteiro, B. Bonotto, L. Agostini, J. G\u00fcntzel, Energy-efficient Hadamard-based SATD hardware architectures through calculation reuse. IEEE Trans. Circuits Syst. I: Regul Pap. 66, 2102\u20132115 (2019)","journal-title":"IEEE Trans. Circuits Syst. I: Regul Pap."},{"key":"1839_CR32","doi-asserted-by":"crossref","unstructured":"L.F. Sequeira, G.M. Santana, G.\u00a0Paim, L.M.G. Rocha, B.\u00a0Abreu, E.\u00a0Costa, S.\u00a0Bampi, Low-power hevc 8-point 2-d discrete cosine transform hardware using adder compressors, in 2018 16th IEEE International New Circuits and Systems Conference (NEWCAS), pp. 309\u2013312 (2018)","DOI":"10.1109\/NEWCAS.2018.8585470"},{"key":"1839_CR33","doi-asserted-by":"crossref","unstructured":"B.\u00a0Silveira, C.\u00a0Diniz, M.\u00a0Beck Fonseca, E.\u00a0Costa, SATD hardware architecture based on 8 $$\\times $$ 8 Hadamard transform for HEVC encoder, in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, pp. 576\u2013579 (2015)","DOI":"10.1109\/ICECS.2015.7440382"},{"key":"1839_CR34","doi-asserted-by":"crossref","unstructured":"B.\u00a0Silveira, R.\u00a0Ferreira, G.\u00a0Paim, C.\u00a0Diniz, E.\u00a0Costa, Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors, in 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS), pp. 277\u2013280 (2017)","DOI":"10.1109\/NEWCAS.2017.8010159"},{"issue":"12","key":"1839_CR35","doi-asserted-by":"publisher","first-page":"3126","DOI":"10.1109\/TCSI.2017.2728802","volume":"64","author":"B Silveira","year":"2017","unstructured":"B. Silveira, G. Paim, B. Abreu, M. Grellert, C.M. Diniz, E.A.C. da Costa, S. Bampi, Power-efficient sum of absolute differences hardware architecture using adder compressors for integer motion estimation design. IEEE Trans. Circuits Syst. I: Regul. Pap. 64(12), 3126\u20133137 (2017)","journal-title":"IEEE Trans. Circuits Syst. I: Regul. Pap."},{"key":"1839_CR36","doi-asserted-by":"crossref","unstructured":"L.B. Soares, C.M. Diniz, E.A.C. da\u00a0Costa, S.\u00a0Bampi, A novel pruned-based algorithm for energy-efficient SATD operation in the HEVC coding, in 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI), pp. 1\u20136 (2016)","DOI":"10.1109\/SBCCI.2016.7724049"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-021-01839-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-021-01839-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-021-01839-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T13:25:39Z","timestamp":1725801939000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-021-01839-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,9,16]]},"references-count":36,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2022,3]]}},"alternative-id":["1839"],"URL":"https:\/\/doi.org\/10.1007\/s00034-021-01839-x","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2021,9,16]]},"assertion":[{"value":"26 March 2020","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"26 August 2021","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"28 August 2021","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"16 September 2021","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}