{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T05:00:11Z","timestamp":1771477211661,"version":"3.50.1"},"reference-count":24,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2021,12,2]],"date-time":"2021-12-02T00:00:00Z","timestamp":1638403200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"},{"start":{"date-parts":[[2021,12,2]],"date-time":"2021-12-02T00:00:00Z","timestamp":1638403200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"}],"funder":[{"DOI":"10.13039\/501100011011","name":"junta de andaluc\u00eda","doi-asserted-by":"publisher","award":["P18-FR-3130"],"award-info":[{"award-number":["P18-FR-3130"]}],"id":[{"id":"10.13039\/501100011011","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100014440","name":"ministerio de ciencia, innovaci\u00f3n y universidades","doi-asserted-by":"publisher","award":["PID2019-105396RBI00"],"award-info":[{"award-number":["PID2019-105396RBI00"]}],"id":[{"id":"10.13039\/100014440","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2022,3]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point support. Since variable shifter implementation (required in any FP adder) has a very high cost in FPGA, high-radix formats considerably reduce the number of possible shifts, decreasing the execution time and area highly. Although the high-radix format produces also a significant penalty in the implementation of multipliers, the experimental results show that the adder improvement overweights the multiplication penalty for most of the practical and common cases (digital filters, matrix multiplications, etc.). We also provide the designer with guidelines on selecting a suitable radix as a function of the ratio between the number of additions and multiplications of the targeted algorithm. For applications with similar numbers of additions and multiplications, the high-radix version may be up to 26% faster and even having a wider dynamic range and using higher number of significant bits. Furthermore, thanks to the proposed efficient converters between the standard IEEE-754 format and our internal high-radix format, the cost of the input\/output conversions in FPGA accelerators is negligible.<\/jats:p>","DOI":"10.1007\/s00034-021-01855-x","type":"journal-article","created":{"date-parts":[[2021,12,2]],"date-time":"2021-12-02T17:03:29Z","timestamp":1638464609000},"page":"1683-1703","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["High-Radix Formats for Enhancing Floating-Point FPGA Implementations"],"prefix":"10.1007","volume":"41","author":[{"given":"Julio","family":"Villalba","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5454-6821","authenticated-orcid":false,"given":"Javier","family":"Hormigo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2021,12,2]]},"reference":[{"key":"1855_CR1","unstructured":"Altera: Arria10 device overview. http:\/\/www.altera.com\/literature\/hb\/arria-10\/a10_overview.pdf (2014)"},{"key":"1855_CR2","doi-asserted-by":"publisher","unstructured":"B. Catanzaro, B. Nelson, Higher radix floating-point representations for FPGA-based arithmetic, in 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2005. FCCM 2005, pp. 161\u2013170 (2005). https:\/\/doi.org\/10.1109\/FCCM.2005.43","DOI":"10.1109\/FCCM.2005.43"},{"issue":"4","key":"1855_CR3","doi-asserted-by":"publisher","first-page":"18","DOI":"10.1109\/MDT.2011.44","volume":"28","author":"F de Dinechin","year":"2011","unstructured":"F. de Dinechin, B. Pasca, Designing custom arithmetic data paths with flopoco. IEEE Des. Test Comput. 28(4), 18\u201327 (2011). https:\/\/doi.org\/10.1109\/MDT.2011.44","journal-title":"IEEE Des. Test Comput."},{"key":"1855_CR4","doi-asserted-by":"publisher","unstructured":"F. de\u00a0Dinechin, B. Pasca, O. Cret, R. Tudoran, An fpga-specific approach to floating-point accumulation and sum-of-products, in International Conference on ICECE Technology, 2008. FPT 2008, pp. 33\u201340 (2008). https:\/\/doi.org\/10.1109\/FPT.2008.4762363","DOI":"10.1109\/FPT.2008.4762363"},{"key":"1855_CR5","volume-title":"Digital Arithmetic","author":"MD Ercegovac","year":"2004","unstructured":"M.D. Ercegovac, T. Lang, Digital Arithmetic (Morgan Kaufmann, San Francisco, 2004)"},{"key":"1855_CR6","doi-asserted-by":"publisher","DOI":"10.3390\/app10030827","author":"J Frances-Villora","year":"2020","unstructured":"J. Frances-Villora, M. Bataller-Mompean, A. Mjahad, A. Rosado-Mu\u00f1oz, A. Martin, V. Teruel-Marti, V. Villanueva, K. Hampel, J. Guerrero-Martinez, Real-time localization of epileptogenic foci EEG signals: an FPGA-based implementation. Appl. Sci. (Switzerland) (2020). https:\/\/doi.org\/10.3390\/app10030827","journal-title":"Appl. Sci. (Switzerland)"},{"issue":"4","key":"1855_CR7","doi-asserted-by":"publisher","first-page":"548","DOI":"10.1049\/iet-cds.2018.5478","volume":"13","author":"C Guo","year":"2019","unstructured":"C. Guo, J. Xu, H. Zhang, Design of doppler parameters estimation circuit. IET Circuits Devices Syst. 13(4), 548\u2013557 (2019). https:\/\/doi.org\/10.1049\/iet-cds.2018.5478","journal-title":"IET Circuits Devices Syst."},{"key":"1855_CR8","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126620500450","author":"N Hasanikhah","year":"2020","unstructured":"N. Hasanikhah, S. Amin-Nejad, G. Darvish, M. Moniri, An efficient and high-speed implementation of GRD-MGS algorithm for stap application based on floating point FPGAs. J. Circuits Syst. Comput. (2020). https:\/\/doi.org\/10.1142\/S0218126620500450","journal-title":"J. Circuits Syst. Comput."},{"issue":"12","key":"1855_CR9","doi-asserted-by":"publisher","first-page":"1709","DOI":"10.1109\/TVLSI.2008.2006616","volume":"17","author":"CH Ho","year":"2009","unstructured":"C.H. Ho, C.W. Yu, P. Leong, W. Luk, S. Wilton, Floating-point FPGA: architecture and modeling. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17(12), 1709\u20131718 (2009). https:\/\/doi.org\/10.1109\/TVLSI.2008.2006616","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"1855_CR10","doi-asserted-by":"publisher","unstructured":"IEEE: IEEE standard for floating-point arithmetic. IEEE Std 754-2008, pp. 1\u201358 (2008). https:\/\/doi.org\/10.1109\/IEEESTD.2008.4610935","DOI":"10.1109\/IEEESTD.2008.4610935"},{"key":"1855_CR11","doi-asserted-by":"publisher","DOI":"10.1016\/j.compbiomed.2019.103598","author":"O Inam","year":"2020","unstructured":"O. Inam, A. Basit, M. Qureshi, H. Omer, FPGA-based hardware accelerator for sense (a parallel MR image reconstruction method). Comput. Biol. Med. (2020). https:\/\/doi.org\/10.1016\/j.compbiomed.2019.103598","journal-title":"Comput. Biol. Med."},{"key":"1855_CR12","doi-asserted-by":"publisher","first-page":"134434","DOI":"10.1109\/ACCESS.2019.2942205","volume":"7","author":"H Issa","year":"2019","unstructured":"H. Issa, S. Eisa Ahmed, FPGA implementation of floating point based cuckoo search algorithm. IEEE Access 7, 134434\u2013134447 (2019). https:\/\/doi.org\/10.1109\/ACCESS.2019.2942205","journal-title":"IEEE Access"},{"issue":"5","key":"1855_CR13","doi-asserted-by":"publisher","first-page":"2097","DOI":"10.1007\/s00034-018-0953-y","volume":"38","author":"U Korat","year":"2019","unstructured":"U. Korat, A. Alimohammad, A reconfigurable hardware architecture for principal component analysis. Circuits Syst. Signal Process. 38(5), 2097\u20132113 (2019). https:\/\/doi.org\/10.1007\/s00034-018-0953-y","journal-title":"Circuits Syst. Signal Process."},{"issue":"3","key":"1855_CR14","doi-asserted-by":"publisher","first-page":"152","DOI":"10.1504\/IJCAT.2019.102852","volume":"61","author":"I Koyuncu","year":"2019","unstructured":"I. Koyuncu, M. Al\u00e7in, M. Tuna, I. Pehlivan, M. Varan, S. Vaidyanathan, Real-time high-speed 5-D hyperchaotic Lorenz system on FPGA. Int. J. Comput. Appl. Technol. 61(3), 152\u2013165 (2019). https:\/\/doi.org\/10.1504\/IJCAT.2019.102852","journal-title":"Int. J. Comput. Appl. Technol."},{"issue":"1","key":"1855_CR15","doi-asserted-by":"publisher","first-page":"1360","DOI":"10.1515\/jisys-2017-0509","volume":"29","author":"M Kumar","year":"2020","unstructured":"M. Kumar, K. Chari, Noise reduction using modified wiener filter in digital hearing aid for speech signal enhancement. J. Intell. Syst. 29(1), 1360\u20131378 (2020). https:\/\/doi.org\/10.1515\/jisys-2017-0509","journal-title":"J. Intell. Syst."},{"issue":"7","key":"1855_CR16","doi-asserted-by":"publisher","first-page":"7465","DOI":"10.1109\/TPEL.2019.2954558","volume":"35","author":"FJ Lin","year":"2020","unstructured":"F.J. Lin, M.S. Huang, S.G. Chen, C.W. Hsu, C.H. Liang, Adaptive backstepping control for synchronous reluctance motor based on intelligent current angle control. IEEE Trans. Power Electron. 35(7), 7465\u20137479 (2020). https:\/\/doi.org\/10.1109\/TPEL.2019.2954558","journal-title":"IEEE Trans. Power Electron."},{"key":"1855_CR17","doi-asserted-by":"publisher","DOI":"10.1016\/j.ijepes.2020.106575","author":"Z Ortatepe","year":"2021","unstructured":"Z. Ortatepe, A. Karaarslan, Error minimization based on multi-objective finite control set model predictive control for matrix converter in dfig. Int. J. Electr. Power Energy Syst. (2021). https:\/\/doi.org\/10.1016\/j.ijepes.2020.106575","journal-title":"Int. J. Electr. Power Energy Syst."},{"key":"1855_CR18","doi-asserted-by":"publisher","DOI":"10.1016\/j.epsr.2020.106716","author":"T Ould-Bachir","year":"2021","unstructured":"T. Ould-Bachir, H. Chalangar, K. Sheshyekani, J. Mahseredjian, High performance computing engines for the FPGA-based simulation of the ulm. Electric Power Syst. Res. (2021). https:\/\/doi.org\/10.1016\/j.epsr.2020.106716","journal-title":"Electric Power Syst. Res."},{"key":"1855_CR19","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2020.102997","author":"F Pajuelo-Holguera","year":"2020","unstructured":"F. Pajuelo-Holguera, J. G\u00f3mez-Pulido, F. Ortega, J. Granado-Criado, Recommender system implementations for embedded collaborative filtering applications. Microprocessors Microsyst. (2020). https:\/\/doi.org\/10.1016\/j.micpro.2020.102997","journal-title":"Microprocessors Microsyst."},{"issue":"99","key":"1855_CR20","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/TII.2015.2431223","volume":"PP","author":"J Rodriguez-Andina","year":"2015","unstructured":"J. Rodriguez-Andina, M. Valdes-Pena, M. Moure, Advanced features and industrial applications of FPGAs\u2014a review. IEEE Trans. Ind. Inform. PP(99), 1\u20131 (2015). https:\/\/doi.org\/10.1109\/TII.2015.2431223","journal-title":"IEEE Trans. Ind. Inform."},{"key":"1855_CR21","doi-asserted-by":"crossref","first-page":"189","DOI":"10.1007\/978-981-13-1544-2_16","volume":"811","author":"S Roy Chatterjee","year":"2019","unstructured":"S. Roy Chatterjee, J. Chowdhury, M. Chakraborty, Hardware realization of power adaptation technique for cognitive radio sensor node. Adv. Intell. Syst. Comput. 811, 189\u2013198 (2019)","journal-title":"Adv. Intell. Syst. Comput."},{"key":"1855_CR22","doi-asserted-by":"publisher","first-page":"75530","DOI":"10.1109\/ACCESS.2020.2988527","volume":"8","author":"R Sun","year":"2020","unstructured":"R. Sun, P. Liu, J. Xue, S. Yang, J. Qian, R. Ying, Bax: A bundle adjustment accelerator with decoupled access\/execute architecture for visual odometry. IEEE Access 8, 75530\u201375542 (2020). https:\/\/doi.org\/10.1109\/ACCESS.2020.2988527","journal-title":"IEEE Access"},{"key":"1855_CR23","doi-asserted-by":"publisher","unstructured":"J. Villalba, J. Hormigo, F. Corbera, M. Gonzalez, E. Zapata, Efficient floating-point representation for balanced codes for FPGA devices, in 2013 IEEE 31st International Conference on Computer Design (ICCD), pp. 272\u2013277 (2013). https:\/\/doi.org\/10.1109\/ICCD.2013.6657053","DOI":"10.1109\/ICCD.2013.6657053"},{"key":"1855_CR24","unstructured":"Xilinx: LogiCORE IP floating-point operator v6.0. DS816 (2012)"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-021-01855-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-021-01855-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-021-01855-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,11,13]],"date-time":"2023-11-13T14:27:11Z","timestamp":1699885631000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-021-01855-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12,2]]},"references-count":24,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2022,3]]}},"alternative-id":["1855"],"URL":"https:\/\/doi.org\/10.1007\/s00034-021-01855-x","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,12,2]]},"assertion":[{"value":"3 February 2021","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"12 September 2021","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"13 September 2021","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"2 December 2021","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}