{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T11:02:22Z","timestamp":1740135742426,"version":"3.37.3"},"reference-count":23,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2022,10,17]],"date-time":"2022-10-17T00:00:00Z","timestamp":1665964800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2022,10,17]],"date-time":"2022-10-17T00:00:00Z","timestamp":1665964800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2023,4]]},"DOI":"10.1007\/s00034-022-02205-1","type":"journal-article","created":{"date-parts":[[2022,10,17]],"date-time":"2022-10-17T18:03:06Z","timestamp":1666029786000},"page":"1873-1892","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A 12-Phase and 5-GHz PLL with a Subfeedback Loop Technique"],"prefix":"10.1007","volume":"42","author":[{"given":"Hong-Yi","family":"Huang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7045-6586","authenticated-orcid":false,"given":"Jen-Chieh","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fu-Chien","family":"Tsai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kun-Hua","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kun-Yuan","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2022,10,17]]},"reference":[{"issue":"6","key":"2205_CR1","doi-asserted-by":"publisher","first-page":"1278","DOI":"10.1109\/JSSC.2012.2188564","volume":"47","author":"MM Abdul-Latif","year":"2012","unstructured":"M.M. Abdul-Latif, E. Sanchez-Sinencio, Low phase noise wide tuning range N-push cyclic-coupled ring oscillators. IEEE J. Solid-State Circuits 47(6), 1278\u20131294 (2012)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"5","key":"2205_CR2","doi-asserted-by":"publisher","first-page":"2466","DOI":"10.1007\/s00034-021-01900-9","volume":"41","author":"D Biswas","year":"2022","unstructured":"D. Biswas, Spur reduction circuit for fractional-N PLLs. Circuits Syst. Signal Process 41(5), 2466\u20132485 (2022)","journal-title":"Circuits Syst. Signal Process"},{"key":"2205_CR3","doi-asserted-by":"crossref","unstructured":"I.S. Bristy, M.N. Uddin, Optimization and performance analysis of 32 channel 60 Gbps hybrid mono stage MZM based WDM PON covering 120 km transmission distance, in IEEE International Conference on Robotics, Electrical and Signal Processing Techniques (2021), pp. 635\u2013639","DOI":"10.1109\/ICREST51555.2021.9331216"},{"issue":"6","key":"2205_CR4","doi-asserted-by":"publisher","first-page":"2982","DOI":"10.1007\/s00034-020-01608-2","volume":"40","author":"H Ghasemian","year":"2021","unstructured":"H. Ghasemian, A. Bahrami, E. Abiri, M.R. Salehi, A new low-power charge pump with a glitch-free PFD for speedup the acquisition process of a PLL in 65 nm CMOS technology. Circuits Syst. Signal Process 40(6), 2982\u20133006 (2021)","journal-title":"Circuits Syst. Signal Process"},{"issue":"10","key":"2205_CR5","doi-asserted-by":"publisher","first-page":"2332","DOI":"10.1109\/TCSI.2011.2142810","volume":"58","author":"AA Hafez","year":"2011","unstructured":"A.A. Hafez, C.-K. Yang, Design and optimization of multipath ring oscillators. IEEE Trans. Circuits Syst. I Reg. Pap. 58(10), 2332\u20132345 (2011)","journal-title":"IEEE Trans. Circuits Syst. I Reg. Pap."},{"key":"2205_CR6","unstructured":"H.-Y. Huang, F.-C. Tsai, Analysis and optimization of ring oscillator using sub-feedback scheme, in Proceedings of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (2009), pp. 28\u201329"},{"issue":"5","key":"2205_CR7","doi-asserted-by":"publisher","first-page":"2522","DOI":"10.1007\/s00034-021-01921-4","volume":"41","author":"IU Khan","year":"2022","unstructured":"I.U. Khan, D. Balodi, N.K. Misra, Low power LC-quadrature VCO with superior phase noise performance in 0.13 \u00b5m RF-CMOS process for modern WLAN application. Circuits Syst. Signal Process 41(5), 2522\u20132540 (2022)","journal-title":"Circuits Syst. Signal Process"},{"issue":"6","key":"2205_CR8","doi-asserted-by":"publisher","first-page":"1385","DOI":"10.1109\/4.62166","volume":"25","author":"B Kim","year":"1990","unstructured":"B. Kim, D.N. Helman, P.R. Gray, A 30-MHz hybrid analog\/digital clock recovery circuit in 2-\u03bcm CMOS. IEEE J. Solid-State Circuits 25(6), 1385\u20131394 (1990)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"11","key":"2205_CR9","doi-asserted-by":"publisher","first-page":"1403","DOI":"10.1109\/JSSC.2002.803937","volume":"37","author":"J Kim","year":"2002","unstructured":"J. Kim, M.A. Horowitz, Adaptive supply serial links with sub-1-V operation and per-pin clock recovery. IEEE J. Solid-State Circuits 37(11), 1403\u20131413 (2002)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"1","key":"2205_CR10","doi-asserted-by":"publisher","first-page":"193","DOI":"10.1109\/JSSC.2006.888297","volume":"42","author":"K-H Kim","year":"2007","unstructured":"K.-H. Kim, H.-J. Chung, W.-S. Kim, M. Park, Y.-C. Jang, J.-Y. Kim, H.-W. Park, U. Kang, P.W. Coteus, J.-S. Choi, C.-H. Kim, An 8 Gb\/s\/pin 9.6 ns row-cycle 288 Mb deca-data rate SDRAM with an I\/O error detection scheme. IEEE J. Solid-State Circuits 42(1), 193 (2007)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"2205_CR11","unstructured":"Y. Konno, K. Tomioka, Y. Aiba, K. Yamazoe, B.-S. Song, A CMOS 1\u00d7- to 16\u00d7-speed DVD write channel IC, in IEEE International Solid-State Circuits Conference: Digest of Technical Papers (2005), pp. 568\u2013569"},{"key":"2205_CR12","doi-asserted-by":"crossref","unstructured":"M.-A. LaCroix, H. Wong, Y.H. Liu, H. Ho, S. Lebedev, P. Krotnev, D.A. Nicolescu, D. Petrov, C. Carvalho, S. Alie, E. Chong, F.A. Musa, D. Tonietto, A 60Gb\/s PAM-4 ADC-DSP transceiver in 7\u00a0nm CMOS with SNR-based adaptive power scaling achieving 6.9pJ\/b at 32dB loss, in IEEE IEEE International Solid-State Circuits Conference: Digest of Technical Papers (2019), pp. 114\u2013116","DOI":"10.1109\/ISSCC.2019.8662322"},{"issue":"2","key":"2205_CR13","doi-asserted-by":"publisher","first-page":"289","DOI":"10.1109\/4.551926","volume":"32","author":"S-J Lee","year":"1997","unstructured":"S.-J. Lee, B. Kim, K. Lee, A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme. IEEE J. Solid-State Circuits 32(2), 289\u2013291 (1997)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"3","key":"2205_CR14","doi-asserted-by":"publisher","first-page":"39717","DOI":"10.1109\/ACCESS.2021.3064378","volume":"9","author":"J-C Liu","year":"2021","unstructured":"J.-C. Liu, Y.-P. Li, A low supply voltage all-digital phase-locked loop with a bootstrapped and forward interpolation digitally controlled oscillator. IEEE Access 9(3), 39717\u201339726 (2021)","journal-title":"IEEE Access"},{"issue":"12","key":"2205_CR15","doi-asserted-by":"publisher","first-page":"4809","DOI":"10.1007\/s00034-017-0640-4","volume":"36","author":"Y-L Lo","year":"2017","unstructured":"Y.-L. Lo, W.-H. Ho, A low-voltage PLL design using a new calibration technique for low-power implantable biomedical systems. Circuits Syst. Signal Process 36(12), 4809\u20134828 (2017)","journal-title":"Circuits Syst. Signal Process"},{"issue":"12","key":"2205_CR16","doi-asserted-by":"publisher","first-page":"1273","DOI":"10.1109\/4.262000","volume":"28","author":"JG Maneatis","year":"1993","unstructured":"J.G. Maneatis, M.A. Horowitz, Precise delay generation using coupled oscillators. IEEE J. Solid-State Circuits 28(12), 1273\u20131282 (1993)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"4","key":"2205_CR17","doi-asserted-by":"publisher","first-page":"831","DOI":"10.1109\/JSSC.2008.917567","volume":"43","author":"A Matsumoto","year":"2008","unstructured":"A. Matsumoto, S. Sakiyama, Y. Tokunaga, T. Morie, S. Dosho, A design method and developments of a low-power and high-resolution multiphase generation system. IEEE J. Solid-State Circuits 43(4), 831\u2013843 (2008)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"3","key":"2205_CR18","doi-asserted-by":"publisher","first-page":"337","DOI":"10.1109\/4.661199","volume":"33","author":"JF Parker","year":"1998","unstructured":"J.F. Parker, D. Ray, A 1.6-GHz CMOS PLL with on-chip loop filter. IEEE J. Solid-State Circuits 33(3), 337\u2013343 (1998)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"2205_CR19","unstructured":"A. Rofourgan, J. Rael, M. Rofourgan, A. Abidi, A 900 MHz CMOS LC-oscillator with quadrature outputs, in IEEE International Solid-State Circuits Conference: Digest of Technical Papers (1996), pp. 392\u2013393"},{"issue":"8","key":"2205_CR20","doi-asserted-by":"publisher","first-page":"3884","DOI":"10.1007\/s00034-021-01653-5","volume":"40","author":"S Salem","year":"2021","unstructured":"S. Salem, M. Saneei, D. Abbasi-Moghadam, Jitter modeling in digital CDR with quantization noise analysis. Circuits Syst. Signal Process 40(8), 3884\u20133906 (2021)","journal-title":"Circuits Syst. Signal Process"},{"issue":"6","key":"2205_CR21","doi-asserted-by":"publisher","first-page":"910","DOI":"10.1109\/4.924853","volume":"36","author":"L Sun","year":"2001","unstructured":"L. Sun, T.A. Kwasniewski, A 1.25-GHz 0.35-um monolithic CMOS PLL based on a multiphase ring oscillator. IEEE J. Solid-State Circuits 36(6), 910\u2013916 (2001)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"2205_CR22","unstructured":"L. Sun, T. Kwasniewski, K. Iniewski, A quadrature output voltage-controlled ring oscillator based on three-stage sub-feedback loops, in Proceedings of IEEE International Symposium on Circuits and Systems (1999), pp. 176\u2013179"},{"issue":"6","key":"2205_CR23","doi-asserted-by":"publisher","first-page":"720","DOI":"10.1049\/iet-cds.2018.5149","volume":"12","author":"Y-H Tu","year":"2018","unstructured":"Y.-H. Tu, J.-C. Liu, K.-H. Cheng, C.-Y. Chang, Low supply voltage and multiphase all-digital crystal-less clock generator. IEE Circuits Devices Syst. 12(6), 720\u2013725 (2018)","journal-title":"IEE Circuits Devices Syst."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-022-02205-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-022-02205-1\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-022-02205-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,4,4]],"date-time":"2023-04-04T12:07:00Z","timestamp":1680610020000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-022-02205-1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,17]]},"references-count":23,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2023,4]]}},"alternative-id":["2205"],"URL":"https:\/\/doi.org\/10.1007\/s00034-022-02205-1","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2022,10,17]]},"assertion":[{"value":"27 April 2022","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"29 September 2022","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"29 September 2022","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"17 October 2022","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}