{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,3]],"date-time":"2026-03-03T16:26:40Z","timestamp":1772555200972,"version":"3.50.1"},"reference-count":23,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2022,11,11]],"date-time":"2022-11-11T00:00:00Z","timestamp":1668124800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2022,11,11]],"date-time":"2022-11-11T00:00:00Z","timestamp":1668124800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2023,2]]},"DOI":"10.1007\/s00034-022-02232-y","type":"journal-article","created":{"date-parts":[[2022,11,11]],"date-time":"2022-11-11T18:03:54Z","timestamp":1668189834000},"page":"780-800","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":14,"title":["Area-, Power-, and Delay-Optimized 2D FIR Filter Architecture for Image Processing Applications"],"prefix":"10.1007","volume":"42","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4909-2287","authenticated-orcid":false,"given":"Gundugonti Kishore","family":"Kumar","sequence":"first","affiliation":[]},{"given":"Ravi Raja","family":"Akurati","sequence":"additional","affiliation":[]},{"given":"Venkata Hanuma Prasad","family":"Reddy","sequence":"additional","affiliation":[]},{"given":"Soumica","family":"Cheemalakonda","sequence":"additional","affiliation":[]},{"given":"Sudeeksha","family":"Chagarlamudi","sequence":"additional","affiliation":[]},{"given":"Bhasita","family":"Dasari","sequence":"additional","affiliation":[]},{"given":"Sameera Sulthana","family":"Shaik","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2022,11,11]]},"reference":[{"key":"2232_CR1","doi-asserted-by":"crossref","unstructured":"A. Benyamina, S. Moulahoum, FPGA in the loop based single phase power factor correction, in 2019 Progress in Applied Electrical Engineering (PAEE) (IEEE, 2019), pp. 1\u20136","DOI":"10.1109\/PAEE.2019.8788997"},{"issue":"2","key":"2232_CR2","doi-asserted-by":"publisher","first-page":"618","DOI":"10.1109\/TCSI.2017.2724767","volume":"65","author":"T Bindima","year":"2017","unstructured":"T. Bindima, E. Elias, Design and implementation of low complexity 2-d variable digital fir filters using single-parameter-tunable 2-d farrow structure. IEEE Trans. Circuits Syst. I Regul. Pap. 65(2), 618\u2013627 (2017)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"2232_CR3","doi-asserted-by":"crossref","unstructured":"F. Cabello, J. Le\u00f3n, Y. Iano, R. Arthur, Implementation of a fixed-point 2d Gaussian filter for image processing based on FPGA, in 2015 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA) (IEEE, 2015), pp. 28\u201333","DOI":"10.1109\/SPA.2015.7365108"},{"issue":"2","key":"2232_CR4","doi-asserted-by":"publisher","first-page":"1079","DOI":"10.1007\/s11042-014-2358-7","volume":"75","author":"A Chandra","year":"2016","unstructured":"A. Chandra, S. Chattopadhyay, A new strategy of image denoising using multiplier-less fir filter designed with the aid of differential evolution algorithm. Multimed. Tools Appl. 75(2), 1079\u20131098 (2016)","journal-title":"Multimed. Tools Appl."},{"issue":"1","key":"2232_CR5","doi-asserted-by":"publisher","first-page":"112","DOI":"10.1109\/TCSI.2010.2055274","volume":"58","author":"P-Y Chen","year":"2010","unstructured":"P.-Y. Chen, L.-D. Van, I.-H. Khoo, H.C. Reddy, C.-T. Lin, Power-efficient and cost-effective 2-d symmetry filter architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 58(1), 112\u2013125 (2010)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"issue":"6","key":"2232_CR6","first-page":"547","volume":"43","author":"P Das","year":"2021","unstructured":"P. Das, S.K. Naskar, S. Narayan Patra, Fast converging cuckoo search algorithm to design symmetric FIR filters. Int. J. Comput. Appl. 43(6), 547\u2013565 (2021)","journal-title":"Int. J. Comput. Appl."},{"issue":"2","key":"2232_CR7","doi-asserted-by":"publisher","first-page":"2597","DOI":"10.1007\/s11227-021-03963-6","volume":"78","author":"A Dehghani","year":"2022","unstructured":"A. Dehghani, A. Kavari, M. Kalbasi, K. RahimiZadeh, A new approach for design of an efficient FPGA-based reconfigurable convolver for image processing. J. Supercomput. 78(2), 2597\u20132615 (2022)","journal-title":"J. Supercomput."},{"issue":"1","key":"2232_CR8","doi-asserted-by":"publisher","first-page":"204","DOI":"10.1016\/j.mejo.2010.08.008","volume":"42","author":"F Fons","year":"2011","unstructured":"F. Fons, M. Fons, E. Cant\u00f3, Run-time self-reconfigurable 2d convolver for adaptive image processing. Microelectron. J. 42(1), 204\u2013217 (2011)","journal-title":"Microelectron. J."},{"issue":"15","key":"2232_CR9","doi-asserted-by":"publisher","first-page":"2050243","DOI":"10.1142\/S0218126620502436","volume":"29","author":"KK Gundugonti","year":"2020","unstructured":"K.K. Gundugonti, B. Narayanam, An area-power efficient denoising hardware architecture for real EOG signal. J. Circuits Syst. Comput. 29(15), 2050243 (2020)","journal-title":"J. Circuits Syst. Comput."},{"issue":"3","key":"2232_CR10","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1007\/s42979-021-00553-4","volume":"2","author":"KK Gundugonti","year":"2021","unstructured":"K.K. Gundugonti, B. Narayanam, Efficient Haar wavelet transform for detecting saccades and blinks in real-time EOG signal. SN Comput. Sci. 2(3), 1\u20137 (2021)","journal-title":"SN Comput. Sci."},{"issue":"13","key":"2232_CR11","doi-asserted-by":"publisher","first-page":"2150237","DOI":"10.1142\/S0218126621502376","volume":"30","author":"KK Gundugonti","year":"2021","unstructured":"K.K. Gundugonti, B. Narayanam, High speed fir filter using radix-2 r multiplier and its application for denoising EOG signal. J. Circuits Syst. Comput. 30(13), 2150237 (2021)","journal-title":"J. Circuits Syst. Comput."},{"key":"2232_CR12","doi-asserted-by":"crossref","unstructured":"N. Habibunnisha, D. Nedumaran, Hardware-based document image thresholding techniques using dsp builder and simulink, in Artificial Intelligence and Evolutionary Computations in Engineering Systems (Springer, 2022), pp. 207\u2013220","DOI":"10.1007\/978-981-16-2674-6_16"},{"issue":"6","key":"2232_CR13","first-page":"683","volume":"3","author":"S Kaur","year":"2013","unstructured":"S. Kaur, M.S.M. Suman, S. Manna, Implementation of modified booth algorithm (radix 4) and its comparison with booth algorithm (radix-2). Adv. Electron. Electr. Eng. 3(6), 683\u2013690 (2013)","journal-title":"Adv. Electron. Electr. Eng."},{"issue":"7","key":"2232_CR14","doi-asserted-by":"publisher","first-page":"2934","DOI":"10.1007\/s00034-017-0698-z","volume":"37","author":"P Kumar","year":"2018","unstructured":"P. Kumar, P.C. Shrivastava, M. Tiwari, A. Dhawan, ASIC implementation of area-efficient, high-throughput 2-d IIR filter using distributed arithmetic. Circuits Syst. Signal Process. 37(7), 2934\u20132957 (2018)","journal-title":"Circuits Syst. Signal Process."},{"issue":"3","key":"2232_CR15","doi-asserted-by":"publisher","first-page":"1099","DOI":"10.1007\/s00034-018-0897-2","volume":"38","author":"P Kumar","year":"2019","unstructured":"P. Kumar, P.C. Shrivastava, M. Tiwari, G.R. Mishra, High-throughput, area-efficient architecture of 2-d block FIR filter using distributed arithmetic algorithm. Circuits Syst. Signal Process. 38(3), 1099\u20131113 (2019)","journal-title":"Circuits Syst. Signal Process."},{"issue":"4","key":"2232_CR16","doi-asserted-by":"publisher","first-page":"1385","DOI":"10.1007\/s11045-020-00714-3","volume":"31","author":"VK Odugu","year":"2020","unstructured":"V.K. Odugu, C. Venkata Narasimhulu, K. Satya Prasad, Design and implementation of low complexity circularly symmetric 2d FIR filter architectures. Multidimens. Syst. Signal Process. 31(4), 1385\u20131410 (2020)","journal-title":"Multidimens. Syst. Signal Process."},{"issue":"11","key":"2232_CR17","doi-asserted-by":"publisher","first-page":"3653","DOI":"10.1002\/cta.3114","volume":"49","author":"VK Odugu","year":"2021","unstructured":"V.K. Odugu, C. Venkata Narasimhulu, K. Satya Prasad, An efficient VLSI architecture of 2-d finite impulse response filter using enhanced approximate compressor circuits. Int. J. Circuit Theory Appl. 49(11), 3653\u20133668 (2021)","journal-title":"Int. J. Circuit Theory Appl."},{"issue":"5","key":"2232_CR18","first-page":"349","volume":"61","author":"AK Oudjida","year":"2014","unstructured":"A.K. Oudjida, N. Chaillet, Radix-$$2^r$$ arithmetic for multiplication by a constant. IEEE Trans. Circuits Syst. II Express Briefs 61(5), 349\u2013353 (2014)","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"2232_CR19","volume-title":"Verilog HDL: A Guide to Digital Design and Synthesis","author":"S Palnitkar","year":"2003","unstructured":"S. Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, vol. 1 (Prentice Hall Professional, Hoboken, 2003)"},{"issue":"1","key":"2232_CR20","doi-asserted-by":"publisher","first-page":"169","DOI":"10.1007\/s10470-017-1025-0","volume":"93","author":"G Rajakumar","year":"2017","unstructured":"G. Rajakumar, A. Andrew Roobert, T. Arun Samuel, D. Gracia Nirmala Rani, Low power VLSI architecture design of BMC, BPSC and PC schemes. Analog Integr. Circuits Signal Process. 93(1), 169\u2013178 (2017)","journal-title":"Analog Integr. Circuits Signal Process."},{"issue":"2","key":"2232_CR21","doi-asserted-by":"publisher","first-page":"111","DOI":"10.1109\/TC.2005.32","volume":"54","author":"P-M Seidel","year":"2005","unstructured":"P.-M. Seidel, L.D. McFearin, D.W. Matula, Secondary radix recodings for higher radix multipliers. IEEE Trans. Comput. 54(2), 111\u2013123 (2005)","journal-title":"IEEE Trans. Comput."},{"key":"2232_CR22","unstructured":"O. Shipitko, A. Grigoryev, Gaussian filtering for fpga based image processing with high-level synthesis tools, in Proceedings of the IV International Conference on Information Technology and Nanotechnology, Sarma, Russia (2018), pp. 24\u201327"},{"key":"2232_CR23","doi-asserted-by":"crossref","unstructured":"V. Thamizharasan, N. Kasthuri, FPGA implementation of high performance digital FIR filter design using a hybrid adder and multiplier. Int. J. Electron. 1\u201321 (2022)","DOI":"10.1080\/00207217.2022.2098387"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-022-02232-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-022-02232-y\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-022-02232-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,2,3]],"date-time":"2023-02-03T03:10:31Z","timestamp":1675393831000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-022-02232-y"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,11,11]]},"references-count":23,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2023,2]]}},"alternative-id":["2232"],"URL":"https:\/\/doi.org\/10.1007\/s00034-022-02232-y","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,11,11]]},"assertion":[{"value":"13 April 2022","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"29 October 2022","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"29 October 2022","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"11 November 2022","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors state that they do not have any conflicts of interest.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}]}}