{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T11:02:15Z","timestamp":1740135735246,"version":"3.37.3"},"reference-count":30,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2022,11,22]],"date-time":"2022-11-22T00:00:00Z","timestamp":1669075200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2022,11,22]],"date-time":"2022-11-22T00:00:00Z","timestamp":1669075200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"funder":[{"DOI":"10.13039\/501100002322","name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002322","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2023,2]]},"DOI":"10.1007\/s00034-022-02235-9","type":"journal-article","created":{"date-parts":[[2022,11,23]],"date-time":"2022-11-23T00:11:46Z","timestamp":1669162306000},"page":"828-852","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Energy-Efficient VLSI Squarer Unit with Optimized Radix-2m Multiplication Logic"],"prefix":"10.1007","volume":"42","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9582-9011","authenticated-orcid":false,"given":"Morgana M. A.","family":"da Rosa","sequence":"first","affiliation":[]},{"given":"Eduardo A. C.","family":"da Costa","sequence":"additional","affiliation":[]},{"given":"Leandro Giacomini","family":"Rocha","sequence":"additional","affiliation":[]},{"given":"Guilherme","family":"Paim","sequence":"additional","affiliation":[]},{"given":"Sergio","family":"Bampi","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2022,11,22]]},"reference":[{"key":"2235_CR1","doi-asserted-by":"crossref","unstructured":"A. Banerjee, D. K. Das, Squarer design with reduced area and delay, in 2015 19th International Symposium on VLSI Design and Test (2015). pp. 1\u20136","DOI":"10.1109\/ISVDAT.2015.7208092"},{"key":"2235_CR2","doi-asserted-by":"crossref","unstructured":"A. Banerjee, D. Das, A new squarer design with reduced area and delay. in 19th International Symposium on VLSI Design and Test (VDAT), Avignon (2016). pp. 205\u2013214","DOI":"10.1049\/iet-cdt.2015.0170"},{"key":"2235_CR3","doi-asserted-by":"crossref","unstructured":"S. Bui and J. Stine, Additional optimizations for parallel squarer units. in IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, Australia (2014)","DOI":"10.1109\/ISCAS.2014.6865140"},{"key":"2235_CR4","doi-asserted-by":"crossref","unstructured":"S. Bui, J. Stine, M. Sadeghian, Experiments with high speed parallel cubing units. in IEEE Computer Society Annual Symposium on VLSI, Tampa,FL, USA (2014)","DOI":"10.1109\/ISVLSI.2014.97"},{"key":"2235_CR5","unstructured":"Cadence. (2017) Rtl compiler. https:\/\/www.cadence.com\/"},{"key":"2235_CR6","doi-asserted-by":"crossref","unstructured":"J. Coron, Resistance against differential power analysis for elliptic curve cryptosystems. in Conference on Cryptographic Hardware and Embedded Systems(CHES) (1999). p. 292\u2013302","DOI":"10.1007\/3-540-48059-5_25"},{"key":"2235_CR7","unstructured":"L. Dadda, Some schemes for parallel multipliers, Alta Frequenza (1965)"},{"issue":"1","key":"2235_CR8","doi-asserted-by":"publisher","first-page":"1","DOI":"10.29292\/jics.v14i1.51","volume":"14","author":"T Fontanari","year":"2019","unstructured":"T. Fontanari, G. Paim, L. Rocha, G. Santana, E. da Costa, S. Bampi, A fast monolithic 8\u20132 adder compressor circuit. J. Integr. Circ. Syst. 14(1), 1\u20137 (2019)","journal-title":"J. Integr. Circ. Syst."},{"key":"2235_CR9","unstructured":"G. Ganesh, V. Charishma, Design of high speed vedic multiplier using vedic mathematics techniques. in International Journal of Scientific and Research Publications (2012)"},{"key":"2235_CR10","doi-asserted-by":"crossref","unstructured":"M. Hisham, S. Yaakob, R. Raof, A. Nazren, N. Embedded, Template matching using sum of squarer unit difference and normalized cross correlation. in IEEE Student Conference on Research and Development (SCOReD) (2015)","DOI":"10.1109\/SCORED.2015.7449303"},{"key":"2235_CR11","first-page":"1","volume":"10","author":"R Jaikumar","year":"2015","unstructured":"R. Jaikumar, M. Karpagam, L. Raju, A novel approach to implement high speed squaring circuit using ancient vedic mathematics techniques. Int. J. Appl. Eng. Res. 10, 1\u20136 (2015)","journal-title":"Int. J. Appl. Eng. Res."},{"key":"2235_CR12","doi-asserted-by":"crossref","unstructured":"M. Joye, Highly regular mary powering ladders. in Springer (2009), p. 350\u2013363","DOI":"10.1007\/978-3-642-05445-7_22"},{"key":"2235_CR13","unstructured":"D. Kumar, A. Kumar, Hardware implementation of 16 * 16 bit multiplier and square using vedic mathematics. in International Conference on Signal, Image and Video Processing (ICSIVP) (2012)"},{"key":"2235_CR14","unstructured":"A. Liddicoat, M.J. Flynn, \u201cParallel square and cube computations,\u201d in Signals, Systems and Computers, 2000. Conference Record of the Thirty-Fourth Asilomar Conference on (2000). p. 1325\u20131329"},{"issue":"5","key":"2235_CR15","doi-asserted-by":"publisher","first-page":"1230","DOI":"10.1109\/TVLSI.2020.2976131","volume":"28","author":"K ManikanttaReddy","year":"2020","unstructured":"K. ManikanttaReddy, M.H. Vasantha, Y.B. NithinKumar, D. Dwivedi, Design of approximate booth squarer for error-tolerant computing. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 28(5), 1230\u20131241 (2020)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"2235_CR16","volume-title":"Power Analysis Attacks of Modular Exponentiation in Smart Cards","author":"T Messerges","year":"1999","unstructured":"T. Messerges, E. Dabbish, R. Sloan, Power Analysis Attacks of Modular Exponentiation in Smart Cards (Springer, Berlin, 1999)"},{"issue":"177","key":"2235_CR17","doi-asserted-by":"publisher","first-page":"243","DOI":"10.1090\/S0025-5718-1987-0866113-7","volume":"48","author":"PL Montgomery","year":"1987","unstructured":"P.L. Montgomery, Speeding the pollard and elliptic curve methods of factorization. Math. Comput. 48(177), 243\u2013264 (1987)","journal-title":"Math. Comput."},{"key":"2235_CR18","doi-asserted-by":"crossref","unstructured":"S. Ourselin, X. Pennec, R. Stefanescu, G. Malandain, N. Ayache. Robust registration of multi-modal medical images: Towards real-time clinical applications. (Doctoral dissertation, INRIA) (2001)","DOI":"10.1007\/3-540-45787-9_18"},{"key":"2235_CR19","unstructured":"M. Poornima, K. Shivaraj, S. Shivukuma, H. Sanjay, Implementation of multiplier using vedic algorithm. in International journal of innovative technology and exploring engineering (IJITEE) (2013)"},{"key":"2235_CR20","unstructured":"S. Ramachandran, S. Kirti, Design, implementation and performance analysis of an integrated vedic multiplier architecture. in International Journal of Computational Engineering Research (IJCER) (2012)"},{"key":"2235_CR21","doi-asserted-by":"crossref","unstructured":"M. Ramalatha, K. Thanushkodi, D. Deena, P. Dharani, A novel time and energy efficient cubing circuit using vedic mathematics for finite field arithmetic. in International Conference on Advances in Recent Technologies in Communication and Computing, Kottayam, Kerala, India (2009)","DOI":"10.1109\/ARTCom.2009.227"},{"key":"2235_CR22","doi-asserted-by":"crossref","unstructured":"M. Rosa, G. Paim, L. Rocha, E. da Costa, and S. Bampi, The radix-$$2^{m}$$ squared multiplier, in 27th IEEE International Conference on Electronics,Circuits and Systems (2020)","DOI":"10.1109\/ICECS49266.2020.9294854"},{"key":"2235_CR23","doi-asserted-by":"crossref","unstructured":"J. Rudagi, V. Amblr, V. Munavalli, R. Patil, V. Sajjan, Design and implementation of efficient multiplier using vedic mathematics. in 3rd International Conference on Advances in Recent Technologies in Communication and Computing (ARTCom 2011) (2011)","DOI":"10.1049\/ic.2011.0071"},{"key":"2235_CR24","unstructured":"D. Sharath, G. Devaraju, C. Kavitha., Optimization and implementation of parallel squarer. IJRET"},{"key":"2235_CR25","doi-asserted-by":"crossref","unstructured":"M. Sharma and G. Singh, Design and fpga implementation of optimized 32-bit vedic multiplier and square architectures. in International Conference on Industrial Instrumentation and Control (ICIC) (2015)","DOI":"10.1109\/IIC.2015.7150883"},{"key":"2235_CR26","unstructured":"P. Shivaraj, Implementation of multiplier using vedic algorithm, Int. J. Innova. Technol. Explor. Eng. (IJITEE) (2013)"},{"issue":"4","key":"2235_CR27","doi-asserted-by":"publisher","first-page":"213","DOI":"10.1007\/s00138-002-0070-5","volume":"13","author":"L Stefano","year":"2003","unstructured":"L. Stefano, S. Mattoccia, Fast template matching using bounded partial correlation. Mach. Vis. Appl. 13(4), 213\u2013221 (2003)","journal-title":"Mach. Vis. Appl."},{"issue":"5","key":"2235_CR28","first-page":"250","volume":"50","author":"A Strollo","year":"2003","unstructured":"A. Strollo, D. De Caro, Booth folding encoding for high performance squarer circuits. IEEE Trans. Circ. Syst. II Anal. Digital Signal Process. 50(5), 250\u2013254 (2003)","journal-title":"IEEE Trans. Circ. Syst. II Anal. Digital Signal Process."},{"key":"2235_CR29","unstructured":"K. Vaithiyanathan, S. Venkatesan, S. Sivaramakrishnan, S. Siva, Simulation and implementation of vedic multiplier using vhdl code. in International Journal of Scientific and Engineering Research (2013)"},{"key":"2235_CR30","doi-asserted-by":"publisher","first-page":"14","DOI":"10.1109\/PGEC.1964.263830","volume":"1","author":"C Wallace","year":"1964","unstructured":"C. Wallace, A suggestion for fast multiplier. IEEE Trans. Eletron. Comput. 1, 14\u201317 (1964)","journal-title":"IEEE Trans. Eletron. Comput."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-022-02235-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-022-02235-9\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-022-02235-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,2,3]],"date-time":"2023-02-03T03:11:21Z","timestamp":1675393881000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-022-02235-9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,11,22]]},"references-count":30,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2023,2]]}},"alternative-id":["2235"],"URL":"https:\/\/doi.org\/10.1007\/s00034-022-02235-9","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2022,11,22]]},"assertion":[{"value":"20 April 2022","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"1 November 2022","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"2 November 2022","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"22 November 2022","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}