{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,2]],"date-time":"2025-11-02T12:28:26Z","timestamp":1762086506154,"version":"build-2065373602"},"reference-count":36,"publisher":"Springer Science and Business Media LLC","issue":"8","license":[{"start":{"date-parts":[[2023,3,11]],"date-time":"2023-03-11T00:00:00Z","timestamp":1678492800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,3,11]],"date-time":"2023-03-11T00:00:00Z","timestamp":1678492800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2023,8]]},"DOI":"10.1007\/s00034-023-02332-3","type":"journal-article","created":{"date-parts":[[2023,3,26]],"date-time":"2023-03-26T22:00:32Z","timestamp":1679868032000},"page":"4784-4808","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Programmable Feedback Shift Register"],"prefix":"10.1007","volume":"42","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5580-2882","authenticated-orcid":false,"given":"Saleh","family":"Abdel-Hafeez","sequence":"first","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2023,3,11]]},"reference":[{"issue":"4","key":"2332_CR1","doi-asserted-by":"publisher","first-page":"938","DOI":"10.1002\/cta.2921","volume":"49","author":"S Abdel-Hafeez","year":"2021","unstructured":"S. Abdel-Hafeez, A. Gordon-Ross, Reconfigurable FIFO memory circuit for synchronous and asynchronous communication. Int. J. Circuit Theory Appl. 49(4), 938\u2013952 (2021)","journal-title":"Int. J. Circuit Theory Appl."},{"issue":"6","key":"2332_CR2","doi-asserted-by":"publisher","first-page":"1023","DOI":"10.1109\/TVLSI.2010.2044818","volume":"19","author":"S Abdel-Hafeez","year":"2011","unstructured":"S. Abdel-Hafeez, A. Gordon-Ross, A digital CMOS parallel counter architecture based on state look-ahead logic. J IEEE Trans Very Large Scale Integr (VLSI) Syst 19(6), 1023\u20131034 (2011)","journal-title":"J IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"2332_CR3","doi-asserted-by":"crossref","unstructured":"P.M. Ajane Furth, E.E. Johnson, R.L. Subramanyam, Comparison of binary and LFSR counters and efficient LFSR decoding algorithm, in IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), (Seoul, 2011), pp. 1\u20134","DOI":"10.1109\/MWSCAS.2011.6026392"},{"key":"2332_CR4","doi-asserted-by":"crossref","unstructured":"A. Alamgir, A.K. Bin A\u2019ain, N. Paraman, U.U. Sheikh, I. Grout, A comparative analysis of LFSR cascading for hardware efficiency and high fault coverage in BIST applications, in IEEE 29th Asian Test Symposium (ATS) (Penang, Malaysia, 2020), pp. 1\u20135","DOI":"10.1109\/ATS49688.2020.9301561"},{"issue":"6","key":"2332_CR5","first-page":"546","volume":"55","author":"W Aloisi","year":"2008","unstructured":"W. Aloisi, R. Mita, Gated-clock design of linear-feedback shift registers. IEEE Trans. Circuits Syst. II 55(6), 546\u2013550 (2008)","journal-title":"IEEE Trans. Circuits Syst. II"},{"issue":"6","key":"2332_CR6","doi-asserted-by":"publisher","first-page":"3766","DOI":"10.1109\/TIT.2019.2956741","volume":"66","author":"Z Chang","year":"2020","unstructured":"Z. Chang, G. Gong, Q. Wang, Cycle structures of a class of cascaded FSRs. IEEE Trans. Inf. Theory 66(6), 3766\u20133774 (2020)","journal-title":"IEEE Trans. Inf. Theory"},{"key":"2332_CR7","doi-asserted-by":"crossref","unstructured":"P. Chen, An all-digital clock generator with modified dynamic frequency counting loop and LFSR dithering, in International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) (Taipei, 2019), pp. 1\u20132","DOI":"10.1109\/ISPACS48206.2019.8986306"},{"key":"2332_CR8","doi-asserted-by":"crossref","unstructured":"I.V. Chugunkov, B.V. Kliuchnikova, V.S. Tsyganov, M.A. Ivanov, V.I. Chugunkov, Pseudorandom number generators with predetermined period and pre-period, in IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus), (St. Petersburg and Moscow, 2020), pp. 268\u2013270","DOI":"10.1109\/EIConRus49466.2020.9039138"},{"key":"2332_CR9","doi-asserted-by":"crossref","unstructured":"D. Datta, B. Datta, H.S. Dutta, Design and implementation of multibit LFSR on FPGA to generate pseudorandom sequence number, in Devices for Integrated Circuit (DevIC) (Kalyani, 2017), pp. 346\u2013349","DOI":"10.1109\/DEVIC.2017.8073966"},{"key":"2332_CR10","volume-title":"ARM: System-On-Chip Architecture","author":"S Furber","year":"2000","unstructured":"S. Furber, ARM: System-On-Chip Architecture, 2nd edn. (Addison-Wesley, New York, 2000)","edition":"2"},{"key":"2332_CR11","doi-asserted-by":"crossref","unstructured":"M. Han, Y. Kim, Unpredictable 16 bits LFSR-based true random number generator, in International SoC Design Conference (ISOCC) (Seoul, 2017), pp. 284\u2013285","DOI":"10.1109\/ISOCC.2017.8368897"},{"issue":"3","key":"2332_CR12","doi-asserted-by":"publisher","first-page":"1159","DOI":"10.1109\/TVLSI.2016.2608921","volume":"25","author":"G Hu","year":"2017","unstructured":"G. Hu, J. Sha, Z. Wang, High-speed parallel LFSR architectures based on improved state-space transformations. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(3), 1159\u20131163 (2017)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"1","key":"2332_CR13","first-page":"156","volume":"70","author":"JL Ima\u00f1a","year":"2021","unstructured":"J.L. Ima\u00f1a, LFSR-based bit-serial GF(2m) GF(2m) multipliers using irreducible trinomials. IEEE Trans. Comput. 70(1), 156\u2013162 (2021)","journal-title":"IEEE Trans. Comput."},{"key":"2332_CR14","doi-asserted-by":"crossref","unstructured":"H. Jiang, C. Li, J. Fan, Research on pseudo-random characteristics of new random components, in International Conference on Artificial Intelligence and Advanced Manufacturing (AIAM) (Dublin, 2019), pp. 163\u2013167","DOI":"10.1109\/AIAM48774.2019.00040"},{"issue":"11","key":"2332_CR15","first-page":"1068","volume":"62","author":"J Jung","year":"2015","unstructured":"J. Jung, H. Yoo, Y. Lee, I. Park, Efficient parallel architecture for linear feedback shift registers. IEEE Trans. Circuits Syst. II 62(11), 1068\u20131072 (2015)","journal-title":"IEEE Trans. Circuits Syst. II"},{"key":"2332_CR16","doi-asserted-by":"crossref","unstructured":"M. Jurecek, J. Bucek, R. L\u00f3rencz, Side-channel attack on the A5\/1 stream cipher, in 22nd Euromicro Conference on Digital System Design (DSD) (Kallithea, 2019), pp. 633\u2013638","DOI":"10.1109\/DSD.2019.00099"},{"issue":"3","key":"2332_CR17","doi-asserted-by":"publisher","first-page":"1783","DOI":"10.1109\/TIT.2011.2174332","volume":"58","author":"S Krishnaswamy","year":"2012","unstructured":"S. Krishnaswamy, H.K. Pillai, On the number of linear feedback shift registers with registercial structure. IEEE Trans. Inf. Theory 58(3), 1783\u20131790 (2012)","journal-title":"IEEE Trans. Inf. Theory"},{"key":"2332_CR18","doi-asserted-by":"crossref","unstructured":"W. Li, X. Yang, A parallel and reconfigurable United Architecture for Fibonacci and Galois LFSR, in 7th International Conference on Intelligent Human-Machine Systems and Cybernetics, (vol. 1, Hangzhou, China, 2015), pp. 203\u2013206","DOI":"10.1109\/IHMSC.2015.265"},{"key":"2332_CR19","doi-asserted-by":"crossref","unstructured":"H. Lv, J. Fang, J. Xie, P. Qi, Generating of a nonlinear pseudorandom sequence using linear feedback shift register, in International Conference on ICT Convergence (ICTC), (Jeju, 2012), pp. 432\u2013435","DOI":"10.1109\/ICTC.2012.6387168"},{"key":"2332_CR20","doi-asserted-by":"crossref","unstructured":"I.Z. Moghadam, A.S. Rostami, M.R. Tanhatalab, Designing a random number generator with novel parallel LFSR substructure for key stream ciphers, in International Conference on Computer Design and Applications (ICCDA 2010) (vol. 5, Qinhuangdao, 2010), pp. V5-598\u2013V5-601","DOI":"10.1109\/ICCDA.2010.5541188"},{"issue":"1","key":"2332_CR21","doi-asserted-by":"publisher","first-page":"103","DOI":"10.1109\/TVLSI.2018.2872021","volume":"27","author":"D Morrison","year":"2019","unstructured":"D. Morrison, D. Delic, M.R. Yuce, J. Redoute, Multistage linear feedback shift register counters with reduced decoding logic in 130-nm CMOS for large-scale array applications. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 27(1), 103\u2013115 (2019)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"2332_CR22","unstructured":"90 \u03bcm CMOS ASIC Process Digests, Taiwan Semiconductor Manufacturing Corporation (Hsinchu, 2005)"},{"key":"2332_CR23","unstructured":"K. Nii, Y. Masuda, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, M. Igarashi, K. Tomita, N. Tsuboi, H. Makino, K. Ishibashi, H. Shinohara, A 65 nm ultra-high-density dual-port SRAM with 0.71um\/sup ~\/ 8T-Cell for SoC, in Symposium on VLSI Circuits, Digest of Technical Papers (Honolulu, 2006)"},{"key":"2332_CR24","unstructured":"B. Nowacki, N. Paulino, J. Goes, A simple 1 GHz non-overlapping two-phase clock generators for SC circuits, in 20th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES) (Gdynia, 2013), pp. 174\u2013178"},{"key":"2332_CR25","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-04101-3","volume-title":"Understanding Cryptography","author":"C Paar","year":"2010","unstructured":"C. Paar, J. Pelzl, Understanding Cryptography (Springer, Berlin, 2010)"},{"key":"2332_CR26","volume-title":"Verilog HDL: A Guide to Digital Design and Synthesis","author":"S Palnitkar","year":"2003","unstructured":"S. Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, 2nd edn. (SunSoft Press, Mountain View, 2003)","edition":"2"},{"issue":"4","key":"2332_CR27","doi-asserted-by":"publisher","first-page":"1011","DOI":"10.1109\/TIM.2019.2909248","volume":"69","author":"AK Panda","year":"2019","unstructured":"A.K. Panda, K.C. Ray, A coupled variable input LCG method and its VLSI architecture for pseudorandom bit generation. IEEE Trans. Instrum. Meas. 69(4), 1011\u20131019 (2019)","journal-title":"IEEE Trans. Instrum. Meas."},{"key":"2332_CR28","doi-asserted-by":"crossref","unstructured":"A.K. Panda, P. Rajput, B. Shukla, FPGA implementation of 8, 16, and 32 Bit LFSR with maximum length feedback polynomial using VHDL, in International Conference on Communication Systems and Network Technologies (Rajkot, 2012), pp. 769\u2013773","DOI":"10.1109\/CSNT.2012.168"},{"issue":"12","key":"2332_CR29","doi-asserted-by":"publisher","first-page":"5238","DOI":"10.1109\/TCAD.2020.2966452","volume":"39","author":"I Pomeranz","year":"2020","unstructured":"I. Pomeranz, Direct computation of LFSR-based stored tests for broadside and skewed-load tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12), 5238\u20135246 (2020)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"2332_CR30","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-82865-2","volume-title":"Analysis and Design of Stream Ciphers","author":"RA Rueppel","year":"1986","unstructured":"R.A. Rueppel, Analysis and Design of Stream Ciphers (Springer, Berlin, 1986)"},{"issue":"4","key":"2332_CR31","doi-asserted-by":"publisher","first-page":"992","DOI":"10.1109\/TVLSI.2019.2963678","volume":"28","author":"SA Salehi","year":"2020","unstructured":"S.A. Salehi, Low-cost stochastic number generators for stochastic computing. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 28(4), 992\u20131001 (2020)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"2332_CR32","unstructured":"A statistical test suit for random and pseudorandom number generators for cryptographic applications, NIST special publications 800\u201322. My (2001)"},{"key":"2332_CR33","doi-asserted-by":"crossref","unstructured":"J. Szmidt, Nonlinear feedback shift registers and Zech\u2019s logarithms, in International Conference on Military Communications and Information Systems (ICMCIS) (Budva, Montenegro, 2019), pp. 1\u20134.","DOI":"10.1109\/ICMCIS.2019.8842713"},{"key":"2332_CR34","doi-asserted-by":"crossref","unstructured":"T. Tuncer, E. Avaro\u011flu, Random number generation with LFSR based stream cipher algorithms, in 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO) (Opatija, 2017), pp. 171\u2013175","DOI":"10.23919\/MIPRO.2017.7973412"},{"issue":"3","key":"2332_CR35","first-page":"412","volume":"66","author":"X Zhang","year":"2019","unstructured":"X. Zhang, A low-power parallel architecture for linear feedback shift registers. IEEE Trans. Circuits Syst. II 66(3), 412\u2013416 (2019)","journal-title":"IEEE Trans. Circuits Syst. II"},{"key":"2332_CR36","doi-asserted-by":"crossref","unstructured":"P. Zode, P. Zode, R. Deshmukh, FPGA based novel true random number generator using LFSR with dynamic seed, in IEEE 16th India Council International Conference (INDICON), (Rajkot, India, 2019), pp. 1\u20133","DOI":"10.1109\/INDICON47234.2019.9029049"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-023-02332-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-023-02332-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-023-02332-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,17]],"date-time":"2024-10-17T01:39:01Z","timestamp":1729129141000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-023-02332-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,3,11]]},"references-count":36,"journal-issue":{"issue":"8","published-print":{"date-parts":[[2023,8]]}},"alternative-id":["2332"],"URL":"https:\/\/doi.org\/10.1007\/s00034-023-02332-3","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2023,3,11]]},"assertion":[{"value":"19 May 2022","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"20 February 2023","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"21 February 2023","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"11 March 2023","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}