{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,23]],"date-time":"2025-09-23T13:24:55Z","timestamp":1758633895738,"version":"3.37.3"},"reference-count":24,"publisher":"Springer Science and Business Media LLC","issue":"10","license":[{"start":{"date-parts":[[2023,5,23]],"date-time":"2023-05-23T00:00:00Z","timestamp":1684800000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,5,23]],"date-time":"2023-05-23T00:00:00Z","timestamp":1684800000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2023,10]]},"DOI":"10.1007\/s00034-023-02397-0","type":"journal-article","created":{"date-parts":[[2023,5,23]],"date-time":"2023-05-23T03:51:50Z","timestamp":1684813910000},"page":"5799-5810","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":6,"title":["Variation-Tolerant Sense Amplifier Using Decoupling Transistors for Enhanced SRAM Read Performance"],"prefix":"10.1007","volume":"42","author":[{"given":"Ayush","family":"Dahiya","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9479-8628","authenticated-orcid":false,"given":"Poornima","family":"Mittal","sequence":"additional","affiliation":[]},{"given":"Rajesh","family":"Rohilla","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2023,5,23]]},"reference":[{"key":"2397_CR1","unstructured":"Arizona State\u00a0University NI, Group M (2008) Predictive Technology Models. http:\/\/ptm.asu.edu\/latest.html"},{"issue":"10","key":"2397_CR2","first-page":"986","volume":"55","author":"AT Do","year":"2008","unstructured":"A.T. Do, Z.H. Kong, K.S. Yeo, Hybrid-mode SRAM sense amplifiers: new approach on transistor sizing. IEEE Trans. Circuits Syst. II Exp. Br. 55(10), 986\u2013990 (2008)","journal-title":"IEEE Trans. Circuits Syst. II Exp. Br."},{"issue":"2","key":"2397_CR3","doi-asserted-by":"publisher","first-page":"196","DOI":"10.1109\/TVLSI.2009.2033110","volume":"19","author":"AT Do","year":"2011","unstructured":"A.T. Do, Z.H. Kong, K.S. Yeo et al., Design and sensitivity analysis of a new current-mode sense amplifier for low-power SRAM. IEEE Trans. Very Large Scale Integr. Syst. (VLSI) 19(2), 196\u2013204 (2011)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst. (VLSI)"},{"issue":"3","key":"2397_CR4","first-page":"285","volume":"20","author":"D Dutt","year":"2022","unstructured":"D. Dutt, P. Mittal, B. Rawat et al., Design and performance analysis of high-performance low power voltage mode sense amplifier for static RAM. Adv. Electr. Electron. Eng. 20(3), 285\u2013293 (2022)","journal-title":"Adv. Electr. Electron. Eng."},{"issue":"5","key":"2397_CR5","doi-asserted-by":"publisher","first-page":"651","DOI":"10.1016\/j.jpdc.2010.09.006","volume":"71","author":"C Hern\u00e1ndez","year":"2011","unstructured":"C. Hern\u00e1ndez, A. Roca, J. Flich et al., Characterizing the impact of process variation on 45 nm NoC-based CMPs. J. Parallel Distrib. Comput. 71(5), 651\u2013663 (2011)","journal-title":"J. Parallel Distrib. Comput."},{"issue":"11","key":"2397_CR6","doi-asserted-by":"publisher","first-page":"2157","DOI":"10.1109\/TCSI.2004.835664","volume":"51","author":"W Marble","year":"2004","unstructured":"W. Marble, K. Kotani, C. Petrie, Practical charge-transfer amplifier design architectures for low-power flash A\/D converters. IEEE Trans. Circuits Syst. I Regul. Pap. 51(11), 2157\u20132164 (2004)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"issue":"5","key":"2397_CR7","doi-asserted-by":"publisher","first-page":"2135","DOI":"10.1007\/s00034-020-01578-5","volume":"40","author":"JK Mishra","year":"2021","unstructured":"J.K. Mishra, B.B. Upadhyay, P.K. Misra et al., Design and analysis of SRAM cell using body bias controller for low power applications. Circuits Syst. Signal Process. 40(5), 2135\u20132158 (2021)","journal-title":"Circuits Syst. Signal Process."},{"key":"2397_CR8","doi-asserted-by":"publisher","first-page":"104491","DOI":"10.1016\/j.micpro.2022.104491","volume":"90","author":"P Mittal","year":"2022","unstructured":"P. Mittal, B. Rawat, N. Kumar, Tetra-variate scrutiny of diverse multiplexer techniques for designing a barrel shifter for low power digital circuits. Microprocess. Microsyst. 90, 104491 (2022)","journal-title":"Microprocess. Microsyst."},{"key":"2397_CR9","doi-asserted-by":"publisher","first-page":"1437","DOI":"10.1007\/s00034-015-0119-0","volume":"35","author":"M Moghaddam","year":"2016","unstructured":"M. Moghaddam, S. Timarchi, M.H. Moaiyeri et al., An ultra-low-power 9T SRAM cell based on threshold voltage techniques. Circuits, Syst., Signal Process. 35, 1437\u20131455 (2016)","journal-title":"Circuits, Syst., Signal Process."},{"key":"2397_CR10","doi-asserted-by":"publisher","first-page":"108216","DOI":"10.1016\/j.compeleceng.2022.108216","volume":"102","author":"S Pandey","year":"2022","unstructured":"S. Pandey, S. Kumar, V. Bhatnagar et al., A low leakage substrate bias-assisted technique for low voltage dual bit-line SRAM. Comput. Electr. Eng. 102, 108216 (2022)","journal-title":"Comput. Electr. Eng."},{"issue":"7","key":"2397_CR11","doi-asserted-by":"publisher","first-page":"2519","DOI":"10.1109\/TCSI.2019.2899314","volume":"66","author":"D Patel","year":"2019","unstructured":"D. Patel, A. Neale, D. Wright et al., Hybrid latch-type offset tolerant sense amplifier for low-voltage SRAMs. IEEE Trans. Circuits Syst. I: Regul. Pap. 66(7), 2519\u20132532 (2019)","journal-title":"IEEE Trans. Circuits Syst. I: Regul. Pap."},{"issue":"8","key":"2397_CR12","doi-asserted-by":"publisher","first-page":"3265","DOI":"10.1109\/TCSI.2021.3081917","volume":"68","author":"D Patel","year":"2021","unstructured":"D. Patel, A. Neale, D. Wright et al., Body biased sense amplifier with auto-offset mitigation for low-voltage SRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8), 3265\u20133278 (2021)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"issue":"9","key":"2397_CR13","doi-asserted-by":"publisher","first-page":"095006","DOI":"10.1088\/1361-6641\/ac07c8","volume":"36","author":"B Rawat","year":"2021","unstructured":"B. Rawat, P. Mittal, A 32 nm single-ended single-port 7T static random access memory for low power utilization. Semicond. Sci. Technol. 36(9), 095006 (2021)","journal-title":"Semicond. Sci. Technol."},{"key":"2397_CR14","doi-asserted-by":"crossref","unstructured":"B. Rawat, P. Mittal, A comprehensive analysis of different 7T SRAM topologies to design a 1R1W bit interleaving enabled and half select free cell for 32 nm technology node. in Proceedings of the Royal Society A: Mathematical, Physical and Engineering Sciences 478(2259), 20210745 (2022)","DOI":"10.1098\/rspa.2021.0745"},{"issue":"5","key":"2397_CR15","doi-asserted-by":"publisher","first-page":"2779","DOI":"10.1007\/s00034-021-01912-5","volume":"41","author":"B Rawat","year":"2022","unstructured":"B. Rawat, P. Mittal, A reliable and temperature variation tolerant 7T SRAM cell with single bitline configuration for low voltage application. Circuits Syst. Signal Process. 41(5), 2779\u20132801 (2022)","journal-title":"Circuits Syst. Signal Process."},{"issue":"3","key":"2397_CR16","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3576198","volume":"28","author":"B Rawat","year":"2023","unstructured":"B. Rawat, P. Mittal, A switching NMOS based single ended sense amplifier for high density SRAM applications. ACM Trans. Des. Autom. Electron. Syst. 28(3), 1\u201314 (2023)","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"key":"2397_CR17","doi-asserted-by":"crossref","unstructured":"D. Schinkel, E. Mensink, E. Klumperink et al., A double-tail latch-type voltage sense amplifier with 18ps setup+ hold time, in 2007 IEEE international solid-state circuits conference. (Digest of technical papers, IEEE, 2007), pp. 314\u2013605","DOI":"10.1109\/ISSCC.2007.373420"},{"issue":"4","key":"2397_CR18","doi-asserted-by":"publisher","first-page":"525","DOI":"10.1109\/4.75050","volume":"26","author":"E Seevinck","year":"1991","unstructured":"E. Seevinck, P.J. van Beers, H. Ontrop, Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM\u2019s. IEEE J. Solid-State Circuits 26(4), 525\u2013536 (1991)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"10","key":"2397_CR19","doi-asserted-by":"publisher","first-page":"2416","DOI":"10.1109\/JSSC.2011.2159056","volume":"46","author":"V Sharma","year":"2011","unstructured":"V. Sharma, S. Cosemans, M. Ashouei et al., A 4.4 pJ\/access 80 MHz, 128 kbit variability resilient SRAM with multi-sized sense amplifier redundancy. IEEE J. Solid-State Circuits 46(10), 2416\u20132430 (2011)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"2397_CR20","doi-asserted-by":"crossref","unstructured":"N. Verma, A.P. Chandrakasan, A 65nm 8T sub-Vt SRAM employing sense-amplifier redundancy, in 2007 IEEE International Solid-State Circuits Conference. (Digest of Technical Papers, IEEE, 2007), pp. 328\u2013606","DOI":"10.1109\/ISSCC.2007.373427"},{"issue":"7","key":"2397_CR21","doi-asserted-by":"publisher","first-page":"1148","DOI":"10.1109\/JSSC.2004.829399","volume":"39","author":"B Wicht","year":"2004","unstructured":"B. Wicht, T. Nirschl, D. Schmitt-Landsiedel, Yield and speed optimization of a latch-type voltage sense amplifier. IEEE J. Solid-State Circuits 39(7), 1148\u20131158 (2004)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"11","key":"2397_CR22","doi-asserted-by":"publisher","first-page":"2600","DOI":"10.1109\/JSSC.2007.907173","volume":"42","author":"M Wieckowski","year":"2007","unstructured":"M. Wieckowski, S. Patil, M. Margala, Portless SRAM-A high-performance alternative to the 6T methodology. IEEE J. Solid-State Circuits 42(11), 2600\u20132610 (2007)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"2397_CR23","doi-asserted-by":"publisher","first-page":"105578","DOI":"10.1016\/j.mejo.2022.105578","volume":"128","author":"Y Zhao","year":"2022","unstructured":"Y. Zhao, J. Wang, Z. Tong et al., An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset. Microelectron. J. 128, 105578 (2022)","journal-title":"Microelectron. J."},{"issue":"1","key":"2397_CR24","doi-asserted-by":"publisher","first-page":"72","DOI":"10.4103\/0256-4602.107343","volume":"30","author":"J Zhu","year":"2013","unstructured":"J. Zhu, N. Bai, J. Wu, A review of sense amplifiers for static random access memory. IETE Tech. Rev. 30(1), 72\u201381 (2013)","journal-title":"IETE Tech. Rev."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-023-02397-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-023-02397-0\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-023-02397-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,11]],"date-time":"2023-08-11T14:07:31Z","timestamp":1691762851000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-023-02397-0"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,5,23]]},"references-count":24,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2023,10]]}},"alternative-id":["2397"],"URL":"https:\/\/doi.org\/10.1007\/s00034-023-02397-0","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2023,5,23]]},"assertion":[{"value":"19 November 2022","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"30 April 2023","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"2 May 2023","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"23 May 2023","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"Not applicable","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}},{"value":"Not applicable","order":3,"name":"Ethics","group":{"name":"EthicsHeading","label":"Code Availability"}}]}}