{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,13]],"date-time":"2026-02-13T20:39:12Z","timestamp":1771015152770,"version":"3.50.1"},"reference-count":30,"publisher":"Springer Science and Business Media LLC","issue":"11","license":[{"start":{"date-parts":[[2023,6,10]],"date-time":"2023-06-10T00:00:00Z","timestamp":1686355200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,6,10]],"date-time":"2023-06-10T00:00:00Z","timestamp":1686355200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2023,11]]},"DOI":"10.1007\/s00034-023-02418-y","type":"journal-article","created":{"date-parts":[[2023,6,10]],"date-time":"2023-06-10T14:01:56Z","timestamp":1686405716000},"page":"6749-6779","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Designing of an 8\u2009\u00d7\u20098 Multiplier with New Inexact 4:2 Compressors for Image Processing Applications"],"prefix":"10.1007","volume":"42","author":[{"given":"Mitra","family":"Rahmani","sequence":"first","affiliation":[]},{"given":"Majid","family":"Babaeinik","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1140-0117","authenticated-orcid":false,"given":"Vahid","family":"Ghods","sequence":"additional","affiliation":[]},{"given":"Hassan","family":"Khalesi","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2023,6,10]]},"reference":[{"key":"2418_CR1","doi-asserted-by":"publisher","first-page":"152859","DOI":"10.1016\/J.AEUE.2019.152859","volume":"110","author":"M Ahmadinejad","year":"2019","unstructured":"M. Ahmadinejad, M.H. Moaiyeri, F. Sabetzadeh, Energy and area efficient inexact compressors for inexact multiplication at nanoscale. AEU-Int. J. Electron. Commun. 110, 152859 (2019). https:\/\/doi.org\/10.1016\/J.AEUE.2019.152859","journal-title":"AEU-Int. J. Electron. Commun."},{"issue":"4","key":"2418_CR2","doi-asserted-by":"publisher","first-page":"1352","DOI":"10.1109\/TVLSI.2016.2643003","volume":"25","author":"O Akbari","year":"2017","unstructured":"O. Akbari et al., Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers. IEEE Trans. Very Large Scale Integr 25(4), 1352\u20131361 (2017). https:\/\/doi.org\/10.1109\/TVLSI.2016.2643003","journal-title":"IEEE Trans. Very Large Scale Integr"},{"issue":"3","key":"2418_CR19","doi-asserted-by":"publisher","first-page":"918","DOI":"10.11591\/ijeecs.v11.i3.pp918-924","volume":"11","author":"RG Deshpande","year":"2018","unstructured":"R.G. Deshpande, L.L. Ragha, S.K. Sharma, Video quality assessment through PSNR estimation for different compression standards. Indones. J. Electr. Eng. Comput. Sci. 11(3), 918\u2013924 (2018). https:\/\/doi.org\/10.11591\/ijeecs.v11.i3.pp918-924","journal-title":"Indones. J. Electr. Eng. Comput. Sci."},{"issue":"08","key":"2418_CR3","doi-asserted-by":"publisher","first-page":"2150138","DOI":"10.1109\/ACCESS.2020.2978773","volume":"30","author":"PJ Edavoor","year":"2021","unstructured":"P.J. Edavoor, S. Raveendran, A.D. Rahulkar, Novel 4: 2 inexact compressor designs for multimedia and neural network applications. J. Circuits, Syst. Comput. 30(08), 2150138 (2021). https:\/\/doi.org\/10.1109\/ACCESS.2020.2978773","journal-title":"J. Circuits, Syst. Comput."},{"key":"2418_CR4","doi-asserted-by":"publisher","first-page":"48337","DOI":"10.1109\/ACCESS.2020.2978773","volume":"8","author":"PJ Edavoor","year":"2020","unstructured":"P.J. Edavoor, S. Raveendran, A.D. Rahulkar, Inexact multiplier design using novel dual-stage 4: 2 compressors. IEEE Access 8, 48337\u201348351 (2020). https:\/\/doi.org\/10.1109\/ACCESS.2020.2978773","journal-title":"IEEE Access"},{"key":"2418_CR5","doi-asserted-by":"publisher","unstructured":"Y. Devi Ykuntam, K. Pavani, K. Saladi, Design and analysis of High speed wallace tree multiplier using parallel prefix adders for VLSI circuit designs, in 2020 11th International Conference on Computing, Communication and Networking Technologies (ICCCNT) (IEEE). https:\/\/doi.org\/10.1109\/ICCCNT49239.2020.9225404","DOI":"10.1109\/ICCCNT49239.2020.9225404"},{"issue":"12","key":"2418_CR6","doi-asserted-by":"publisher","first-page":"4169","DOI":"10.1109\/TCSI.2018.2839266","volume":"65","author":"D Esposito","year":"2018","unstructured":"D. Esposito et al., Inexact multipliers based on new inexact compressors. IEEE Trans. Circuits Syst. I Regul. Pap. 65(12), 4169\u20134182 (2018)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"issue":"3","key":"2418_CR7","doi-asserted-by":"publisher","first-page":"429","DOI":"10.1007\/s10836-020-05883-4","volume":"36","author":"B Garg","year":"2020","unstructured":"B. Garg, S.K. Patel, S. Dutt, LoBA: a leading one bit based inexact multiplier for efficient image processing. J. Electron. Test. 36(3), 429\u2013437 (2020). https:\/\/doi.org\/10.1007\/s10836-020-05883-4","journal-title":"J. Electron. Test."},{"key":"2418_CR8","unstructured":"R. C. Gonzales, R.E. Woods, Digital Image Processing (Pearson Education Inc, 2010)"},{"key":"2418_CR9","doi-asserted-by":"publisher","unstructured":"T. S. Krishna, et al., 15\u20134 Inexact Compressor based multiplier for image processing, in 2nd International Conference on Trends in Electronics and Informatics (ICOEI) (IEEE, 2018). https:\/\/doi.org\/10.1109\/ICOEI.2018.8553734","DOI":"10.1109\/ICOEI.2018.8553734"},{"key":"2418_CR10","doi-asserted-by":"publisher","unstructured":"U. A. Kumar, S. V. Bharadwaj, A. B. Pattaje, S. Nambi, S. E. Ahmed, CAAM: compressor based adaptive inexact multiplier for neural network applications. IEEE Embed. Syst. Lett. (2022). https:\/\/doi.org\/10.1109\/LES.2022.3199273","DOI":"10.1109\/LES.2022.3199273"},{"issue":"03","key":"2418_CR11","doi-asserted-by":"publisher","first-page":"2250049","DOI":"10.1142\/S0218126622500499","volume":"31","author":"UA Kumar","year":"2022","unstructured":"U.A. Kumar et al., A high-speed and power-efficient inexact adder for image processing applications. J. Circuits, Syst. Comput. 31(03), 2250049 (2022)","journal-title":"J. Circuits, Syst. Comput."},{"issue":"2","key":"2418_CR12","doi-asserted-by":"publisher","first-page":"59","DOI":"10.1109\/LES.2021.3113005","volume":"14","author":"UA Kumar","year":"2022","unstructured":"U.A. Kumar, S.K. Chatterjee, S.E. Ahmed, Low-power compressor-based inexact multipliers with error correcting module. IEEE Embed. Syst. Lett. 14(2), 59\u201362 (2022). https:\/\/doi.org\/10.1109\/LES.2021.3113005","journal-title":"IEEE Embed. Syst. Lett."},{"issue":"10","key":"2418_CR13","doi-asserted-by":"publisher","first-page":"1950171","DOI":"10.1142\/S0218126619501718","volume":"28","author":"V Kumar","year":"2019","unstructured":"V. Kumar et al., Power-delay-error-efficient inexact adder for error-resilient applications. J. Circuits, Syst. Comput. 28(10), 1950171 (2019). https:\/\/doi.org\/10.1142\/S0218126619501718","journal-title":"J. Circuits, Syst. Comput."},{"issue":"5","key":"2418_CR14","first-page":"233","volume":"16","author":"J Lee","year":"2021","unstructured":"J. Lee, H. Kim, Highly accurate inexact multiplier using heterogeneous inexact 4\u20132 compressors for error-resilient applications. IEMEK J. Embed. Syst. Appl. 16(5), 233\u2013240 (2021)","journal-title":"IEMEK J. Embed. Syst. Appl."},{"key":"2418_CR15","doi-asserted-by":"publisher","unstructured":"C. H. Lin, C. Lin, High accuracy inexact multiplier with error correction, in 2013 IEEE 31st International Conference on Computer Design (ICCD) (IEEE, 2013). https:\/\/doi.org\/10.1109\/ICCD.2013.6657022","DOI":"10.1109\/ICCD.2013.6657022"},{"issue":"3","key":"2418_CR16","doi-asserted-by":"publisher","first-page":"293","DOI":"10.2298\/SJEE1103293N","volume":"8","author":"R Nirlakalla","year":"2011","unstructured":"R. Nirlakalla, R.T. Subba, T. Jayachandra-Prasad, Performance evaluation of high speed compressors for high speed multipliers. Serb. J. Electr. Eng. 8(3), 293\u2013306 (2011)","journal-title":"Serb. J. Electr. Eng."},{"issue":"02","key":"2418_CR17","doi-asserted-by":"publisher","first-page":"1950019","DOI":"10.1142\/S0218126619500191","volume":"28","author":"R Pinto","year":"2019","unstructured":"R. Pinto, K. Shama, Low-power modified shift-add multiplier design using parallel prefix adder. J. Circuits, Syst. Comput. 28(02), 1950019 (2019). https:\/\/doi.org\/10.1142\/S0218126619500191","journal-title":"J. Circuits, Syst. Comput."},{"issue":"3","key":"2418_CR18","doi-asserted-by":"publisher","first-page":"111","DOI":"10.1109\/CJECE.2013.6704692","volume":"36","author":"A Pishvaie","year":"2013","unstructured":"A. Pishvaie, G. Jaberipur, A. Jahanian, Redesigned CMOS (4; 2) compressor for fast binary multipliers. Can. J. Electr. Comput. Eng. 36(3), 111\u2013115 (2013). https:\/\/doi.org\/10.1109\/CJECE.2013.6704692","journal-title":"Can. J. Electr. Comput. Eng."},{"issue":"8","key":"2418_CR20","doi-asserted-by":"publisher","first-page":"1288","DOI":"10.1080\/00207217.2020.1858973","volume":"108","author":"D Rostami","year":"2021","unstructured":"D. Rostami, M. Eshghi, Y.S. Mehrabani, Low-power and high-speed inexact 4: 2 compressors for image multiplication applications in CNFETs. Int. J. Electron. 108(8), 1288\u20131308 (2021). https:\/\/doi.org\/10.1080\/00207217.2020.1858973","journal-title":"Int. J. Electron."},{"issue":"9","key":"2418_CR21","doi-asserted-by":"publisher","first-page":"4633","DOI":"10.1007\/s00034-021-01688-8","volume":"40","author":"F Salmanpour","year":"2021","unstructured":"F. Salmanpour, M.H. Moaiyeri, F. Sabetzadeh, Ultra-Compact inexact 4: 2 compressor and multiplier circuits for inexact computing in deep nanoscale. Circuits Syst. Signal Process. 40(9), 4633\u20134650 (2021). https:\/\/doi.org\/10.1007\/s00034-021-01688-8","journal-title":"Circuits Syst. Signal Process."},{"key":"2418_CR22","unstructured":"M.M.D. Savio, T. Deepa, Design of higher order multiplier with inexact compressor, in 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)"},{"issue":"1","key":"2418_CR23","doi-asserted-by":"publisher","first-page":"10633","DOI":"10.53730\/ijhs.v6nS1.7546","volume":"6","author":"G Shobana","year":"2022","unstructured":"G. Shobana, R. Chithiraimuthu, A. Adhithyavel, Performance analysis and implementation of inexact multipliers on spartan 6 FPGA. Int. J. Health Sci. 6(1), 10633\u201310652 (2022). https:\/\/doi.org\/10.53730\/ijhs.v6nS1.7546","journal-title":"Int. J. Health Sci."},{"issue":"9","key":"2418_CR24","doi-asserted-by":"publisher","first-page":"4407","DOI":"10.1007\/S00034-021-01671-3","volume":"40","author":"V Solanki","year":"2021","unstructured":"V. Solanki, A.D. Darji, H. Singapuri, Design of low-power wallace tree multiplier architecture using modular approach. Circuits Syst. Signal Process. 40(9), 4407\u20134427 (2021). https:\/\/doi.org\/10.1007\/S00034-021-01671-3","journal-title":"Circuits Syst. Signal Process."},{"issue":"9","key":"2418_CR25","doi-asserted-by":"publisher","first-page":"3021","DOI":"10.1109\/TCSI.2020.2988353","volume":"67","author":"AGM Strollo","year":"2020","unstructured":"A.G.M. Strollo et al., Comparison and extension of inexact 4\u20132 compressors for low-power inexact multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. 67(9), 3021\u20133034 (2020). https:\/\/doi.org\/10.1109\/TCSI.2020.2988353","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"issue":"9","key":"2418_CR26","first-page":"354","volume":"5","author":"W Sulakshana","year":"2022","unstructured":"W. Sulakshana, Design of approximate multiplier to reduce delay and area. Iconic Res. Eng. J. 5(9), 354\u2013358 (2022)","journal-title":"Iconic Res. Eng. J."},{"issue":"12","key":"2418_CR27","doi-asserted-by":"publisher","first-page":"6224","DOI":"10.1007\/S00034-021-01765-Y","volume":"40","author":"K Sundaram","year":"2021","unstructured":"K. Sundaram et al., Area\u2013energy\u2013error optimized faithful multiplier for digital signal processing. Circuits Syst. Signal Process. 40(12), 6224\u20136241 (2021). https:\/\/doi.org\/10.1007\/S00034-021-01765-Y","journal-title":"Circuits Syst. Signal Process."},{"key":"2418_CR28","doi-asserted-by":"publisher","first-page":"25481","DOI":"10.1109\/ACCESS.2020.2970968","volume":"8","author":"N Van Toan","year":"2020","unstructured":"N. Van Toan, J.-G. Lee, FPGA-based multi-level inexact multipliers for high-performance error-resilient applications. IEEE Access 8, 25481\u201325497 (2020). https:\/\/doi.org\/10.1109\/ACCESS.2020.2970968","journal-title":"IEEE Access"},{"issue":"5","key":"2418_CR29","doi-asserted-by":"publisher","first-page":"1782","DOI":"10.1109\/TVLSI.2016.2643639","volume":"25","author":"S Venkatachalam","year":"2017","unstructured":"S. Venkatachalam, S.-B. Ko, Design of power and area efficient inexact multipliers. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(5), 1782\u20131786 (2017). https:\/\/doi.org\/10.1109\/TVLSI.2016.2643639","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"15","key":"2418_CR30","doi-asserted-by":"publisher","first-page":"2050241","DOI":"10.1142\/S0218126620502412","volume":"29","author":"Z Yang","year":"2020","unstructured":"Z. Yang, X. Li, J. Yang, Power efficient and high-accuracy inexact multiplier with error correction. J. Circuits, Syst. Comput. 29(15), 2050241 (2020). https:\/\/doi.org\/10.1142\/S0218126620502412","journal-title":"J. Circuits, Syst. Comput."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-023-02418-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-023-02418-y\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-023-02418-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,5]],"date-time":"2023-10-05T19:05:07Z","timestamp":1696532707000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-023-02418-y"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6,10]]},"references-count":30,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2023,11]]}},"alternative-id":["2418"],"URL":"https:\/\/doi.org\/10.1007\/s00034-023-02418-y","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,6,10]]},"assertion":[{"value":"5 August 2022","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"19 May 2023","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"20 May 2023","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"10 June 2023","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}