{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T00:12:13Z","timestamp":1771459933270,"version":"3.50.1"},"reference-count":41,"publisher":"Springer Science and Business Media LLC","issue":"12","license":[{"start":{"date-parts":[[2023,7,13]],"date-time":"2023-07-13T00:00:00Z","timestamp":1689206400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,7,13]],"date-time":"2023-07-13T00:00:00Z","timestamp":1689206400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61704049"],"award-info":[{"award-number":["61704049"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Key Science and Technology Program of Henan Province","award":["232102211066"],"award-info":[{"award-number":["232102211066"]}]},{"name":"Graduate Quality Project of HAUST","award":["2020ZYL-008"],"award-info":[{"award-number":["2020ZYL-008"]}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2023,12]]},"DOI":"10.1007\/s00034-023-02443-x","type":"journal-article","created":{"date-parts":[[2023,7,13]],"date-time":"2023-07-13T13:01:51Z","timestamp":1689253311000},"page":"7023-7044","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":9,"title":["BP Neural Network Modeling and Solving Acceleration of Analog ICs"],"prefix":"10.1007","volume":"42","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6776-1988","authenticated-orcid":false,"given":"Bo","family":"Liu","sequence":"first","affiliation":[]},{"given":"Weizhe","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Wenjuan","family":"Duan","sequence":"additional","affiliation":[]},{"given":"Qingduan","family":"Meng","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2023,7,13]]},"reference":[{"issue":"4","key":"2443_CR1","doi-asserted-by":"publisher","first-page":"2030","DOI":"10.3906\/elk-1910-16","volume":"28","author":"M Abdel-Majeed","year":"2020","unstructured":"M. Abdel-Majeed, T. Almousa, M. Alsalman, A. Yosf, Sketic: a machine learning-based digital circuit recognition platform. Turkish J. Electr. Eng. Comput. Sci. 28(4), 2030\u20132045 (2020). https:\/\/doi.org\/10.3906\/elk-1910-16","journal-title":"Turkish J. Electr. Eng. Comput. Sci."},{"key":"2443_CR2","doi-asserted-by":"publisher","first-page":"113","DOI":"10.1016\/j.vlsi.2020.11.006","volume":"77","author":"E Afacan","year":"2021","unstructured":"E. Afacan, N.C. Louren\u00e7o, R.M. Martins, G. D\u00fcndar, Review: Machine learning techniques in analog\/RF integrated circuit design, synthesis, layout, and test. Integr VLSI J. 77, 113\u2013130 (2021). https:\/\/doi.org\/10.1016\/j.vlsi.2020.11.006","journal-title":"Integr VLSI J."},{"key":"2443_CR3","doi-asserted-by":"publisher","unstructured":"E. Afacan, M.B. Yelten, G. D\u00fcndar, Review: analog design methodologies for reliability in nanoscale CMOS circuits, in Proceedings of 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017, pp. 1\u20134. https:\/\/doi.org\/10.1109\/SMACD.2017.7981608","DOI":"10.1109\/SMACD.2017.7981608"},{"issue":"2","key":"2443_CR4","doi-asserted-by":"publisher","first-page":"1299","DOI":"10.11591\/ijece.v12i2.pp1299-1307","volume":"12","author":"NT Almalah","year":"2022","unstructured":"N.T. Almalah, F.H. Aldabbagh, Inductanceless high order low frequency filters for medical applications. Int J Electr Comput Eng 12(2), 1299\u20131307 (2022). https:\/\/doi.org\/10.11591\/ijece.v12i2.pp1299-1307","journal-title":"Int J Electr Comput Eng"},{"issue":"4","key":"2443_CR5","doi-asserted-by":"publisher","first-page":"230","DOI":"10.5923\/J.EEE.20120204.09","volume":"2","author":"B Bachir","year":"2012","unstructured":"B. Bachir, A. Ali, M. Abdellah, Multiobjective optimization of an operational amplifier by the ant colony optimisation algorithm. Electr Electron Eng 2(4), 230\u2013235 (2012). https:\/\/doi.org\/10.5923\/J.EEE.20120204.09","journal-title":"Electr Electron Eng"},{"key":"2443_CR6","doi-asserted-by":"publisher","unstructured":"M.F. Barros, J. Guilherme, N.C. Horta, GA-SVM feasibility model and optimization kernel applied to analog IC design automation, in Proceedings of the 17th ACM Great Lakes symposium on VLSI, 2007, pp. 469\u2013472. https:\/\/doi.org\/10.1145\/1228784.1228895","DOI":"10.1145\/1228784.1228895"},{"key":"2443_CR7","doi-asserted-by":"publisher","unstructured":"I. Baturone, S. S\u00e1nchez-Solano, A. Gersnoviez, M. Brox, An automated design flow from linguistic models to piecewise polynomial digital circuits, in Proceedings of the IEEE International Symposium on Circuits and Systems, 2010, pp. 3317\u20133320. https:\/\/doi.org\/10.1109\/ISCAS.2010.5537890","DOI":"10.1109\/ISCAS.2010.5537890"},{"key":"2443_CR8","first-page":"128","volume":"10","author":"B Benhala","year":"2016","unstructured":"B. Benhala, An improved aco algorithm for the analog circuits design optimization. Int. J. Circuits Syst. Signal Process. 10, 128\u2013133 (2016)","journal-title":"Int. J. Circuits Syst. Signal Process."},{"key":"2443_CR9","doi-asserted-by":"publisher","first-page":"29573","DOI":"10.1109\/ACCESS.2021.3058506","volume":"9","author":"M Bucolo","year":"2021","unstructured":"M. Bucolo, A. Buscarino, C. Famoso, L. Fortuna, S. Gagliano, Imperfections in integrated devices allow the emergence of unexpected strange attractors in electronic circuits. IEEE Access 9, 29573\u201329583 (2021). https:\/\/doi.org\/10.1109\/ACCESS.2021.3058506","journal-title":"IEEE Access"},{"issue":"5","key":"2443_CR10","doi-asserted-by":"publisher","first-page":"1209","DOI":"10.1109\/TCAD.2021.3081405","volume":"41","author":"AF Budak","year":"2021","unstructured":"A.F. Budak, M. Gandara, W. Shi, D.Z. Pan, N. Sun, B. Liu, An efficient analog circuit sizing method based on machine learning assisted global optimization. IEEE Trans Comput Aided Des Integr Circuits Syst. 41(5), 1209\u20131221 (2021). https:\/\/doi.org\/10.1109\/TCAD.2021.3081405","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst."},{"key":"2443_CR11","doi-asserted-by":"publisher","unstructured":"Z. Cashero, A. Chen, R. Hoppal, T. Chen, Fast evaluation of analog circuits using linear programming, in Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2010, pp. 253\u2013258. https:\/\/doi.org\/10.1109\/ISVLSI.2010.94","DOI":"10.1109\/ISVLSI.2010.94"},{"issue":"5","key":"2443_CR12","doi-asserted-by":"publisher","first-page":"2530","DOI":"10.1152\/JN.00692.2001","volume":"88","author":"JR Cavanaugh","year":"2002","unstructured":"J.R. Cavanaugh, W. Bair, J.A. Movshon, Nature and interaction of signals from the receptive field center and surround in macaque V1 neurons. J. Neurophysiol. 88(5), 2530\u20132546 (2002). https:\/\/doi.org\/10.1152\/JN.00692.2001","journal-title":"J. Neurophysiol."},{"issue":"4","key":"2443_CR13","doi-asserted-by":"publisher","first-page":"621","DOI":"10.1007\/S13042-014-0299-0","volume":"6","author":"BP De","year":"2015","unstructured":"B.P. De, R. Kar, D. Mandal, S.P. Ghoshal, Optimal selection of components value for analog active filter design using simplex particle swarm optimization. Int. J. Mach. Learn. Cybern. 6(4), 621\u2013636 (2015). https:\/\/doi.org\/10.1007\/S13042-014-0299-0","journal-title":"Int. J. Mach. Learn. Cybern."},{"issue":"3","key":"2443_CR14","doi-asserted-by":"publisher","first-page":"1229","DOI":"10.3390\/app12031229","volume":"12","author":"M Faseehuddin","year":"2022","unstructured":"M. Faseehuddin, N. Herencsar, S. Shireen, W. Tangsrirat, S.H. Md Ali, Voltage differencing buffered amplifier-based novel truly mixed-mode biquadratic universal filter with versatile input\/output features. Appl. Sci. 12(3), 1229 (2022). https:\/\/doi.org\/10.3390\/app12031229","journal-title":"Appl. Sci."},{"issue":"1","key":"2443_CR15","doi-asserted-by":"publisher","first-page":"18","DOI":"10.1007\/s00034-022-02219-9","volume":"9","author":"K Gaj","year":"1999","unstructured":"K. Gaj, Q. Herr, V. Adler, A. Krasniewski, E.G. Friedman, M.J. Feldman, Tools for the computer-aided design of multigigahertz superconducting digital circuits. IEEE Trans. Appl. Supercond. 9(1), 18\u201338 (1999). https:\/\/doi.org\/10.1007\/s00034-022-02219-9","journal-title":"IEEE Trans. Appl. Supercond."},{"key":"2443_CR16","doi-asserted-by":"publisher","unstructured":"S. Indrapriyadarsini, S. Mahboubi, H. Ninomiya, T. Kamio, H. Asai, A neural network approach to analog circuit design optimization using nesterov's accelerated quasi-newton method, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1\u20131. https:\/\/doi.org\/10.1109\/ISCAS45731.2020.9181152","DOI":"10.1109\/ISCAS45731.2020.9181152"},{"key":"2443_CR17","doi-asserted-by":"publisher","unstructured":"W. Jiang, Y. Zhang, R. Wang, Comparative study on several PSO algorithms, in Proceedings of the 26th IEEE Chinese Control and Decision Conference, 2014. pp. 1117\u20131119. https:\/\/doi.org\/10.1109\/CCDC.2014.6852332","DOI":"10.1109\/CCDC.2014.6852332"},{"key":"2443_CR18","doi-asserted-by":"publisher","first-page":"220","DOI":"10.1016\/j.vlsi.2016.07.001","volume":"55","author":"OB Kchaou","year":"2016","unstructured":"O.B. Kchaou, A. Garbaya, M. Kotti, P. Pereira, M. Fakhfakh, M.H. Fino, Sensitivity aware NSGA-II based Pareto front generation for the optimal sizing of analog circuits. Integr. VLSI J. 55, 220\u2013226 (2016). https:\/\/doi.org\/10.1016\/j.vlsi.2016.07.001","journal-title":"Integr. VLSI J."},{"key":"2443_CR19","doi-asserted-by":"publisher","first-page":"154122","DOI":"10.1016\/j.aeue.2022.154122","volume":"146","author":"M Kumngern","year":"2022","unstructured":"M. Kumngern, F. Khateb, T. Kulej, D. Arbet, M. Akbari, Fully differential fifth-order dual-notch low-pass filter for portable EEG system. AEU Int J Electron Commun. 146, 154122 (2022). https:\/\/doi.org\/10.1016\/j.aeue.2022.154122","journal-title":"AEU Int J Electron Commun."},{"key":"2443_CR20","doi-asserted-by":"publisher","unstructured":"J.R. Lakowicz, Instrumentation for fluorescence spectroscopy, in Principles of Fluorescence Spectroscopy, (Springer, 1999) pp. 25\u201361. https:\/\/doi.org\/10.1007\/978-1-4615-7658-7_2","DOI":"10.1007\/978-1-4615-7658-7_2"},{"key":"2443_CR21","doi-asserted-by":"publisher","unstructured":"Y. Li, Y. Lin, M. Madhusudan, A.K. Sharma, W. Xu, S.S. Sapatnekar, R. Harjani, J. Hu, A customized graph neural network model for guiding analog IC placement, in Proceedings of the 2020 IEEE\/ACM International Conference On Computer Aided Design (ICCAD), 2020, pp. 1\u20139. https:\/\/doi.org\/10.1145\/3400302.3415624","DOI":"10.1145\/3400302.3415624"},{"issue":"4","key":"2443_CR22","doi-asserted-by":"publisher","first-page":"47","DOI":"10.1145\/3182169","volume":"23","author":"B Liu","year":"2018","unstructured":"B. Liu, G. Chen, B. Yang, S. Nakatake, Routable and matched layout styles for analog module generation. ACM Trans. Des. Autom. Electron. Syst. 23(4), 47 (2018). https:\/\/doi.org\/10.1145\/3182169","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"key":"2443_CR23","doi-asserted-by":"publisher","first-page":"47","DOI":"10.1016\/j.vlsi.2022.01.003","volume":"84","author":"M Mahendra","year":"2022","unstructured":"M. Mahendra, S. Kumari, M. Gupta, Low voltage fully differential OTA using DTMOS based self cascode transistor with slew-rate enhancement and its filter application. Integr. VLSI J. 84, 47\u201361 (2022). https:\/\/doi.org\/10.1016\/j.vlsi.2022.01.003","journal-title":"Integr. VLSI J."},{"issue":"1","key":"2443_CR24","doi-asserted-by":"publisher","first-page":"188","DOI":"10.1109\/TCAD.2007.907284","volume":"27","author":"SK Mandal","year":"2008","unstructured":"S.K. Mandal, S. Sural, A. Patra, ANN-and PSO-based synthesis of on-chip spiral inductors for RF ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1), 188\u2013192 (2008). https:\/\/doi.org\/10.1109\/TCAD.2007.907284","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"issue":"12","key":"2443_CR25","doi-asserted-by":"publisher","first-page":"1518","DOI":"10.1109\/43.552084","volume":"15","author":"H Murata","year":"1996","unstructured":"H. Murata, K. Fujiyoshi, S. Nakatake, Y. Kajitani, VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12), 1518\u20131524 (1996). https:\/\/doi.org\/10.1109\/43.552084","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"issue":"6","key":"2443_CR26","doi-asserted-by":"publisher","first-page":"519","DOI":"10.1109\/43.703832","volume":"17","author":"S Nakatake","year":"1998","unstructured":"S. Nakatake, K. Fujiyoshi, H. Murata, Y. Kajitani, Module placement on BSG-structure and IC layout applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(6), 519\u2013530 (1998). https:\/\/doi.org\/10.1109\/43.703832","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"issue":"4","key":"2443_CR27","doi-asserted-by":"publisher","first-page":"501","DOI":"10.1109\/43.3185","volume":"7","author":"W Nye","year":"1988","unstructured":"W. Nye, D.C. Riley, A.L. Sangiovanni-Vincentelli, A.L. Tits, DELIGHT. SPICE: an optimization-based system for the design of integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(4), 501\u2013519 (1988). https:\/\/doi.org\/10.1109\/43.3185","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"issue":"9","key":"2443_CR28","doi-asserted-by":"publisher","first-page":"1215","DOI":"10.1109\/5.237532","volume":"81","author":"JW Picone","year":"1993","unstructured":"J.W. Picone, Signal modeling techniques in speech recognition. Proc. IEEE 81(9), 1215\u20131247 (1993). https:\/\/doi.org\/10.1109\/5.237532","journal-title":"Proc. IEEE"},{"key":"2443_CR29","doi-asserted-by":"publisher","unstructured":"A. Pradhan, R.Vemuri, Efficient synthesis of a uniformly spread layout aware pareto surface for analog circuits, in Proceedings of the IEEE 22nd International Conference on VLSI Design, 2009, pp. 131\u2013136. https:\/\/doi.org\/10.1109\/VLSI.Design.2009.67","DOI":"10.1109\/VLSI.Design.2009.67"},{"issue":"11","key":"2443_CR30","doi-asserted-by":"publisher","first-page":"2595","DOI":"10.1109\/TVLSI.2014.2377013","volume":"23","author":"L Qian","year":"2015","unstructured":"L. Qian, Z. Bi, D. Zhou, X. Zeng, Automated technology migration methodology for mixed-signal circuit based on multistart optimization framework. IEEE Trans Very Large Scale Integr Syst. 23(11), 2595\u20132605 (2015). https:\/\/doi.org\/10.1109\/TVLSI.2014.2377013","journal-title":"IEEE Trans Very Large Scale Integr Syst."},{"key":"2443_CR31","doi-asserted-by":"publisher","unstructured":"J. Rosa, D. Guerra, N.C. Horta, R.M. Martins, N.C. Louren\u00e7o, in Using Artificial Neural Networks for Analog Integrated Circuit Design Automation, vol. 1, (Springer, 2020). https:\/\/doi.org\/10.1007\/978-3-030-35743-6","DOI":"10.1007\/978-3-030-35743-6"},{"key":"2443_CR32","doi-asserted-by":"publisher","unstructured":"J. Rosa, D. Guerra, N.C. Horta, R.M. Martins, N.C. Louren\u00e7o, in Using ANNS to Size Analog Integrated Circuits, (Springer, 2020) pp. 45\u201366. https:\/\/doi.org\/10.1007\/978-3-030-35743-6_4","DOI":"10.1007\/978-3-030-35743-6_4"},{"key":"2443_CR33","doi-asserted-by":"publisher","unstructured":"L.C. Severo, W. Van Noije, Single stage OTA and negative transconductance compensation. in Ultra-low Voltage Low Power Active-RC Filters and Amplifiers for Low Energy RF Receivers, (Springer, 2022) pp. 33\u201359. https:\/\/doi.org\/10.1007\/978-3-030-90103-5_3","DOI":"10.1007\/978-3-030-90103-5_3"},{"issue":"2","key":"2443_CR34","doi-asserted-by":"publisher","first-page":"98","DOI":"10.1109\/MSSC.2019.2910646","volume":"11","author":"Y Wang","year":"2019","unstructured":"Y. Wang, G.C. Temes, Scaling for optimum dynamic range and noise-power tradeoff: a review of analog circuit design techniques. IEEE Solid-State Circuits Mag. 11(2), 98\u2013103 (2019). https:\/\/doi.org\/10.1109\/MSSC.2019.2910646","journal-title":"IEEE Solid-State Circuits Mag."},{"key":"2443_CR35","doi-asserted-by":"publisher","unstructured":"Z. Wang, X. Luo, Z. Gong, Application of deep learning in analog circuit sizing. in Proceedings of the 2018 2nd ACM International Conference on Computer Science and Artificial Intelligence, 2018. pp. 571\u2013575. https:\/\/doi.org\/10.1145\/3297156.3297160","DOI":"10.1145\/3297156.3297160"},{"issue":"6","key":"2443_CR36","doi-asserted-by":"publisher","first-page":"1544","DOI":"10.1109\/72.548188","volume":"7","author":"Y Xia","year":"1996","unstructured":"Y. Xia, A new neural network for solving linear and quadratic programming problems. IEEE Trans. Neural Netw. 7(6), 1544\u20131548 (1996). https:\/\/doi.org\/10.1109\/72.548188","journal-title":"IEEE Trans. Neural Netw."},{"key":"2443_CR37","doi-asserted-by":"publisher","unstructured":"B. Xu, K. Zhu, M. Liu, Y. Lin, S. Li, X. Tang, N. Sun, D.Z. Pan, MAGICAL: toward fully automated analog IC layout leveraging human and machine intelligence: invited paper, in Proceedings of the 2019 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), 2019, pp. 1\u20138. https:\/\/doi.org\/10.1109\/ICCAD45719.2019.8942060","DOI":"10.1109\/ICCAD45719.2019.8942060"},{"key":"2443_CR38","doi-asserted-by":"publisher","unstructured":"Y. Xu, K. Hsiung, X. Li, I. Nausieda, S.P. Boyd, L.T. Pileggi, OPERA: optimization with ellipsoidal uncertainty for robust analog IC design, in Proceedings of the 42nd Design Automation Conference (DAC) 2015, pp. 632\u2013637. https:\/\/doi.org\/10.1109\/DAC.2005.193888","DOI":"10.1109\/DAC.2005.193888"},{"key":"2443_CR39","doi-asserted-by":"publisher","unstructured":"S. Zhang, W. Lyu, F. Yang, C. Yan, D. Zhou, X. Zeng, Bayesian optimization approach for analog circuit synthesis using neural network, in Proceedings of the IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, pp. 1463\u20131468. https:\/\/doi.org\/10.23919\/DATE.2019.8714788","DOI":"10.23919\/DATE.2019.8714788"},{"key":"2443_CR40","doi-asserted-by":"publisher","unstructured":"Z. Zhao, L. Zhang, Deep reinforcement learning for analog circuit sizing, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1\u20135. https:\/\/doi.org\/10.1109\/ISCAS45731.2020.9181149","DOI":"10.1109\/ISCAS45731.2020.9181149"},{"issue":"12","key":"2443_CR41","doi-asserted-by":"publisher","first-page":"5182","DOI":"10.1109\/TCAD.2022.3166637","volume":"41","author":"R Zhou","year":"2022","unstructured":"R. Zhou, P. Poechmueller, Y. Wang, An analog circuit design and optimization system with rule-guided genetic algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12), 5182\u20135192 (2022). https:\/\/doi.org\/10.1109\/TCAD.2022.3166637","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-023-02443-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-023-02443-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-023-02443-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,17]],"date-time":"2023-10-17T15:07:59Z","timestamp":1697555279000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-023-02443-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,7,13]]},"references-count":41,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2023,12]]}},"alternative-id":["2443"],"URL":"https:\/\/doi.org\/10.1007\/s00034-023-02443-x","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,7,13]]},"assertion":[{"value":"17 August 2022","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"26 June 2023","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"26 June 2023","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"13 July 2023","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare that they have no known conflict of interests that could have appeared to influence the work reported in this study.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}},{"value":"This article does not contain any studies with human participants or animals performed by any of the authors.","order":3,"name":"Ethics","group":{"name":"EthicsHeading","label":"Ethical Approval"}},{"value":"Informed consent was obtained from all individual participants included in the study.","order":4,"name":"Ethics","group":{"name":"EthicsHeading","label":"Informed Consent"}},{"value":"This manuscript is approved by all authors for publication.","order":5,"name":"Ethics","group":{"name":"EthicsHeading","label":"Consent to Participate"}}]}}