{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T15:03:37Z","timestamp":1773414217673,"version":"3.50.1"},"reference-count":52,"publisher":"Springer Science and Business Media LLC","issue":"12","license":[{"start":{"date-parts":[[2023,8,1]],"date-time":"2023-08-01T00:00:00Z","timestamp":1690848000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,8,1]],"date-time":"2023-08-01T00:00:00Z","timestamp":1690848000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["2138253"],"award-info":[{"award-number":["2138253"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Rezonent Inc.","award":["CORP0061"],"award-info":[{"award-number":["CORP0061"]}]},{"DOI":"10.13039\/100006636","name":"University of Maryland, Baltimore County","doi-asserted-by":"publisher","award":["Startup Grant"],"award-info":[{"award-number":["Startup Grant"]}],"id":[{"id":"10.13039\/100006636","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2023,12]]},"DOI":"10.1007\/s00034-023-02458-4","type":"journal-article","created":{"date-parts":[[2023,8,1]],"date-time":"2023-08-01T18:02:17Z","timestamp":1690912937000},"page":"7549-7579","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Design Automation of Series Resonance Clocking in 14-nm FinFETs"],"prefix":"10.1007","volume":"42","author":[{"given":"Dhandeep","family":"Challagundla","sequence":"first","affiliation":[]},{"given":"Ignatius","family":"Bezzam","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4649-3467","authenticated-orcid":false,"given":"Riadul","family":"Islam","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2023,8,1]]},"reference":[{"key":"2458_CR1","doi-asserted-by":"publisher","first-page":"113","DOI":"10.1007\/s10470-014-0447-1","volume":"82","author":"I Bezzam","year":"2015","unstructured":"I. Bezzam, S. Krishnan, C. Mathiazhagan, T. Raja, F. Maloberti, Wide operating frequency resonant clock and data circuits for switching power reductions. Analog. Integr. Circ. Sig. Process 82, 113\u2013124 (2015). https:\/\/doi.org\/10.1007\/s10470-014-0447-1","journal-title":"Analog. Integr. Circ. Sig. Process"},{"issue":"7","key":"2458_CR2","doi-asserted-by":"publisher","first-page":"1766","DOI":"10.1109\/TCSI.2015.2423797","volume":"62","author":"I Bezzam","year":"2015","unstructured":"I. Bezzam, C. Mathiazhagan, T. Raja, S. Krishnan, An energy-recovering reconfigurable series resonant clocking scheme for wide frequency operation. Trans. Circ. Syst. I. 62(7), 1766\u20131775 (2015). https:\/\/doi.org\/10.1109\/TCSI.2015.2423797","journal-title":"Trans. Circ. Syst. I."},{"key":"2458_CR3","unstructured":"I. Bezzam, Reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. (2019). https:\/\/patents.google.com\/patent\/US10340895B2"},{"key":"2458_CR4","unstructured":"I. Bezzam, Rawat Neelam, Digital circuits for radically reduced power and improved timing performance on advanced semiconductor manufacturing processes. (2021). https:\/\/patents.google.com\/patent\/US11073861B2"},{"key":"2458_CR5","doi-asserted-by":"publisher","unstructured":"F. Brglez, D. Bryan, K. Kozminski, Combinational profiles of sequential benchmark circuits, in International Symposium on Circuits and Systems (ISCAS), (1989), pp. 1929\u20131934 https:\/\/doi.org\/10.1109\/ISCAS.1989.100747","DOI":"10.1109\/ISCAS.1989.100747"},{"issue":"2","key":"2458_CR6","doi-asserted-by":"publisher","first-page":"550","DOI":"10.1109\/JSSC.2018.2875089","volume":"54","author":"Y Cai","year":"2019","unstructured":"Y. Cai, A. Savanth, P. Prabhat, J. Myers, A. Weddell, T. Kazmierski, Ultra-low power 18-transistor fully static contention-free single-phase clocked flip-flop in 65-nm CMOS. J. Solid-State Circ. 54(2), 550\u2013559 (2019). https:\/\/doi.org\/10.1109\/JSSC.2018.2875089","journal-title":"J. Solid-State Circ."},{"key":"2458_CR7","doi-asserted-by":"publisher","unstructured":"D. Challagundla, M. Galib, I. Bezzam, R. Islam, Power and skew reduction using resonant energy recycling in 14-nm FinFET clocks, in 2022 IEEE International Symposium on Circuits and Systems (ISCAS), (2022), pp. 268\u2013272 https:\/\/doi.org\/10.1109\/ISCAS48785.2022.9937771","DOI":"10.1109\/ISCAS48785.2022.9937771"},{"key":"2458_CR8","doi-asserted-by":"publisher","unstructured":"L. Cherif, M. Chentouf, J. Benallal, M. Darmi, R. Elgouri, N. Hmina, Usage and impact of multi-bit flip-flops low power methodology on physical implementation, in 2018 4th International Conference on Optimization and Applications (ICOA), (2018), pp. 1\u20135 https:\/\/doi.org\/10.1109\/ICOA.2018.8370498","DOI":"10.1109\/ICOA.2018.8370498"},{"issue":"7","key":"2458_CR9","doi-asserted-by":"publisher","first-page":"105","DOI":"10.1016\/j.mejo.2016.04.006","volume":"53","author":"LT Clark","year":"2016","unstructured":"L.T. Clark, V. Vashishtha, L. Shifren, A. Gujja, S. Sinha, B. Cline, C. Ramamurthy, G. Yeric, ASAP7: a 7-nm finFET predictive process design kit. Microelectron. J. 53(7), 105\u2013115 (2016). https:\/\/doi.org\/10.1016\/j.mejo.2016.04.006","journal-title":"Microelectron. J."},{"key":"2458_CR10","unstructured":"D. Edwards, H. Nguyen, Semiconductor and IC Package Thermal Metrics (rev. C), Texas Instruments. https:\/\/www.ti.com\/lit\/an\/spra953c\/spra953c.pdf"},{"issue":"7","key":"2458_CR11","doi-asserted-by":"publisher","first-page":"1803","DOI":"10.1109\/TCSI.2017.2680433","volume":"64","author":"WM Elsharkasy","year":"2017","unstructured":"W.M. Elsharkasy, A. Khajeh, A.M. Eltawil, F.J. Kurdahi, Reliability enhancement of low-power sequential circuits using reconfigurable pulsed latches. Trans. Circ. Syst. I. 64(7), 1803\u20131814 (2017). https:\/\/doi.org\/10.1109\/TCSI.2017.2680433","journal-title":"Trans. Circ. Syst. I."},{"key":"2458_CR12","doi-asserted-by":"publisher","unstructured":"S.E. Esmaeili, R. Islam, A.J Al-Khalili, G.E.R. Cowan, Dual-edge triggered sense amplifier flip-flop utilizing an improved scheme to reduce area, power, and complexity, in 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), (2012), pp. 292\u2013295 https:\/\/doi.org\/10.1109\/ICECS.2012.6463565","DOI":"10.1109\/ICECS.2012.6463565"},{"key":"2458_CR13","doi-asserted-by":"publisher","unstructured":"H.A Fahmy, P-Y. Lin, R. Islam, M.R. Guthaus, Switched capacitor quasi-adiabatic clocks, in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), (2015), pp. 1398\u20131401 https:\/\/doi.org\/10.1109\/ISCAS.2015.7168904","DOI":"10.1109\/ISCAS.2015.7168904"},{"key":"2458_CR14","doi-asserted-by":"publisher","unstructured":"T. Fischer, S. Arekapudi, E. Busta, C. Dietz, M. Golden, S. Hilker, A. Horiuchi, K.A. Hurd, D. Johnson, H. McIntyre, S. Naffziger, J. Vinh, J. White, K. Wilcox, Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU. In International Solid-State Circuits Conference, (2011), pp. 78\u201380 https:\/\/doi.org\/10.1109\/ISSCC.2011.5746227","DOI":"10.1109\/ISSCC.2011.5746227"},{"issue":"2","key":"2458_CR15","doi-asserted-by":"publisher","first-page":"536","DOI":"10.1109\/JSSC.2013.2294172","volume":"49","author":"H Fuketa","year":"2014","unstructured":"H. Fuketa, M. Nomura, M. Takamiya, T. Sakurai, Intermittent resonant clocking enabling power reduction at any clock frequency for near\/sub-threshold logic circuits. J. Solid-State Circ. 49(2), 536\u2013544 (2014). https:\/\/doi.org\/10.1109\/JSSC.2013.2294172","journal-title":"J. Solid-State Circ."},{"key":"2458_CR16","doi-asserted-by":"publisher","unstructured":"J.L. Hennessy, D.A. Patterson, A New Golden Age for Computer Architecture. (2019), pp. 48\u201360 https:\/\/doi.org\/10.1145\/3282307","DOI":"10.1145\/3282307"},{"issue":"11","key":"2458_CR17","doi-asserted-by":"publisher","first-page":"2749","DOI":"10.1109\/TCSI.2012.2190671","volume":"59","author":"X Hu","year":"2012","unstructured":"X. Hu, M.R. Guthaus, Distributed LC resonant clock grid synthesis. Trans. Circ. Syst. I. 59(11), 2749\u20132760 (2012). https:\/\/doi.org\/10.1109\/TCSI.2012.2190671","journal-title":"Trans. Circ. Syst. I."},{"key":"2458_CR18","doi-asserted-by":"publisher","unstructured":"X. Hu, W. Condley, M.R. Guthaus, Library-Aware Resonant Clock Synthesis (LARCS), in Proceedings of the 49th Annual Design Automation Conference, (2012), pp. 145\u2013150 https:\/\/doi.org\/10.1145\/2228360.2228389","DOI":"10.1145\/2228360.2228389"},{"issue":"4","key":"2458_CR19","doi-asserted-by":"publisher","first-page":"1383","DOI":"10.1109\/TCSII.2020.3029203","volume":"68","author":"R Islam","year":"2021","unstructured":"R. Islam, B. Saha, I. Bezzam, Resonant energy recycling SRAM architecture. Trans. Circ. Syst. II. 68(4), 1383\u20131387 (2021). https:\/\/doi.org\/10.1109\/TCSII.2020.3029203","journal-title":"Trans. Circ. Syst. II."},{"issue":"3","key":"2458_CR20","doi-asserted-by":"publisher","first-page":"1054","DOI":"10.1109\/TVLSI.2016.2605580","volume":"25","author":"R Islam","year":"2017","unstructured":"R. Islam, M.R. Guthaus, CMCS: current-mode clock synthesis. Trans. Very Large Scale Integr. (VLSI) Syst. 25(3), 1054\u20131062 (2017). https:\/\/doi.org\/10.1109\/TVLSI.2016.2605580","journal-title":"Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"1","key":"2458_CR21","doi-asserted-by":"publisher","first-page":"251","DOI":"10.1109\/TCSI.2018.2866224","volume":"66","author":"R Islam","year":"2019","unstructured":"R. Islam, M.R. Guthaus, HCDN: hybrid-mode clock distribution networks. Trans. Circ. Syst. I. 66(1), 251\u2013262 (2019). https:\/\/doi.org\/10.1109\/TCSI.2018.2866224","journal-title":"Trans. Circ. Syst. I."},{"key":"2458_CR22","doi-asserted-by":"publisher","first-page":"471","DOI":"10.1007\/s10836-018-5737-6","volume":"34","author":"R Islam","year":"2018","unstructured":"R. Islam, Low-power resonant clocking using soft error robust energy recovery flip-flops. J. Electron. Test. 34, 471\u2013485 (2018). https:\/\/doi.org\/10.1007\/s10836-018-5737-6","journal-title":"J. Electron. Test."},{"issue":"10","key":"2458_CR23","doi-asserted-by":"publisher","first-page":"2108","DOI":"10.1109\/TVLSI.2018.2837681","volume":"26","author":"R Islam","year":"2018","unstructured":"R. Islam, H.A. Fahmy, P.Y. Lin, M.R. Guthaus, DCMCS: highly robust low-power differential current-mode clocking and synthesis. Trans. Very Large Scale Integr. VLSI Syst. 26(10), 2108\u20132117 (2018). https:\/\/doi.org\/10.1109\/TVLSI.2018.2837681","journal-title":"Trans. Very Large Scale Integr. VLSI Syst."},{"key":"2458_CR24","unstructured":"R. Islam, High-Speed Energy-Efficient Soft Error Tolerant Flip-flops (2011). https:\/\/spectrum.library.concordia.ca\/id\/eprint\/15130\/"},{"key":"2458_CR25","doi-asserted-by":"publisher","unstructured":"R. Islam, H.A. Fahmy, P.Y. Lin, M.R. Guthaus, Differential current-mode clock distribution, in 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), (2015), pp. 1\u20134 https:\/\/doi.org\/10.1109\/MWSCAS.2015.7282042","DOI":"10.1109\/MWSCAS.2015.7282042"},{"key":"2458_CR26","unstructured":"ISPD-2009, Proceedings of the 2009 International Symposium on Physical Design, (2009). https:\/\/www.ispd.cc\/contests\/09\/ispd09cts.html"},{"key":"2458_CR27","doi-asserted-by":"publisher","unstructured":"S.M Jahinuzzaman, R. Islam, TSPC-DICE: A single phase clock high performance SEU hardened flip-flop, in 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, (2010), pp. 73\u201376 https:\/\/doi.org\/10.1109\/MWSCAS.2010.5548564","DOI":"10.1109\/MWSCAS.2010.5548564"},{"issue":"4","key":"2458_CR28","doi-asserted-by":"publisher","first-page":"609","DOI":"10.1109\/TVLSI.2017.2777788","volume":"26","author":"H Jeong","year":"2018","unstructured":"H. Jeong, T.W. Oh, S.C. Song, S.O. Jung, Sense-amplifier-based flip-flop with transition completion detection for low-voltage operation. Trans. Very Large Scale Integr. (VLSI) Syst. 26(4), 609\u2013620 (2018). https:\/\/doi.org\/10.1109\/TVLSI.2017.2777788","journal-title":"Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"2458_CR29","doi-asserted-by":"publisher","first-page":"27859","DOI":"10.1109\/ACCESS.2019.2901411","volume":"7","author":"AA Khan","year":"2019","unstructured":"A.A. Khan, A. Ali, M. Zakarya, R. Khan, M. Khan, I.U. Rahman, M.A.A. Rahman, A migration aware scheduling technique for real-time aperiodic tasks over multiprocessor systems. IEEE Access. 7, 27859\u201327873 (2019). https:\/\/doi.org\/10.1109\/ACCESS.2019.2901411","journal-title":"IEEE Access."},{"key":"2458_CR30","doi-asserted-by":"publisher","first-page":"643","DOI":"10.1007\/s10586-020-03143-w","volume":"24","author":"N Kumar","year":"2021","unstructured":"N. Kumar, D.P. Vidyarthi, A novel energy-efficient scheduling model for multi-core systems. Clust. Comput. 24, 643\u2013666 (2021). https:\/\/doi.org\/10.1007\/s10586-020-03143-w","journal-title":"Clust. Comput."},{"issue":"1","key":"2458_CR31","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/TVLSI.2018.2874572","volume":"27","author":"S Lerner","year":"2019","unstructured":"S. Lerner, B. Taskin, Slew merging region propagation for bounded slew and skew clock tree synthesis. Trans. Very Large Scale Integr. (VLSI) Syst. 27(1), 1\u201310 (2019). https:\/\/doi.org\/10.1109\/TVLSI.2018.2874572","journal-title":"Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"7","key":"2458_CR32","doi-asserted-by":"publisher","first-page":"2721","DOI":"10.1109\/TCSI.2022.3168082","volume":"69","author":"J Li","year":"2022","unstructured":"J. Li, L. Xiao, L. Li, H. Li, H. Liu, C. Wang, A low-cost error-tolerant flip-flop against SET and SEU for dependable designs. Trans. Circ. Syst. I. 69(7), 2721\u20132729 (2022). https:\/\/doi.org\/10.1109\/TCSI.2022.3168082","journal-title":"Trans. Circ. Syst. I."},{"key":"2458_CR33","unstructured":"Linear Technologies, Package Thermal Resistance Table, https:\/\/www.cloudynights.com\/ubbthreads\/attachments\/6565034-_Linear_Technology_Thermal_Resistance_Table.pdf"},{"key":"2458_CR34","unstructured":"V. Melikyan, M. Martirosyan, A. Melikyan, G. Piliposyan, 14 nm educational design kit: capabilities deployment and future, in Small Systems Simulation Symposium, (2018)"},{"issue":"11","key":"2458_CR35","doi-asserted-by":"publisher","first-page":"3733","DOI":"10.1002\/cta.3124","volume":"49","author":"AK Mishra","year":"2021","unstructured":"A.K. Mishra, D. Vaithiyanathan, U. Chopra, Design and analysis of ultra-low power 18T adaptive data track flip-flop for high-speed application. Int. J. Circuit Theory Appl. 49(11), 3733\u20133747 (2021). https:\/\/doi.org\/10.1002\/cta.3124","journal-title":"Int. J. Circuit Theory Appl."},{"issue":"11","key":"2458_CR36","doi-asserted-by":"publisher","first-page":"1441","DOI":"10.1109\/JSSC.2002.803941","volume":"37","author":"KJ Nowka","year":"2002","unstructured":"K.J. Nowka, G.D. Carpenter, E.W. MacDonald, H.C. Ngo, B.C. Brock, K.I. Ishii, T.Y. Nguyen, J.L. Burns, A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling. J. Solid-State Circuits 37(11), 1441\u20131447 (2002). https:\/\/doi.org\/10.1109\/JSSC.2002.803941","journal-title":"J. Solid-State Circuits"},{"key":"2458_CR37","doi-asserted-by":"publisher","unstructured":"J.M. Rabaey, Low Power Design Essentials (2009). https:\/\/doi.org\/10.1007\/978-0-387-71713-5","DOI":"10.1007\/978-0-387-71713-5"},{"key":"2458_CR38","unstructured":"J.M. Rabaey, Digital integrated circuits: a design perspective, Chapter 7, in Designing Sequential Logic Circuits (2002), pp. 296\u2013339"},{"key":"2458_CR39","unstructured":"J.M. Rabaey, Digital integrated circuits: a design perspective, Chapter 10, in Timing Issues in Digital Circuits (2002), pp. 449\u2013506"},{"issue":"3","key":"2458_CR40","doi-asserted-by":"publisher","first-page":"924","DOI":"10.1109\/JSSC.2017.2780219","volume":"53","author":"FU Rahman","year":"2018","unstructured":"F.U. Rahman, V. Sathe, Quasi-resonant clocking: continuous voltage-frequency scalable resonant clocking system for dynamic voltage-frequency scaling systems. J.Solid-State Circuits. 53(3), 924\u2013935 (2018). https:\/\/doi.org\/10.1109\/JSSC.2017.2780219","journal-title":"J.Solid-State Circuits."},{"issue":"6","key":"2458_CR41","first-page":"1729","volume":"120","author":"N Sabu","year":"2018","unstructured":"N. Sabu, K. Batri, Review of low power design techniques for flip-flops. J. Pure Appl. Math. 120(6), 1729\u20131749 (2018)","journal-title":"J. Pure Appl. Math."},{"key":"2458_CR42","doi-asserted-by":"publisher","unstructured":"V. Sathe, Quasi-resonant clocking: a run-time control approach for true voltage-frequency-scalability, in 2014 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED), (2014), pp. 87\u201392 https:\/\/doi.org\/10.1145\/2627369.2627627","DOI":"10.1145\/2627369.2627627"},{"key":"2458_CR43","doi-asserted-by":"publisher","unstructured":"G. Shin, E. Lee, J. Lee, Y. Lee, Y. Lee, A static contention-free differential flip-flop in 28nm for low-voltage, low-power applications, in 2020 IEEE Custom Integrated Circuits Conference (CICC), (2020), pp. 1\u20134 https:\/\/doi.org\/10.1109\/CICC48029.2020.9075922","DOI":"10.1109\/CICC48029.2020.9075922"},{"issue":"8","key":"2458_CR44","doi-asserted-by":"publisher","first-page":"2963","DOI":"10.1109\/TCSI.2019.2913009","volume":"66","author":"B Song","year":"2019","unstructured":"B. Song, S. Choi, S.H. Kang, S.O. Jung, Offset-cancellation sensing-circuit-based nonvolatile flip-flop operating in near-threshold voltage region. Trans. Circuits Syst. I. 66(8), 2963\u20132972 (2019). https:\/\/doi.org\/10.1109\/TCSI.2019.2913009","journal-title":"Trans. Circuits Syst. I."},{"issue":"3","key":"2458_CR45","doi-asserted-by":"publisher","first-page":"935","DOI":"10.1109\/TCSI.2017.2763423","volume":"65","author":"F Stas","year":"2018","unstructured":"F. Stas, D. Bol, A 0.4-V 0.66-fJ\/cycle retentive true-single-phase-clock 18T flip-flop in 28-nm fully-depleted SOI CMOS. Trans. Circuits Syst. I. 65(3), 935\u2013945 (2018). https:\/\/doi.org\/10.1109\/TCSI.2017.2763423","journal-title":"Trans. Circuits Syst. I."},{"key":"2458_CR46","doi-asserted-by":"publisher","unstructured":"C.N. Sze, ISPD 2010 High performance Clock Network Synthesis Contest (2010), p. 143 https:\/\/doi.org\/10.1145\/1735023.1735058","DOI":"10.1145\/1735023.1735058"},{"key":"2458_CR47","doi-asserted-by":"publisher","unstructured":"V. Tirumalashetty, H. Mahmoodi, Clock gating and negative edge triggering for energy recovery clock, in IEEE International Symposium on Circuits and Systems (ISCAS), (2007), pp. 1141\u20131144. https:\/\/doi.org\/10.1109\/ISCAS.2007.378251","DOI":"10.1109\/ISCAS.2007.378251"},{"key":"2458_CR48","doi-asserted-by":"publisher","DOI":"10.1155\/2020\/8108591","author":"L Touil","year":"2020","unstructured":"L. Touil, A. Hamdi, I. Gassoumi, A. Mtibaa, P. Agathoklis, Design of low-power structural fir filter using data-driven clock gating and multibit flip-flops. J. Electr. Comput. Eng. (2020). https:\/\/doi.org\/10.1155\/2020\/8108591","journal-title":"J. Electr. Comput. Eng."},{"key":"2458_CR49","doi-asserted-by":"publisher","unstructured":"M.Y. Tsai, P.Y. Kuo, J.F. Lin, M.H. Sheu, An ultra-low-power true single-phase clocking flip-flop with improved hold time variation using logic structure reduction scheme, in 2018 IEEE International Symposium on Circuits and Systems (ISCAS) (2018), pp. 1\u20134 https:\/\/doi.org\/10.1109\/ISCAS.2018.8350985","DOI":"10.1109\/ISCAS.2018.8350985"},{"key":"2458_CR50","doi-asserted-by":"publisher","unstructured":"D. Vaithiyanathan, A.K. Mishra, T. Bhardwaj, V.J Verma, B. Kaur, Power consumption and delay comparison of a modified TCFF with existing FF implemented using FinFET and load test circuit analysis, in 2021 IEEE Madras Section Conference (MASCON), (2021), pp. 1\u20135 https:\/\/doi.org\/10.1109\/MASCON51689.2021.9563560","DOI":"10.1109\/MASCON51689.2021.9563560"},{"issue":"5","key":"2458_CR51","doi-asserted-by":"publisher","first-page":"1022","DOI":"10.1109\/TVLSI.2021.3061921","volume":"29","author":"H You","year":"2021","unstructured":"H. You, J. Yuan, Z. Yu, S. Qiao, Low-power retentive true single-phase-clocked flip-flop with redundant-precharge-free operation. Trans. Very Large Scale Integr. (VLSI) Syst. 29(5), 1022\u20131032 (2021). https:\/\/doi.org\/10.1109\/TVLSI.2021.3061921","journal-title":"Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"2458_CR52","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2022.3165527","author":"Q Yu","year":"2022","unstructured":"Q. Yu, J. Gao, J. Wei, J. Li, K.C. Tan, T. Huang, Improving multispike learning with plastic synaptic delays. Trans. Neural Netw. Learn. Syst. (2022). https:\/\/doi.org\/10.1109\/TNNLS.2022.3165527","journal-title":"Trans. Neural Netw. Learn. Syst."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-023-02458-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-023-02458-4\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-023-02458-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,17]],"date-time":"2023-10-17T15:10:37Z","timestamp":1697555437000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-023-02458-4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,8,1]]},"references-count":52,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2023,12]]}},"alternative-id":["2458"],"URL":"https:\/\/doi.org\/10.1007\/s00034-023-02458-4","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,8,1]]},"assertion":[{"value":"16 February 2023","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"13 July 2023","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"14 July 2023","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"1 August 2023","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors have no competing interests to declare.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}]}}