{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,18]],"date-time":"2025-12-18T14:23:43Z","timestamp":1766067823142,"version":"3.37.3"},"reference-count":24,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2023,9,25]],"date-time":"2023-09-25T00:00:00Z","timestamp":1695600000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,9,25]],"date-time":"2023-09-25T00:00:00Z","timestamp":1695600000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2024,2]]},"DOI":"10.1007\/s00034-023-02512-1","type":"journal-article","created":{"date-parts":[[2023,9,25]],"date-time":"2023-09-25T19:01:36Z","timestamp":1695668496000},"page":"1192-1207","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":6,"title":["Implementation and Applications of a Ternary Threshold Logic Gate"],"prefix":"10.1007","volume":"43","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7738-9286","authenticated-orcid":false,"given":"Ahmet","family":"Unutulmaz","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cem","family":"\u00dcnsalan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2023,9,25]]},"reference":[{"issue":"5","key":"2512_CR1","doi-asserted-by":"publisher","first-page":"739","DOI":"10.1109\/JSSC.1984.1052216","volume":"19","author":"PC Balla","year":"1984","unstructured":"P.C. Balla, A. Antoniou, Low power dissipation MOS ternary logic family. IEEE J. Solid-State Circuits 19(5), 739\u2013749 (1984)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"2","key":"2512_CR2","doi-asserted-by":"publisher","first-page":"118","DOI":"10.1166\/jno.2017.1978","volume":"12","author":"NH Bastani","year":"2017","unstructured":"N.H. Bastani, M.H. Moaiyeri, K. Navi, Carbon nanotube field effect transistor switching logic for designing efficient ternary arithmetic circuits. J. Nanoelectron. Optoelectron. 12(2), 118\u2013129 (2017). https:\/\/doi.org\/10.1166\/jno.2017.1978","journal-title":"J. Nanoelectron. Optoelectron."},{"issue":"5","key":"2512_CR3","doi-asserted-by":"publisher","first-page":"1217","DOI":"10.1109\/tnn.2003.816365","volume":"14","author":"V Beiu","year":"2003","unstructured":"V. Beiu, J.M. Quintana, M.J. Avedillo, VLSI implementations of threshold logic\u2014a comprehensive survey. IEEE Trans. Neural Netw. 14(5), 1217\u20131243 (2003). https:\/\/doi.org\/10.1109\/tnn.2003.816365","journal-title":"IEEE Trans. Neural Netw."},{"key":"2512_CR4","doi-asserted-by":"publisher","unstructured":"V.S. Chang, S.H. Wang, J.H. Lu, et al., Enabling multiple-vt device scaling for CMOS technology beyond 7 nm node, in IEEE Symposium on VLSI Technology (2020), pp 1\u20132. https:\/\/doi.org\/10.1109\/vlsitechnology18217.2020.9265050","DOI":"10.1109\/vlsitechnology18217.2020.9265050"},{"key":"2512_CR5","doi-asserted-by":"publisher","first-page":"661","DOI":"10.1109\/tnano.2020.3018867","volume":"19","author":"S Gadgil","year":"2020","unstructured":"S. Gadgil, C. Vudadha, Design of CNTFET-based ternary ALU using 2:1 multiplexer based approach. IEEE Trans. Nanotechnol. 19, 661\u2013671 (2020). https:\/\/doi.org\/10.1109\/tnano.2020.3018867","journal-title":"IEEE Trans. Nanotechnol."},{"issue":"7771","key":"2512_CR6","doi-asserted-by":"publisher","first-page":"595","DOI":"10.1038\/s41586-019-1493-8","volume":"572","author":"G Hills","year":"2019","unstructured":"G. Hills, C. Lau, A. Wright et al., Modern microprocessor built from complementary carbon nanotube transistors. Nature 572(7771), 595\u2013602 (2019)","journal-title":"Nature"},{"issue":"9","key":"2512_CR7","doi-asserted-by":"publisher","first-page":"2873","DOI":"10.1109\/tvlsi.2016.2527783","volume":"24","author":"N Kulkarni","year":"2016","unstructured":"N. Kulkarni, J. Yang, J. Seo et al., Reducing power, leakage, and area of standard-cell asics using threshold logic flip-flops. IEEE Trans. Very Large Scale Integr. Syst. 24(9), 2873\u20132886 (2016). https:\/\/doi.org\/10.1109\/tvlsi.2016.2527783","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"2512_CR8","doi-asserted-by":"publisher","unstructured":"S. Leshner, K. Berezowski, X. Yao, et al, A low power, high performance threshold logic-based standard cell multiplier in 65 nm CMOS, in IEEE Computer Society Annual Symposium on VLSI (2010), pp 210\u2013215. https:\/\/doi.org\/10.1109\/isvlsi.2010.32","DOI":"10.1109\/isvlsi.2010.32"},{"issue":"2","key":"2512_CR9","doi-asserted-by":"publisher","first-page":"217","DOI":"10.1109\/tnano.2009.2036845","volume":"10","author":"S Lin","year":"2009","unstructured":"S. Lin, Y.-B. Kim, F. Lombardi, CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol. 10(2), 217\u2013225 (2009). https:\/\/doi.org\/10.1109\/tnano.2009.2036845","journal-title":"IEEE Trans. Nanotechnol."},{"issue":"8","key":"2512_CR10","doi-asserted-by":"publisher","first-page":"1734","DOI":"10.1109\/tnnls.2016.2547842","volume":"28","author":"AK Maan","year":"2016","unstructured":"A.K. Maan, D.A. Jayadevi, A.P. James, A survey of memristive threshold logic circuits. IEEE Trans. Neural Netw. Learn. Syst. 28(8), 1734\u20131746 (2016). https:\/\/doi.org\/10.1109\/tnnls.2016.2547842","journal-title":"IEEE Trans. Neural Netw. Learn. Syst."},{"key":"2512_CR11","doi-asserted-by":"publisher","first-page":"13","DOI":"10.1016\/S1874-5857(07)80004-5","volume-title":"The Many Valued and Nonmonotonic Turn in Logic, Handbook of the History of Logic","author":"G Malinowski","year":"2007","unstructured":"G. Malinowski, Many-valued logic and its philosophy, in The Many Valued and Nonmonotonic Turn in Logic, Handbook of the History of Logic, vol. 8, ed. by M.G. Dov, W. John (North-Holland, Amsterdam, 2007), pp.13\u201394"},{"issue":"6","key":"2512_CR12","doi-asserted-by":"publisher","first-page":"1911","DOI":"10.1109\/JPROC.2012.2190812","volume":"100","author":"P Mazumder","year":"2012","unstructured":"P. Mazumder, S.-M. Kang, R. Waser, Memristors: devices, models, and applications. Proc. IEEE 100(6), 1911\u20131919 (2012). https:\/\/doi.org\/10.1109\/JPROC.2012.2190812","journal-title":"Proc. IEEE"},{"issue":"8","key":"2512_CR13","doi-asserted-by":"publisher","first-page":"3041","DOI":"10.1109\/tcsi.2019.2902475","volume":"66","author":"G Papandroulidakis","year":"2019","unstructured":"G. Papandroulidakis, A. Serb, A. Khiat et al., Practical implementation of memristor-based threshold logic gates. IEEE Trans. Circuits Syst. I Regul. Pap. 66(8), 3041\u20133051 (2019). https:\/\/doi.org\/10.1109\/tcsi.2019.2902475","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"issue":"3","key":"2512_CR14","doi-asserted-by":"publisher","first-page":"368","DOI":"10.1109\/tnano.2017.2649548","volume":"16","author":"SK Sahoo","year":"2017","unstructured":"S.K. Sahoo, G. Akhilesh, R. Sahoo et al., High-performance ternary adder using CNTFET. IEEE Trans. Nanotechnol. 16(3), 368\u2013374 (2017). https:\/\/doi.org\/10.1109\/tnano.2017.2649548","journal-title":"IEEE Trans. Nanotechnol."},{"key":"2512_CR15","doi-asserted-by":"publisher","DOI":"10.1007\/0-387-48550-3","volume-title":"Routing Congestion in VLSI Circuits","author":"P Saxena","year":"2007","unstructured":"P. Saxena, R.S. Shelar, S. Sapatnekar, Routing Congestion in VLSI Circuits (Springer, New York, 2007). https:\/\/doi.org\/10.1007\/0-387-48550-3"},{"issue":"10","key":"2512_CR16","doi-asserted-by":"publisher","first-page":"4640","DOI":"10.1007\/s00034-019-01070-9","volume":"38","author":"T Sharma","year":"2019","unstructured":"T. Sharma, L. Kumre, CNTFET-based design of ternary arithmetic modules. Circuits Syst. Signal Process. 38(10), 4640\u20134666 (2019). https:\/\/doi.org\/10.1007\/s00034-019-01070-9","journal-title":"Circuits Syst. Signal Process."},{"key":"2512_CR17","doi-asserted-by":"publisher","first-page":"48371","DOI":"10.1109\/access.2019.2909500","volume":"7","author":"N Soliman","year":"2019","unstructured":"N. Soliman, M.E. Fouda, A.G. Alhurbi et al., Ternary functions design using memristive threshold logic. IEEE Access 7, 48371\u201348381 (2019). https:\/\/doi.org\/10.1109\/access.2019.2909500","journal-title":"IEEE Access"},{"key":"2512_CR18","doi-asserted-by":"publisher","first-page":"74","DOI":"10.1016\/j.mejo.2017.12.008","volume":"72","author":"NS Soliman","year":"2018","unstructured":"N.S. Soliman, M.E. Fouda, A.G. Radwan, Memristor-CNTFET based ternary logic gates. Microelectron. J. 72, 74\u201385 (2018). https:\/\/doi.org\/10.1016\/j.mejo.2017.12.008","journal-title":"Microelectron. J."},{"issue":"8","key":"2512_CR19","doi-asserted-by":"publisher","first-page":"753","DOI":"10.1109\/tcsii.2016.2531100","volume":"63","author":"B Srinivasu","year":"2016","unstructured":"B. Srinivasu, K. Sridharan, Low-complexity multiternary digit multiplier design in CNTFET technology. IEEE Trans. Circuits Syst. II Express Br. 63(8), 753\u2013757 (2016). https:\/\/doi.org\/10.1109\/tcsii.2016.2531100","journal-title":"IEEE Trans. Circuits Syst. II Express Br."},{"key":"2512_CR20","doi-asserted-by":"publisher","unstructured":"A. Unutulmaz, C. \u00dcnsalan, Implementation and applications of a ternary threshold logic gate (2022). https:\/\/doi.org\/10.48550\/arXiv.2211.12176","DOI":"10.48550\/arXiv.2211.12176"},{"key":"2512_CR21","doi-asserted-by":"publisher","unstructured":"S. Vrudhula, N. Kulkami, J. Yang, Design of threshold logic gates using emerging devices, in IEEE International Symposium on Circuits and Systems (2015), pp 373\u2013376. https:\/\/doi.org\/10.1109\/iscas.2015.7168648","DOI":"10.1109\/iscas.2015.7168648"},{"issue":"1","key":"2512_CR22","doi-asserted-by":"publisher","first-page":"264","DOI":"10.1109\/tcsi.2020.3027693","volume":"68","author":"X-Y Wang","year":"2021","unstructured":"X.-Y. Wang, P.-F. Zhou, J.K. Eshraghian et al., High-density memristor-cmos ternary logic family. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1), 264\u2013274 (2021). https:\/\/doi.org\/10.1109\/tcsi.2020.3027693","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"2512_CR23","doi-asserted-by":"crossref","unstructured":"J. Yang, N. Kulkarni, S. Yu, et al., Integration of threshold logic gates with RRAM devices for energy efficient and robust operation, in IEEE\/ACM International Symposium on Nanoscale Architectures (2014), pp 39\u201344","DOI":"10.1109\/NANOARCH.2014.6880500"},{"issue":"11","key":"2512_CR24","doi-asserted-by":"publisher","first-page":"2816","DOI":"10.1109\/ted.2006.884077","volume":"53","author":"W Zhao","year":"2006","unstructured":"W. Zhao, Y. Cao, New generation of predictive technology model for sub-45 nm early design exploration. IEEE Trans. Electron. Dev. 53(11), 2816\u20132823 (2006). https:\/\/doi.org\/10.1109\/ted.2006.884077","journal-title":"IEEE Trans. Electron. Dev."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-023-02512-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-023-02512-1\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-023-02512-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,25]],"date-time":"2024-01-25T21:03:06Z","timestamp":1706216586000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-023-02512-1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,9,25]]},"references-count":24,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2024,2]]}},"alternative-id":["2512"],"URL":"https:\/\/doi.org\/10.1007\/s00034-023-02512-1","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2023,9,25]]},"assertion":[{"value":"23 November 2022","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"7 September 2023","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"8 September 2023","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"25 September 2023","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors have no conflicts of interest to declare that are relevant to the content of this article.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}]}}