{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,20]],"date-time":"2026-02-20T19:01:25Z","timestamp":1771614085494,"version":"3.50.1"},"reference-count":27,"publisher":"Springer Science and Business Media LLC","issue":"9","license":[{"start":{"date-parts":[[2024,6,9]],"date-time":"2024-06-09T00:00:00Z","timestamp":1717891200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,6,9]],"date-time":"2024-06-09T00:00:00Z","timestamp":1717891200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2024,9]]},"DOI":"10.1007\/s00034-024-02724-z","type":"journal-article","created":{"date-parts":[[2024,6,9]],"date-time":"2024-06-09T19:01:25Z","timestamp":1717959685000},"page":"5897-5911","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Design of an Area Efficient and High-Performance Adder with a Novel Sum Generator"],"prefix":"10.1007","volume":"43","author":[{"given":"Niyas Ahamed","family":"Allavudeen","sequence":"first","affiliation":[]},{"given":"Madheswaran","family":"Muthusamy","sequence":"additional","affiliation":[]},{"given":"Anand","family":"Karuppannan","sequence":"additional","affiliation":[]},{"given":"Nazrin Salma","family":"Sheriff","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2024,6,9]]},"reference":[{"key":"2724_CR1","doi-asserted-by":"publisher","first-page":"15","DOI":"10.1016\/j.micpro.2018.03.003","volume":"59","author":"F Ahmad","year":"2018","unstructured":"F. Ahmad, N. Kandasamy, S. Reddy, R. Babu, N. Telagam, S. Ultapalli, Performance evaluation of 4-Bit MAC using hybrid GDI and transmission gate based adder multiplier circuits in 180 and 90 nm technology. Microprocess. Microsyst. 59, 15\u201328 (2018). https:\/\/doi.org\/10.1016\/j.micpro.2018.03.003","journal-title":"Microprocess. Microsyst."},{"issue":"2","key":"2724_CR2","doi-asserted-by":"publisher","first-page":"1221","DOI":"10.1049\/iet-cds.2019.0084","volume":"13","author":"AAE Zarandi","year":"2019","unstructured":"A.A.E. Zarandi, F. Jafarzadehpour, A.S. Molahosseini, L. Sousa, New Energy-efficient hybrid wide-operand adder architecture. IET Circuits Devices Syst. 13(2), 1221\u20131231 (2019). https:\/\/doi.org\/10.1049\/iet-cds.2019.0084","journal-title":"IET Circuits Devices Syst."},{"key":"2724_CR3","doi-asserted-by":"publisher","unstructured":"N. Kandasamy, N.M. Kumar, N. Telagam, F. Ahmad, G. Mishra, , November. Analysis of self checking and self resetting logic in CLA and CSA circuits using gate diffusion input technique. In\u00a02019 International Conference on Smart Systems and Inventive Technology (ICSSIT) p 1\u20136 IEEE (2019). https:\/\/doi.org\/10.1109\/ICSSIT46314.2019.8987817","DOI":"10.1109\/ICSSIT46314.2019.8987817"},{"issue":"1","key":"2724_CR4","doi-asserted-by":"publisher","first-page":"126","DOI":"10.1016\/j.mejo.2008.08.020","volume":"40","author":"K Navi","year":"2009","unstructured":"K. Navi, M.H. Moaiyeri, R.F. Mirzaee, O. Hashemipour, B.M. Nezhad, Two new low power full adder based on majority-NOT gates. Microelectron. J. 40(1), 126\u2013130 (2009). https:\/\/doi.org\/10.1016\/j.mejo.2008.08.020","journal-title":"Microelectron. J."},{"issue":"4","key":"2724_CR5","doi-asserted-by":"publisher","first-page":"641","DOI":"10.1142\/S0218126611007517","volume":"20","author":"RF Mirzaee","year":"2011","unstructured":"R.F. Mirzaee, M.H. Moaiyeri, H. Khorsand, K. Navi, A new robust and hybrid high performance full adder cell. J. Circuit. Syst. Comput. 20(4), 641\u2013655 (2011). https:\/\/doi.org\/10.1142\/S0218126611007517","journal-title":"J. Circuit. Syst. Comput."},{"issue":"4","key":"2724_CR6","first-page":"1923","volume":"20","author":"G Guna","year":"2019","unstructured":"G. Guna, D. Prabhakaran, M. Thirumarimurugan, Active disturbance rejection control (ADRC) for a pilot scale reverse osmosis system. J. Environ. Prot. Ecol. 20(4), 1923\u20131934 (2019)","journal-title":"J. Environ. Prot. Ecol."},{"issue":"6","key":"2724_CR7","doi-asserted-by":"publisher","first-page":"754","DOI":"10.1109\/TVLSI.2005.848819","volume":"13","author":"VG Oklobdzija","year":"2005","unstructured":"V.G. Oklobdzija, B.R. Zeydel, H.Q. Dao, S. Mathew, R. Krishnamurthy, Comparison of high-performance VLSI adders in the energy-delay space. IEEE Trans. very large scale integr. VLSI Syst. 13(6), 754\u2013758 (2005). https:\/\/doi.org\/10.1109\/TVLSI.2005.848819","journal-title":"IEEE Trans. very large scale integr. VLSI Syst."},{"issue":"10\u201311","key":"2724_CR8","doi-asserted-by":"publisher","first-page":"2923","DOI":"10.2166\/wst.2021.302","volume":"84","author":"G Guna","year":"2021","unstructured":"G. Guna, D. Prabhakaran, M. Thirumarimurugan, Design, implementation, control and optimization of single stage pilot scale reverse osmosis process. Water Sci. Technol. 84(10\u201311), 2923\u20132942 (2021). https:\/\/doi.org\/10.2166\/wst.2021.302","journal-title":"Water Sci. Technol."},{"issue":"1","key":"2724_CR9","doi-asserted-by":"publisher","first-page":"336","DOI":"10.1109\/TCSI.2007.913610","volume":"55","author":"Y He","year":"2008","unstructured":"Y. He, C.H. Chang, A power-delay efficient hybrid carry look ahead\/ carry-select based redundant binary to two\u2019s complement converter. IEEE Trans. Circuit. Syst. 55(1), 336\u2013346 (2008). https:\/\/doi.org\/10.1109\/TCSI.2007.913610","journal-title":"IEEE Trans. Circuit. Syst."},{"issue":"2","key":"2724_CR10","doi-asserted-by":"publisher","first-page":"237","DOI":"10.1109\/JPROC.2009.2035453","volume":"98","author":"D Markovic","year":"2010","unstructured":"D. Markovic, C.C. Wang, L.P. Alarcon, T.T. Liu, J.M. Rabaey, Ultra Low-power design in near-threshold region. Proceed. IEEE 98(2), 237\u2013252 (2010). https:\/\/doi.org\/10.1109\/JPROC.2009.2035453","journal-title":"Proceed. IEEE"},{"issue":"2","key":"2724_CR11","doi-asserted-by":"publisher","first-page":"371","DOI":"10.1109\/TVLSI.2010.2101621","volume":"20","author":"B Ramkumar","year":"2012","unstructured":"B. Ramkumar, H.M. Kittur, Low-power and area-efficient carry select adder. IEEE Trans. Very Large Scale Integr. VLSI Syst. 20(2), 371\u2013375 (2012). https:\/\/doi.org\/10.1109\/TVLSI.2010.2101621","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"key":"2724_CR12","first-page":"3","volume":"591","author":"A Weinberger","year":"1958","unstructured":"A. Weinberger, J.L. Smith, A logic for high speed addition. Natl. Bur. Stand. Circ. 591, 3\u201312 (1958)","journal-title":"Natl. Bur. Stand. Circ."},{"key":"2724_CR13","unstructured":"J. Levy, J. Nyathi, A High Performance, low area overhead carry lookahead adder. proceedings of the international conference on embedded systems and applications, ESA '04 & Proceedings of the International Conference on VLSI, VLSI '04, June 21\u201324 (2004)."},{"issue":"2","key":"2724_CR14","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/TVLSI.2015.2405133","volume":"24","author":"M Bahadori","year":"2015","unstructured":"M. Bahadori, M. Kamal, A. Afzali-Kusha, M. Pedram, High-speed and energy-efficient carry skip adder operating under a wide range of supply voltage levels. IEEE Trans. Very Large Scale Integr. VLSI Syst. 24(2), 1\u201313 (2015). https:\/\/doi.org\/10.1109\/TVLSI.2015.2405133","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"issue":"1129","key":"2724_CR15","doi-asserted-by":"publisher","first-page":"1","DOI":"10.3390\/electronics8101129","volume":"8","author":"H You","year":"2019","unstructured":"H. You, J. Yuan, W. Tang, S. Qiao, An energy and area efficient carry select adder with dual carry adder cell. Electronics 8(1129), 1\u201310 (2019). https:\/\/doi.org\/10.3390\/electronics8101129","journal-title":"Electronics"},{"key":"2724_CR16","doi-asserted-by":"publisher","unstructured":"M. Hasan, M.J. Hossain, U.K. Saha, M.S. Tarif, (2018) Overview and Comparative Performance Analysis of Various Full Adder Cells in 90 nm Technology. 2018 4th International Conference on Computing Communication and Automation (ICCCA) https:\/\/doi.org\/10.1109\/CCAA.2018.8777684","DOI":"10.1109\/CCAA.2018.8777684"},{"issue":"02","key":"2724_CR17","doi-asserted-by":"publisher","first-page":"433","DOI":"10.5829\/IJE.2021.34.02B.15","volume":"34","author":"M Valinataj","year":"2021","unstructured":"M. Valinataj, An enhanced self-checking carry select adder utilizing the concept of self-checking full adder. Int. J. Eng. 34(02), 433\u2013442 (2021). https:\/\/doi.org\/10.5829\/IJE.2021.34.02B.15","journal-title":"Int. J. Eng."},{"issue":"2","key":"2724_CR18","doi-asserted-by":"publisher","first-page":"1221","DOI":"10.1049\/iet-cds.2019.0084","volume":"13","author":"F Jafarzadehpour","year":"2019","unstructured":"F. Jafarzadehpour, A.S. Molahosseini, A.A. Emrani Zarandi, L. Sousa, New energy-efficient hybrid wide-operand adder architecture. IET Circuit. Devices Syst. 13(2), 1221\u20131231 (2019). https:\/\/doi.org\/10.1049\/iet-cds.2019.0084","journal-title":"IET Circuit. Devices Syst."},{"issue":"3","key":"2724_CR19","doi-asserted-by":"publisher","first-page":"409","DOI":"10.1007\/s11265-017-1249-3","volume":"90","author":"X Cui","year":"2018","unstructured":"X. Cui, W. Liu, S. Wang, E.E. Swartzlander, F. Lombardi, Design of high-speed wide-word hybrid parallel-prefix\/carry-select and skip adders. J. Signal Process. Syst. 90(3), 409\u2013419 (2018). https:\/\/doi.org\/10.1007\/s11265-017-1249-3","journal-title":"J. Signal Process. Syst."},{"issue":"12","key":"2724_CR20","doi-asserted-by":"publisher","first-page":"2050186","DOI":"10.1142\/S0218126620501868","volume":"29","author":"SK Singhal","year":"2020","unstructured":"S.K. Singhal, B.K. Mohanty, S.K. Patel, G. Saxena, Efficient diminished-1 modulo (2 n+ 1) adder using parallel prefix adder. J. Circuit. Syst. Comput. 29(12), 2050186 (2020). https:\/\/doi.org\/10.1142\/S0218126620501868","journal-title":"J. Circuit. Syst. Comput."},{"key":"2724_CR21","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1016\/j.micpro.2019.102958","volume":"73","author":"B Sakthivel","year":"2020","unstructured":"B. Sakthivel, A. Padma, Area and delay efficient accuracy reconfigurable adder design. Microprocess. Microsyst. 73, 1\u201312 (2020). https:\/\/doi.org\/10.1016\/j.micpro.2019.102958","journal-title":"Microprocess. Microsyst."},{"key":"2724_CR22","doi-asserted-by":"publisher","unstructured":"K.B. Lakshmi, S. Tejaswi, S.C.Vamsi, B. Jeevanarani, A novel area efficient parity generator and checker circuits design using QCA. In 2020 International Conference on Inventive Computation Technologies (ICICT) p 1108\u20131113 IEEE (2020). https:\/\/doi.org\/10.1109\/ICICT48043.2020.9112545","DOI":"10.1109\/ICICT48043.2020.9112545"},{"key":"2724_CR23","unstructured":"D. Arulraj, A.Rajaram, Efficient implementation of digital filters using a booth multipliers with low power and bandstop responses."},{"issue":"1","key":"2724_CR24","doi-asserted-by":"publisher","first-page":"1","DOI":"10.12785\/ijcds\/140110","volume":"14","author":"J Garg","year":"2023","unstructured":"J. Garg, S. Wariya, Design of low power arithmetic logic unit using SHE assisted STT\/MTJ. Int. J. Comput. Digit. Syst. 14(1), 1\u20131 (2023). https:\/\/doi.org\/10.12785\/ijcds\/140110","journal-title":"Int. J. Comput. Digit. Syst."},{"issue":"1","key":"2724_CR25","doi-asserted-by":"publisher","first-page":"105","DOI":"10.1109\/TNANO.2011.2158006","volume":"11","author":"V Pudi","year":"2012","unstructured":"V. Pudi, K. Sridharan, Low complexity design of ripple carry and brent-kung adders in QCA. IEEE Trans. Nanotechnol. 11(1), 105\u2013109 (2012). https:\/\/doi.org\/10.1109\/TNANO.2011.2158006","journal-title":"IEEE Trans. Nanotechnol."},{"issue":"11","key":"2724_CR26","doi-asserted-by":"publisher","first-page":"2196","DOI":"10.1109\/TC.2012.111","volume":"62","author":"I Ouretas","year":"2013","unstructured":"I. Ouretas, C. Basetas, V. Paliouras, Low-power logarithmic number system addition\/subtraction and their impact in their digital filters. IEEE Trans. Comput. 62(11), 2196\u20132209 (2013). https:\/\/doi.org\/10.1109\/TC.2012.111","journal-title":"IEEE Trans. Comput."},{"key":"2724_CR27","doi-asserted-by":"publisher","first-page":"5513","DOI":"10.1007\/s12652-020-02062-3","volume":"12","author":"R Mirzaee","year":"2011","unstructured":"R. Mirzaee, G. Ragunath, Low power area optimized and high speed carry select adder using optimized half sum and carry generation unit for FIR filter. J. Ambient. Intell. Humaniz. Comput. 12, 5513\u20135524 (2011). https:\/\/doi.org\/10.1007\/s12652-020-02062-3","journal-title":"J. Ambient. Intell. Humaniz. Comput."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-024-02724-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-024-02724-z\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-024-02724-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,14]],"date-time":"2024-08-14T12:08:22Z","timestamp":1723637302000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-024-02724-z"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,9]]},"references-count":27,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2024,9]]}},"alternative-id":["2724"],"URL":"https:\/\/doi.org\/10.1007\/s00034-024-02724-z","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,6,9]]},"assertion":[{"value":"2 August 2023","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"6 May 2024","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"6 May 2024","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"9 June 2024","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"Conflict of Interest is not applicable in this work.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}},{"value":"No participation of humans takes place in this implementation process.","order":3,"name":"Ethics","group":{"name":"EthicsHeading","label":"Ethics Approval and Consent to Participate"}},{"value":"No violation of Human and Animal Rights is involved.","order":4,"name":"Ethics","group":{"name":"EthicsHeading","label":"Human and Animal Rights"}}]}}