{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T15:01:12Z","timestamp":1775055672279,"version":"3.50.1"},"reference-count":50,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2024,12,13]],"date-time":"2024-12-13T00:00:00Z","timestamp":1734048000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,12,13]],"date-time":"2024-12-13T00:00:00Z","timestamp":1734048000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2025,4]]},"DOI":"10.1007\/s00034-024-02835-7","type":"journal-article","created":{"date-parts":[[2024,12,13]],"date-time":"2024-12-13T20:47:20Z","timestamp":1734122840000},"page":"2473-2502","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Design and Implementation of a 16-bit Multi-mode 4-Channel Time-Interleaved Delta-Sigma Modulator with SNDR\u2009&gt;\u2009106\u00a0dB and DCE Compensation Based on FPGA"],"prefix":"10.1007","volume":"44","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2335-8051","authenticated-orcid":false,"given":"Abolfazl","family":"Roshanpanah","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1646-7054","authenticated-orcid":false,"given":"Pooya","family":"Torkzadeh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7465-6983","authenticated-orcid":false,"given":"Khosrow","family":"Hajsadeghi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2884-7062","authenticated-orcid":false,"given":"Massoud","family":"Dousti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2024,12,13]]},"reference":[{"issue":"5","key":"2835_CR1","doi-asserted-by":"publisher","first-page":"871","DOI":"10.1109\/TVLSI.2021.3056316","volume":"29","author":"A Mahmoudi","year":"2021","unstructured":"A. Mahmoudi, P. Torkzadeh, M. Dousti, A 6-Bit 15-GS\/s SAR ADC with smart speculative two-tap embedded DFE in 130-nm CMOS for wireline receiver applications. IEEE Trans. Very Large Scale Integr. VLSI Syst. 29(5), 871\u2013882 (2021). https:\/\/doi.org\/10.1109\/TVLSI.2021.3056316","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"issue":"4","key":"2835_CR2","doi-asserted-by":"publisher","first-page":"626","DOI":"10.1109\/JPROC.2009.2013012","volume":"97","author":"J Mitola","year":"2009","unstructured":"J. Mitola, Cognitive radio architecture evolution. Proc. IEEE 97(4), 626\u2013641 (2009)","journal-title":"Proc. IEEE"},{"issue":"5","key":"2835_CR3","doi-asserted-by":"publisher","first-page":"26","DOI":"10.1109\/35.393001","volume":"33","author":"J Mitola","year":"1995","unstructured":"J. Mitola, The software radio architecture. IEEE Commun. Mag. 33(5), 26\u201338 (1995)","journal-title":"IEEE Commun. Mag."},{"key":"2835_CR4","volume-title":"Understanding Delta-Sigma Data Converters","author":"S Pavan","year":"2017","unstructured":"S. Pavan, R. Schreier, G.C. Temes, Understanding Delta-Sigma Data Converters (Wiley, New York, 2017)"},{"issue":"5","key":"2835_CR5","doi-asserted-by":"publisher","first-page":"2125","DOI":"10.1007\/s00034-016-0406-4","volume":"36","author":"B Khazaeili","year":"2017","unstructured":"B. Khazaeili, M. Yavari, A simple structure for MASH sigma delta modulators with highly reduced in-band quantization noise. Circuits Syst. Signal Process. 36(5), 2125\u20132153 (2017). https:\/\/doi.org\/10.1007\/s00034-016-0406-4","journal-title":"Circuits Syst. Signal Process."},{"issue":"1","key":"2835_CR6","doi-asserted-by":"publisher","first-page":"34","DOI":"10.1016\/j.vlsi.2008.07.004","volume":"42","author":"A Silva","year":"2009","unstructured":"A. Silva, J. Guilherme, N. Horta, Reconfigurable multi-mode sigma\u2013delta modulator for 4G mobile terminals. Integration 42(1), 34\u201346 (2009). https:\/\/doi.org\/10.1016\/j.vlsi.2008.07.004","journal-title":"Integration"},{"issue":"3","key":"2835_CR7","doi-asserted-by":"publisher","first-page":"190","DOI":"10.1109\/TCSII.2009.2015365","volume":"56","author":"PTMV Zeijl","year":"2009","unstructured":"P.T.M.V. Zeijl, M. Collados, On the attenuation of DAC aliases through multiphase clocking. IEEE Trans. Circuits Syst. II Express Briefs 56(3), 190\u2013194 (2009). https:\/\/doi.org\/10.1109\/TCSII.2009.2015365","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"2835_CR8","doi-asserted-by":"crossref","unstructured":"M.S. Alavi, G. Voicu, R.B. Staszewski, L.C.N. de Vreede, J.R. Long, A 2\u00d7 13-bit all-digital i\/q rf-dac in 65-nm cmos. 2013: IEEE, pp. 167\u2013170, 1467360627","DOI":"10.1109\/RFIC.2013.6569551"},{"issue":"8","key":"2835_CR9","doi-asserted-by":"publisher","first-page":"1710","DOI":"10.1109\/JSSC.2007.900255","volume":"42","author":"A Jerng","year":"2007","unstructured":"A. Jerng, C.G. Sodini, A wideband \u0394\u03a3 digital-RF modulator for high data rate transmitters. IEEE J. Solid-State Circuits 42(8), 1710\u20131722 (2007)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"9","key":"2835_CR10","doi-asserted-by":"publisher","first-page":"1462","DOI":"10.1109\/JSSC.2004.829377","volume":"39","author":"S Luschas","year":"2004","unstructured":"S. Luschas, R. Schreier, H.-S. Lee, Radio frequency digital-to-analog converter. IEEE J. Solid-State Circuits 39(9), 1462\u20131467 (2004)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"2835_CR11","doi-asserted-by":"publisher","first-page":"6","DOI":"10.1016\/j.aeue.2018.03.005","volume":"89","author":"A Mahmoudi","year":"2018","unstructured":"A. Mahmoudi, P. Torkzadeh, M. Dousti, A 5-bit 1.8 GS\/s ADC-based receiver with two-tap low-overhead embedded DFE in 130-nm CMOS. AEU Int. J. Electron. Commun. 89, 6\u201314 (2018). https:\/\/doi.org\/10.1016\/j.aeue.2018.03.005","journal-title":"AEU Int. J. Electron. Commun."},{"key":"2835_CR12","doi-asserted-by":"crossref","unstructured":"P.E. Paro Filho, M. Ingels, P. Wambacq, J. Craninckx, 9.3 A transmitter with 10b 128MS\/S incremental-charge-based DAC achieving\u2014155dBc\/Hz out-of-band noise, 2015: IEEE, p. 1\u20133","DOI":"10.1109\/ISSCC.2015.7062977"},{"issue":"1","key":"2835_CR13","doi-asserted-by":"publisher","first-page":"296","DOI":"10.1007\/s00034-020-01470-2","volume":"40","author":"D Li","year":"2021","unstructured":"D. Li, C. Fei, Q. Zhang, Analysis and design of low-complexity stochastic DEM encoder for reduced-distortion multi-bit DAC in sigma-delta modulators. Circuits Syst. Signal Process. 40(1), 296\u2013310 (2021). https:\/\/doi.org\/10.1007\/s00034-020-01470-2","journal-title":"Circuits Syst. Signal Process."},{"key":"2835_CR14","doi-asserted-by":"crossref","unstructured":"A. Pozsgay, T. Zounes, R. Hossain, M. Boulemnakher, V. Knopik, S. Grange, A fully digital 65nm CMOS transmitter for the 2.4-to-2.7 GHz WiFi\/WiMAX bands using 5.4 GHz \u0394\u03a3 RF DACs, 2008: IEEE, p. 360\u2013619 1424420105","DOI":"10.1109\/ISSCC.2008.4523206"},{"issue":"10","key":"2835_CR15","doi-asserted-by":"publisher","first-page":"2306","DOI":"10.1109\/JSSC.2015.2460375","volume":"50","author":"A Bhide","year":"2015","unstructured":"A. Bhide, A. Alvandpour, An 11 GS\/s 1.1 GHz Bandwidth Interleaved \u0394\u03a3 DAC for 60 GHz Radio in 65 nm CMOS. IEEE J. Solid-State Circuits 50(10), 2306\u20132318 (2015). https:\/\/doi.org\/10.1109\/JSSC.2015.2460375","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"11","key":"2835_CR16","doi-asserted-by":"publisher","first-page":"4929","DOI":"10.1007\/s00034-018-0791-y","volume":"37","author":"C Schmidt","year":"2018","unstructured":"C. Schmidt, C. Kottke, V.H. Tanzil, R. Freund, V. Jungnickel, F. Gerfers, Digital-to-analog converters using frequency interleaving: mathematical framework and experimental verification. Circuits Syst. Signal Process. 37(11), 4929\u20134954 (2018). https:\/\/doi.org\/10.1007\/s00034-018-0791-y","journal-title":"Circuits Syst. Signal Process."},{"issue":"1","key":"2835_CR17","doi-asserted-by":"publisher","first-page":"64","DOI":"10.1109\/MMM.2011.2173983","volume":"13","author":"S Balasubramanian","year":"2012","unstructured":"S. Balasubramanian et al., Ultimate transmission. IEEE Microw. Mag. 13(1), 64\u201382 (2012)","journal-title":"IEEE Microw. Mag."},{"issue":"12\u201313","key":"2835_CR18","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/NORCHP.2012.6403097","volume":"2012","author":"S Balasubramanian","year":"2012","unstructured":"S. Balasubramanian, W. Khalil, Architectural trends in GHz speed DACs. NORCHIP 2012(12\u201313), 1\u20134 (2012). https:\/\/doi.org\/10.1109\/NORCHP.2012.6403097","journal-title":"NORCHIP"},{"key":"2835_CR19","doi-asserted-by":"publisher","unstructured":"E. Bechthum, G. Radulov, J. Briaire, G. Geelen, A.v. Roermund, 9.6 A 5.3GHz 16b 1.75GS\/S wideband RF Mixing-DAC achieving IMD<-82dBc up to 1.9GHz, in 2015 IEEE International Solid-State Circuits Conference\u2014(ISSCC) Digest of Technical Papers, 22\u201326 Feb. 2015, pp. 1\u20133. https:\/\/doi.org\/10.1109\/ISSCC.2015.7062980","DOI":"10.1109\/ISSCC.2015.7062980"},{"key":"2835_CR20","doi-asserted-by":"publisher","unstructured":"E. Bechthum, G. Radulov, J. Briaire, G. Geelen, A.v. Roermund, A novel timing-error based approach for high speed highly linear mixing-DAC architectures, in 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, VIC, Australia, 1\u20135 June 2014: IEEE, pp. 942\u2013945. https:\/\/doi.org\/10.1109\/ISCAS.2014.6865292","DOI":"10.1109\/ISCAS.2014.6865292"},{"key":"2835_CR21","doi-asserted-by":"publisher","unstructured":"E. Bechthum, G. Radulov, J. Briaire, G. Geelen, A.v. Roermund, Systematic analysis of the impact of mixing locality on Mixing-DAC linearity for multicarrier GSM, in 2012 IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, Korea (South), 20\u201323 May 2012: IEEE, pp. 241\u2013244. https:\/\/doi.org\/10.1109\/ISCAS.2012.6271784","DOI":"10.1109\/ISCAS.2012.6271784"},{"key":"2835_CR22","doi-asserted-by":"publisher","unstructured":"B. Razavi, The future of radios, in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24\u201327 May 2015: IEEE, p. 1\u20138 1479983918, https:\/\/doi.org\/10.1109\/ISCAS.2015.7168556","DOI":"10.1109\/ISCAS.2015.7168556"},{"key":"2835_CR23","doi-asserted-by":"publisher","first-page":"128","DOI":"10.1016\/j.vlsi.2019.02.005","volume":"66","author":"MR Sadeghifar","year":"2019","unstructured":"M.R. Sadeghifar, H. Bengtsson, J.J. Wikner, O. Gustafsson, Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC. Integration 66, 128\u2013134 (2019). https:\/\/doi.org\/10.1016\/j.vlsi.2019.02.005","journal-title":"Integration"},{"issue":"12","key":"2835_CR24","doi-asserted-by":"publisher","first-page":"882","DOI":"10.1109\/TCSII.2011.2172526","volume":"58","author":"S Balasubramanian","year":"2011","unstructured":"S. Balasubramanian et al., Systematic analysis of interleaved digital-to-analog converters. IEEE Trans. Circuits Syst. II Express Briefs 58(12), 882\u2013886 (2011). https:\/\/doi.org\/10.1109\/TCSII.2011.2172526","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"issue":"3","key":"2835_CR25","doi-asserted-by":"publisher","first-page":"1312","DOI":"10.1007\/s00034-022-02168-3","volume":"42","author":"S Uenohara","year":"2023","unstructured":"S. Uenohara, K. Aihara, A trainable synapse circuit using a time-domain digital-to-analog converter. Circuits Syst. Signal Process 42(3), 1312\u20131326 (2023). https:\/\/doi.org\/10.1007\/s00034-022-02168-3","journal-title":"Circuits Syst. Signal Process"},{"issue":"5","key":"2835_CR26","doi-asserted-by":"publisher","first-page":"1109","DOI":"10.1109\/JSSC.2016.2521903","volume":"51","author":"JJ McCue","year":"2016","unstructured":"J.J. McCue et al., A time-interleaved multimode delta sigma RF-DAC for direct digital-to-RF synthesis. IEEE J. Solid-State Circuits 51(5), 1109\u20131124 (2016). https:\/\/doi.org\/10.1109\/JSSC.2016.2521903","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"9","key":"2835_CR27","doi-asserted-by":"publisher","first-page":"858","DOI":"10.1109\/TCSII.2008.923426","volume":"55","author":"J Pham","year":"2008","unstructured":"J. Pham, A.C. Carusone, A time-interleaved delta sigma-DAC architecture clocked at the Nyquist rate. IEEE Trans. Circuits Syst. Express Briefs 55(9), 858\u2013862 (2008). https:\/\/doi.org\/10.1109\/TCSII.2008.923426","journal-title":"IEEE Trans. Circuits Syst. Express Briefs"},{"issue":"8","key":"2835_CR28","doi-asserted-by":"publisher","first-page":"2375","DOI":"10.1109\/JSSC.2021.3060859","volume":"56","author":"D Jiang","year":"2021","unstructured":"D. Jiang, L. Qi, S.W. Sin, F. Maloberti, R.P. Martins, A time-interleaved 2nd-order \u0394\u03a3 modulator achieving 5-MHz bandwidth and 86.1-dB SNDR using digital feed-forward extrapolation. IEEE J. Solid-State Circuits 56(8), 2375\u20132387 (2021). https:\/\/doi.org\/10.1109\/JSSC.2021.3060859","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"6","key":"2835_CR29","doi-asserted-by":"publisher","first-page":"2299","DOI":"10.1007\/s00034-017-0681-8","volume":"37","author":"V O\u2019Brien","year":"2018","unstructured":"V. O\u2019Brien, A.G. Scanlan, B. Mullane, A reduced hardware ISI and mismatch shaping DEM decoder. Circuits Syst. Signal Process 37(6), 2299\u20132317 (2018). https:\/\/doi.org\/10.1007\/s00034-017-0681-8","journal-title":"Circuits Syst. Signal Process"},{"issue":"4","key":"2835_CR30","doi-asserted-by":"publisher","first-page":"896","DOI":"10.1109\/JSSC.2014.2385752","volume":"50","author":"S Su","year":"2015","unstructured":"S. Su, T. Tsai, P.K. Sharma, M.S. Chen, 12 bit 1 GS\/s dual-rate hybrid DAC with an 8 GS\/s unrolled pipeline delta-sigma modulator achieving > 75 dB SFDR over the Nyquist band. IEEE J. Solid-State Circuits 50(4), 896\u2013907 (2015A). https:\/\/doi.org\/10.1109\/JSSC.2014.2385752","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"4","key":"2835_CR31","doi-asserted-by":"publisher","first-page":"2416","DOI":"10.1007\/s00034-022-02228-8","volume":"42","author":"A Khakpour","year":"2023","unstructured":"A. Khakpour, G. Karimian, An oversampling-based fast convergent blind technique for gain mismatch and timing skew error correction in time-interleaved ADCs. Circuits Syst. Signal Process. 42(4), 2416\u20132432 (2023). https:\/\/doi.org\/10.1007\/s00034-022-02228-8","journal-title":"Circuits Syst. Signal Process."},{"key":"2835_CR32","doi-asserted-by":"publisher","unstructured":"O. Eng Hwee, J. Kneckt, O. Alanen, Z. Chang, T. Huovinen, T. Nihtil\u00e4, IEEE 802.11ac: enhancements for very high throughput WLANs, in 2011 IEEE 22nd International Symposium on Personal, Indoor and Mobile Radio Communications, 11\u201314 Sept. 2011, p. 849\u2013853, https:\/\/doi.org\/10.1109\/PIMRC.2011.6140087 (2011)","DOI":"10.1109\/PIMRC.2011.6140087"},{"key":"2835_CR33","unstructured":"High Rate 60 GHz PHY, E.-. MAC and PALs, Dec. 2010"},{"key":"2835_CR34","unstructured":"Wireless HD Specification V1.1 Overview, W. H. S. V. Overview (2010)"},{"key":"2835_CR35","doi-asserted-by":"publisher","first-page":"19","DOI":"10.1016\/j.aeue.2018.10.008","volume":"98","author":"HA Ameen","year":"2019","unstructured":"H.A. Ameen et al., A 28 GHz four-channel phased-array transceiver in 65-nm CMOS technology for 5G applications. AEU-Int. J. Electron. Commun. 98, 19\u201328 (2019)","journal-title":"AEU-Int. J. Electron. Commun."},{"key":"2835_CR36","doi-asserted-by":"publisher","first-page":"13992","DOI":"10.1109\/ACCESS.2017.2727550","volume":"5","author":"Y Huo","year":"2017","unstructured":"Y. Huo, X. Dong, W. Xu, 5G cellular user equipment: from theory to practical hardware design. IEEE Access 5, 13992\u201314010 (2017)","journal-title":"IEEE Access"},{"issue":"8","key":"2835_CR37","doi-asserted-by":"publisher","first-page":"634","DOI":"10.1109\/82.618037","volume":"44","author":"R Khoini-Poorfard","year":"1997","unstructured":"R. Khoini-Poorfard, L.B. Lim, D.A. Johns, Time-interleaved oversampling A\/D converters: theory and practice. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process 44(8), 634\u2013645 (1997). https:\/\/doi.org\/10.1109\/82.618037","journal-title":"IEEE Trans. Circuits Syst. II Analog Digit. Signal Process"},{"issue":"5","key":"2835_CR38","doi-asserted-by":"publisher","first-page":"1207","DOI":"10.1109\/JSSC.2008.920319","volume":"43","author":"J Savoj","year":"2008","unstructured":"J. Savoj, A. Abbasfar, A. Amirkhany, M. Jeeradit, B.W. Garlepp, A 12-GS\/s phase-calibrated CMOS digital-to-analog converter for backplane communications. IEEE J. Solid-State Circuits 43(5), 1207\u20131216 (2008). https:\/\/doi.org\/10.1109\/JSSC.2008.920319","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"7","key":"2835_CR39","doi-asserted-by":"publisher","first-page":"387","DOI":"10.1109\/TCSII.2013.2258272","volume":"60","author":"A Bhide","year":"2013","unstructured":"A. Bhide, O.E. Najari, B. Mesgarzadeh, A. Alvandpour, An 8-GS\/s 200-MHz bandwidth 68-mW Delta Sigma DAC in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 60(7), 387\u2013391 (2013). https:\/\/doi.org\/10.1109\/TCSII.2013.2258272","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"2835_CR40","unstructured":"S. Joshi et al., A 12-Gb\/s transceiver in 32-nm bulk CMOS, in 2009 Symposium on VLSI Circuits, 16\u201318 June 2009 (2009), p. 52\u201353"},{"key":"2835_CR41","doi-asserted-by":"publisher","unstructured":"K. Doris, A.v. Roermund, D. Leenaerts, A general analysis on the timing jitter in D\/A converters, in 2002 IEEE International Symposium on Circuits and Systems Proceedings (Cat. No. 02CH37353), 26\u201329 May 2002, vol. 1, p. I\u2013I. https:\/\/doi.org\/10.1109\/ISCAS.2002.1009791","DOI":"10.1109\/ISCAS.2002.1009791"},{"key":"2835_CR42","doi-asserted-by":"publisher","unstructured":"J. Hinrichs, G. Miao, Jitter error spectrum for NRZ D\/A converters, in 2008 IEEE International Symposium on Circuits and Systems (ISCAS), 18\u201321 May 200 2008\/8, p. 2410\u20132413, https:\/\/doi.org\/10.1109\/ISCAS.2008.4541941","DOI":"10.1109\/ISCAS.2008.4541941"},{"issue":"1","key":"2835_CR43","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/TCSII.2009.2036545","volume":"57","author":"P Gui","year":"2010","unstructured":"P. Gui, Z. Gao, C.W. Huang, L. Xiu, The effects of flying-adder clocks on digital-to-analog converters. IEEE Trans. Circuits Syst. II Express Briefs 57(1), 1\u20135 (2010). https:\/\/doi.org\/10.1109\/TCSII.2009.2036545","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"issue":"7","key":"2835_CR44","doi-asserted-by":"publisher","first-page":"646","DOI":"10.1109\/TCSII.2015.2415691","volume":"62","author":"A Bhide","year":"2015","unstructured":"A. Bhide, A. Ojani, A. Alvandpour, Effect of clock duty-cycle error on two-channel interleaved delta sigma DACs. IEEE Trans. Circuits Syst. II Express Briefs 62(7), 646\u2013650 (2015). https:\/\/doi.org\/10.1109\/TCSII.2015.2415691","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"issue":"8","key":"2835_CR45","doi-asserted-by":"publisher","first-page":"1066","DOI":"10.1109\/4.859495","volume":"35","author":"I Fujimori","year":"2000","unstructured":"I. Fujimori, A. Nogi, T. Sugimoto, A multibit delta-sigma audio DAC with 120-dB dynamic range. IEEE J. Solid-State Circuits 35(8), 1066\u20131073 (2000). https:\/\/doi.org\/10.1109\/4.859495","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"3","key":"2835_CR46","doi-asserted-by":"publisher","first-page":"704","DOI":"10.1109\/JSSC.2014.2387946","volume":"50","author":"E Olieman","year":"2015","unstructured":"E. Olieman, A. Annema, B. Nauta, An interleaved full Nyquist high-speed DAC technique. IEEE J. Solid-State Circuits 50(3), 704\u2013713 (2015). https:\/\/doi.org\/10.1109\/JSSC.2014.2387946","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"2","key":"2835_CR47","doi-asserted-by":"publisher","first-page":"386","DOI":"10.1109\/JLT.2019.2931549","volume":"38","author":"H Li","year":"2020","unstructured":"H. Li et al., Real-time 100-GS\/s sigma-delta modulator for all-digital radio-over-fiber transmission. J. Lightw. Technol. 38(2), 386\u2013393 (2020). https:\/\/doi.org\/10.1109\/JLT.2019.2931549","journal-title":"J. Lightw. Technol."},{"issue":"12","key":"2835_CR48","doi-asserted-by":"publisher","first-page":"3517","DOI":"10.1109\/JSSC.2018.2871143","volume":"53","author":"S Su","year":"2018","unstructured":"S. Su, M.S. Chen, A 16-bit 12-GS\/s single-\/dual-rate DAC with a successive bandpass delta-sigma modulator achieving <\u221267-dBc IM3 within DC to 6-GHz tunable passbands. IEEE J. Solid-State Circuits 53(12), 3517\u20133527 (2018). https:\/\/doi.org\/10.1109\/JSSC.2018.2871143","journal-title":"IEEE J. Solid-State Circuits"},{"key":"2835_CR49","doi-asserted-by":"publisher","first-page":"153617","DOI":"10.1016\/j.aeue.2021.153617","volume":"134","author":"H Sariri","year":"2021","unstructured":"H. Sariri, P. Torkzadeh, S. Sadughi, A 7 bit, 3GHz bandwidth random-time-interleaved-hybrid DAC using a novel self-healing structure for DCE in 65nm CMOS technology. AEU Int. J. Electron. Commun. 134, 153617 (2021). https:\/\/doi.org\/10.1016\/j.aeue.2021.153617","journal-title":"AEU Int. J. Electron. Commun."},{"key":"2835_CR50","doi-asserted-by":"publisher","first-page":"107418","DOI":"10.1016\/j.compag.2022.107418","volume":"202","author":"Y Li","year":"2022","unstructured":"Y. Li, J. Wang, H. Wu, Y. Yu, H. Sun, H. Zhang, Detection of powdery mildew on strawberry leaves based on DAC-YOLOv4 model. Comput. Electron. Agric. 202, 107418 (2022). https:\/\/doi.org\/10.1016\/j.compag.2022.107418","journal-title":"Comput. Electron. Agric."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-024-02835-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-024-02835-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-024-02835-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,18]],"date-time":"2025-03-18T16:21:08Z","timestamp":1742314868000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-024-02835-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12,13]]},"references-count":50,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2025,4]]}},"alternative-id":["2835"],"URL":"https:\/\/doi.org\/10.1007\/s00034-024-02835-7","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,12,13]]},"assertion":[{"value":"25 August 2023","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"12 August 2024","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"14 August 2024","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"13 December 2024","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"All authors declare that they have no conflicts of interest.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}]}}