{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T23:35:25Z","timestamp":1780356925155,"version":"3.54.1"},"reference-count":36,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2024,11,5]],"date-time":"2024-11-05T00:00:00Z","timestamp":1730764800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,11,5]],"date-time":"2024-11-05T00:00:00Z","timestamp":1730764800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2025,3]]},"DOI":"10.1007\/s00034-024-02886-w","type":"journal-article","created":{"date-parts":[[2024,11,5]],"date-time":"2024-11-05T13:07:34Z","timestamp":1730812054000},"page":"1817-1844","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["FPGA-Specific Efficient Designs of Digit-Serial Multiplier for Galois Field GF$$(2^m)$$"],"prefix":"10.1007","volume":"44","author":[{"given":"Dibakar","family":"Pradhan","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0992-1159","authenticated-orcid":false,"given":"Pramod Kumar","family":"Meher","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bimal Kumar","family":"Meher","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2024,11,5]]},"reference":[{"issue":"6","key":"2886_CR1","doi-asserted-by":"publisher","first-page":"1734","DOI":"10.1109\/TC.2015.2456023","volume":"65","author":"EAH Abdulrahman","year":"2015","unstructured":"E.A.H. Abdulrahman, A. Reyhani-Masoleh, High-speed hybrid-double multiplication architectures using new serial-out bit-level mastrovito multipliers. IEEE Trans. Comput. 65(6), 1734\u20131747 (2015)","journal-title":"IEEE Trans. Comput."},{"key":"2886_CR2","doi-asserted-by":"crossref","unstructured":"L. Batina, N. Mentens, S.B. Ors, B. Preneel, Serial multiplier architectures over GF($$2^m$$) for elliptic curve cryptosystems. in Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No. 04CH37521), vol. 2 (2004), pp. 779\u2013782","DOI":"10.1109\/MELCON.2004.1347047"},{"issue":"4","key":"2886_CR3","doi-asserted-by":"publisher","first-page":"458","DOI":"10.1109\/49.17708","volume":"7","author":"T Beth","year":"1989","unstructured":"T. Beth, D. Gollmann, Algorithm engineering for public key algorithms. IEEE J. Sel. Areas Commun. 7(4), 458\u2013466 (1989)","journal-title":"IEEE J. Sel. Areas Commun."},{"key":"2886_CR4","doi-asserted-by":"publisher","unstructured":"M.A. Garc\u00eda-Mart\u00ednez, R. Posada-G\u00f3mez, G. Morales-Luna, F. Rodr\u00edguez-Henr\u00edquez, FPGA implementation of an efficient multiplier over finite fields GF ($$2^m$$). in 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig\u201905) (2005). pp. 5\u201326. https:\/\/doi.org\/10.1109\/RECONFIG.2005.18","DOI":"10.1109\/RECONFIG.2005.18"},{"issue":"2","key":"2886_CR5","doi-asserted-by":"publisher","first-page":"143","DOI":"10.1049\/ip-cdt:19981906","volume":"145","author":"J-H Guo","year":"1998","unstructured":"J.-H. Guo, C.-L. Wang, Digit-serial systolic multiplier for finite fields GF($$2^m$$). IEE Proc.-Comput. Digit. Tech. 145(2), 143\u2013148 (1998)","journal-title":"IEE Proc.-Comput. Digit. Tech."},{"key":"2886_CR6","volume-title":"Guide to Elliptic Curve Cryptography","author":"D Hankerson","year":"2003","unstructured":"D. Hankerson, A.J. Menezes, S. Vanstone, Guide to Elliptic Curve Cryptography (Springer, Berlin, Heidelberg, 2003)"},{"issue":"4","key":"2886_CR7","doi-asserted-by":"publisher","first-page":"667","DOI":"10.1109\/TVLSI.2021.3058509","volume":"29","author":"M Heidarpur","year":"2021","unstructured":"M. Heidarpur, M. Mirhassani, An efficient and high-speed overlap-free Karatsuba-based finite-field multiplier for FPGA implementation. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 29(4), 667\u2013676 (2021)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"12","key":"2886_CR8","doi-asserted-by":"publisher","first-page":"13079","DOI":"10.1016\/j.aej.2022.07.013","volume":"61","author":"A Ibrahim","year":"2022","unstructured":"A. Ibrahim, F. Gebali, Compact hardware accelerator for field multipliers suitable for use in ultra-low power IoT edge devices. Elsevier-Alex. Eng. J. 61(12), 13079\u201313087 (2022)","journal-title":"Elsevier-Alex. Eng. J."},{"issue":"10","key":"2886_CR9","doi-asserted-by":"publisher","first-page":"102188","DOI":"10.1016\/j.asej.2023.102188","volume":"14","author":"A Ibrahim","year":"2023","unstructured":"A. Ibrahim, Low-complexity systolic array structure for field multiplication in resource-constrained IoT nodes. Ain Shams Eng. J. 14(10), 102188 (2023)","journal-title":"Ain Shams Eng. J."},{"issue":"3","key":"2886_CR10","doi-asserted-by":"publisher","first-page":"223","DOI":"10.1049\/cdt2.12026","volume":"15","author":"A Ibrahim","year":"2021","unstructured":"A. Ibrahim, Low-space bit-serial systolic array architecture for interleaved multiplication over GF ($$2^m$$). IET Comput. Digit. Tech. 15(3), 223\u2013229 (2021)","journal-title":"IET Comput. Digit. Tech."},{"issue":"11","key":"2886_CR11","doi-asserted-by":"publisher","first-page":"2894","DOI":"10.1109\/TCSI.2017.2691353","volume":"64","author":"A Ibrahim","year":"2017","unstructured":"A. Ibrahim, F. Gebali, Scalable and unified digit-serial processor array architecture for multiplication and inversion over GF ($$2^m$$). IEEE Trans. Circuits Syst. I Regul. Pap. 64(11), 2894\u20132906 (2017)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"issue":"5","key":"2886_CR12","doi-asserted-by":"publisher","first-page":"520","DOI":"10.1109\/TC.2006.69","volume":"55","author":"JL Ima\u00f1a","year":"2006","unstructured":"J.L. Ima\u00f1a, J.M. Sanchez, F. Tirado, Bit-parallel finite field multipliers for irreducible trinomials. IEEE Trans. Comput. 55(5), 520\u2013533 (2006)","journal-title":"IEEE Trans. Comput."},{"key":"2886_CR13","doi-asserted-by":"publisher","unstructured":"D. Jao, In: Stavroulakis, P., Stamp, M. (eds.) Elliptic Curve Cryptography (Springer, Berlin, Heidelberg, 2010), pp. 35\u201357. https:\/\/doi.org\/10.1007\/978-3-642-04117-4_3","DOI":"10.1007\/978-3-642-04117-4_3"},{"issue":"4","key":"2886_CR14","doi-asserted-by":"publisher","first-page":"476","DOI":"10.1109\/TVLSI.2004.842923","volume":"13","author":"CH Kim","year":"2005","unstructured":"C.H. Kim, C.P. Hong, S. Kwon, A digit-serial multiplier for finite field GF($$2^m$$). IEEE Trans. Very Large Scale Integr. VLSI Syst. 13(4), 476\u2013483 (2005)","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"key":"2886_CR15","doi-asserted-by":"crossref","unstructured":"C.H. Kim, S. Kwon, C.P. Hong, A fast digit-serial systolic multiplier for finite field GF$$(2^m)$$. in Proceedings of the 2005 Asia and South Pacific Design Automation Conference (2005), pp. 1268\u20131271 (2005)","DOI":"10.1109\/ASPDAC.2005.1466574"},{"issue":"2","key":"2886_CR16","doi-asserted-by":"publisher","first-page":"194","DOI":"10.1080\/03772063.2014.914699","volume":"60","author":"K-W Kim","year":"2014","unstructured":"K.-W. Kim, J.-C. Jeon, Polynomial basis multiplier using cellular systolic architecture. IETE J. Res. 60(2), 194\u2013199 (2014)","journal-title":"IETE J. Res."},{"key":"2886_CR17","doi-asserted-by":"crossref","unstructured":"C.-Y. Lee, J. Xie, Efficient subquadratic space complexity digit-serial multipliers over GF$$(2^m)$$ based on bivariate polynomial basis representation. in 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) (2020), pp. 253\u2013258","DOI":"10.1109\/ASP-DAC47756.2020.9045615"},{"issue":"4","key":"2886_CR18","first-page":"1091","volume":"62","author":"C-Y Lee","year":"2015","unstructured":"C.-Y. Lee, P.K. Meher, Subquadratic space-complexity digit-serial multipliers over GF$$(2^{m})$$ using generalized $$(a, b) $$-way Karatsuba algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 62(4), 1091\u20131098 (2015)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"2886_CR19","doi-asserted-by":"publisher","first-page":"774","DOI":"10.1007\/s00034-018-0884-7","volume":"38","author":"BK Meher","year":"2019","unstructured":"B.K. Meher, P.K. Meher, Analysis of systolic penalties and design of efficient digit-level systolic-like multiplier for binary extension fields. Circuits Syst. Sign. Process. 38, 774\u2013790 (2019)","journal-title":"Circuits Syst. Sign. Process."},{"key":"2886_CR20","doi-asserted-by":"crossref","unstructured":"P.K. Meher, Systolic formulation for low-complexity serial-parallel implementation of unified finite field multiplication over GF($$2^m$$). in 2007 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP) (2007), pp. 134\u2013139","DOI":"10.1109\/ASAP.2007.4429970"},{"issue":"1","key":"2886_CR21","doi-asserted-by":"publisher","first-page":"55","DOI":"10.1049\/ip-cds:19981651","volume":"145","author":"M Mekhallalati","year":"1998","unstructured":"M. Mekhallalati, M. Ibrahim, A. Ashur, New low complexity bidirectional systolic structures for serial multiplication over the finite field GF($$q^m$$). IEE Proc.-Circuits Dev. Syst. 145(1), 55\u201360 (1998)","journal-title":"IEE Proc.-Circuits Dev. Syst."},{"key":"2886_CR22","unstructured":"National Institute of Standards and Technology (NIST). https:\/\/csrc.nist.gov\/"},{"issue":"7","key":"2886_CR23","doi-asserted-by":"publisher","first-page":"1614","DOI":"10.1109\/TVLSI.2019.2903289","volume":"27","author":"J-S Pan","year":"2019","unstructured":"J.-S. Pan, C.-Y. Lee, A. Sghaier, M. Zeghid, J. Xie, Novel systolization of subquadratic space complexity multipliers based on toeplitz matrix-vector product approach. IEEE Trans. Very Large Scale Integr. VLSI Syst. 27(7), 1614\u20131622 (2019)","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"key":"2886_CR24","doi-asserted-by":"publisher","unstructured":"D. Pradhan, B.K. Meher, P.K. Meher, Digit-size selection for FPGA implementation of generic digit-serial multiplication over GF($$2^m$$). in 2023 1st International Conference on Circuits, Power and Intelligent Systems (CCPIS) (2023), pp. 1\u20136. https:\/\/doi.org\/10.1109\/CCPIS59145.2023.10291975","DOI":"10.1109\/CCPIS59145.2023.10291975"},{"key":"2886_CR25","doi-asserted-by":"publisher","unstructured":"D. Pradhan, P.K. Meher, B.K. Meher, Input\u2013output scheduling and control for efficient FPGA realization of digit-serial multiplication over generic binary extension fields. Springer Journal of Circuits, Systems, and Signal Processing. (Published online, August 2024). https:\/\/doi.org\/10.1007\/s00034-024-02793-0","DOI":"10.1007\/s00034-024-02793-0"},{"issue":"8","key":"2886_CR26","doi-asserted-by":"publisher","first-page":"945","DOI":"10.1109\/TC.2004.47","volume":"53","author":"A Reyhani-Masoleh","year":"2004","unstructured":"A. Reyhani-Masoleh, M.A. Hasan, Low complexity bit parallel architectures for polynomial basis multiplication over GF ($$2^m$$). IEEE Trans. Comput. 53(8), 945\u2013959 (2004)","journal-title":"IEEE Trans. Comput."},{"key":"2886_CR27","doi-asserted-by":"publisher","first-page":"149","DOI":"10.1023\/A:1008013818413","volume":"19","author":"L Song","year":"1998","unstructured":"L. Song, K.K. Parhi, Low-energy digit-serial\/parallel finite field multipliers. J. VLSI Sign. Process. Syst. Sign. Image Video Technol. 19, 149\u2013166 (1998)","journal-title":"J. VLSI Sign. Process. Syst. Sign. Image Video Technol."},{"key":"2886_CR28","unstructured":"W. Tang, H. Wu, M. Ahmadi, VLSI implementation of bit-parallel word-serial multiplier in GF($$2^{233}$$). in The 3rd International IEEE-NEWCAS Conference, 2005 (2005), pp 399\u2013402"},{"key":"2886_CR29","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2023.3299508","author":"M Thirumoorthi","year":"2023","unstructured":"M. Thirumoorthi, A.J. Leigh, M. Heidarpur, M. Khalid, M. Mirhassani, Novel formulations of m-term overlap-free Karatsuba binary polynomial multipliers and their hardware implementations. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. (2023). https:\/\/doi.org\/10.1109\/TVLSI.2023.3299508","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"2886_CR30","doi-asserted-by":"crossref","unstructured":"X. Wang, N. Wu, F. Zhou, F. Ge, Efficient configurable digit-serial multiplier based on improved Karatsuba algorithm over GF$$(2^m)$$. in 2022 IEEE 22nd International Conference on Communication Technology (ICCT) (2022), pp. 1531\u20131535","DOI":"10.1109\/ICCT56141.2022.10072558"},{"key":"2886_CR31","doi-asserted-by":"crossref","unstructured":"E. Wenger, M. Hutter, Exploring the design space of prime field versus binary field ECC-hardware implementations. in Nordic Conference on Secure IT Systems (Springer, 2011), pp. 256\u2013271","DOI":"10.1007\/978-3-642-29615-4_18"},{"issue":"7","key":"2886_CR32","doi-asserted-by":"publisher","first-page":"750","DOI":"10.1109\/TC.2002.1017695","volume":"51","author":"H Wu","year":"2002","unstructured":"H. Wu, Bit-parallel finite field multiplier and squarer using polynomial basis. IEEE Trans. Comput. 51(7), 750\u2013758 (2002)","journal-title":"IEEE Trans. Comput."},{"key":"2886_CR33","doi-asserted-by":"publisher","first-page":"2565","DOI":"10.1109\/ICCCAS.2006.285197","volume":"4","author":"H Wu","year":"2006","unstructured":"H. Wu, Low complexity bit-parallel multiplier for a class of finite fields. 2006 Int. Conf. Commun. Circuits Syst. 4, 2565\u20132568 (2006)","journal-title":"2006 Int. Conf. Commun. Circuits Syst."},{"issue":"9","key":"2886_CR34","doi-asserted-by":"publisher","first-page":"2119","DOI":"10.1109\/TVLSI.2019.2918836","volume":"27","author":"J Xie","year":"2019","unstructured":"J. Xie, C.-Y. Lee, P.K. Meher, Z.-H. Mao, Novel bit-parallel and digit-serial systolic finite field multipliers over GF$$(2^m)$$ based on reordered normal basis. IEEE Trans. Very Large Scale Integr. VLSI Syst. 27(9), 2119\u20132130 (2019)","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"issue":"7","key":"2886_CR35","doi-asserted-by":"publisher","first-page":"1815","DOI":"10.1109\/TCSI.2017.2677962","volume":"64","author":"J Xie","year":"2017","unstructured":"J. Xie, P.K. Meher, M. Sun, Y. Li, B. Zeng, Z.-H. Mao, Efficient FPGA implementation of low-complexity systolic Karatsuba multiplier over GF$$(2^{m})$$ based on NIST polynomials. IEEE Trans. Circuits Syst. I Regul. Pap. 64(7), 1815\u20131825 (2017)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"issue":"8","key":"2886_CR36","doi-asserted-by":"publisher","first-page":"1192","DOI":"10.1109\/TVLSI.2023.3268999","volume":"31","author":"M Zeghid","year":"2023","unstructured":"M. Zeghid, H.Y. Ahmed, A. Chehri, A. Sghaier, Speed\/area-efficient ECC processor implementation over $$GF(2^m)$$ on FPGA via novel algorithm-architecture co-design. IEEE Trans. Very Large Scale Integr. VLSI Syst. 31(8), 1192\u20131203 (2023)","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-024-02886-w.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-024-02886-w\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-024-02886-w.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,17]],"date-time":"2025-03-17T19:27:45Z","timestamp":1742239665000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-024-02886-w"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,11,5]]},"references-count":36,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2025,3]]}},"alternative-id":["2886"],"URL":"https:\/\/doi.org\/10.1007\/s00034-024-02886-w","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,11,5]]},"assertion":[{"value":"2 August 2024","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"24 September 2024","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"26 September 2024","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"5 November 2024","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare that they have no potential Conflict of interest.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}},{"value":"This research does not use any animal or does not use any information relating to animals.","order":3,"name":"Ethics","group":{"name":"EthicsHeading","label":"Ethics Approval"}},{"value":"No participants were included in the study. It contains the contribution of authors only.","order":4,"name":"Ethics","group":{"name":"EthicsHeading","label":"Consent to Participate"}},{"value":"All the authors have consented to submission of this paper to the Journal of Circuits, Systems, and Signal Processing. No consent from any other organization or individual is required for the submission of this manuscript for publication.","order":5,"name":"Ethics","group":{"name":"EthicsHeading","label":"Consent for Publication"}}]}}