{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,2]],"date-time":"2025-07-02T04:24:07Z","timestamp":1751430247552,"version":"3.41.0"},"reference-count":26,"publisher":"Springer Science and Business Media LLC","issue":"7","license":[{"start":{"date-parts":[[2025,3,6]],"date-time":"2025-03-06T00:00:00Z","timestamp":1741219200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,3,6]],"date-time":"2025-03-06T00:00:00Z","timestamp":1741219200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2025,7]]},"DOI":"10.1007\/s00034-025-03033-9","type":"journal-article","created":{"date-parts":[[2025,3,6]],"date-time":"2025-03-06T09:06:52Z","timestamp":1741252012000},"page":"5343-5356","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Design of Area Efficient In-Memory Adder and Sum-Comparator with a Variable Reference Voltage Mechanism"],"prefix":"10.1007","volume":"44","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-4384-7722","authenticated-orcid":false,"given":"Linknath Surya","family":"Balasubramanian","sequence":"first","affiliation":[]},{"given":"Elijah Eric","family":"Racz","sequence":"additional","affiliation":[]},{"given":"Anoop","family":"Gopinath","sequence":"additional","affiliation":[]},{"given":"Maher","family":"Rizkalla","sequence":"additional","affiliation":[]},{"given":"John J.","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Trond","family":"Ytterdal","sequence":"additional","affiliation":[]},{"given":"Mukesh","family":"Kumar","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2025,3,6]]},"reference":[{"key":"3033_CR1","doi-asserted-by":"publisher","first-page":"4219","DOI":"10.1109\/TCSI.2018.2848999","volume":"65","author":"A Agrawal","year":"2017","unstructured":"A. Agrawal, A.R. Jaiswal, C. Lee, K. Roy, X-SRAM: enabling in-memory boolean computations in CMOS static random access memories. IEEE Trans. Circ. Syst. I Regular Papers 65, 4219\u20134232 (2017)","journal-title":"IEEE Trans. Circ. Syst. I Regular Papers"},{"key":"3033_CR2","doi-asserted-by":"publisher","first-page":"814","DOI":"10.1088\/1402-4896\/ad0814","volume":"98","author":"SS Ahmadpour","year":"2023","unstructured":"S.S. Ahmadpour, N.J. Navimipour, A new nano-design of 16-bit carry look-ahead adder based on quantum technology. Phys. Scripta 98, 814 (2023). https:\/\/doi.org\/10.1088\/1402-4896\/ad0814","journal-title":"Phys. Scripta"},{"key":"3033_CR3","doi-asserted-by":"publisher","first-page":"81","DOI":"10.55549\/epstem.1337631","volume":"22","author":"SS Ahmadpour","year":"2023","unstructured":"S.S. Ahmadpour, N.J. Navimipour, F. Kerestec\u0131oglu, A new nano-design of an efficient synchronous full-adder\/subtractor based on quantum-dots. Eurasia Proc. Sci. Technol. Eng. Math. 22, 81\u201386 (2023). https:\/\/doi.org\/10.55549\/epstem.1337631","journal-title":"Eurasia Proc. Sci. Technol. Eng. Math."},{"key":"3033_CR4","doi-asserted-by":"crossref","unstructured":"K.C. Akyel, H.P. Charles, J.\u00a0Mottin, B.\u00a0Giraud, G.\u00a0Suraci, S.\u00a0Thuries, and J.P. Noel 2016. DRC2: Dynamically reconfigurable computing circuit based on memory architecture. In International Conference on Rebooting Computing","DOI":"10.1109\/ICRC.2016.7738698"},{"issue":"8","key":"3033_CR5","doi-asserted-by":"publisher","first-page":"2521","DOI":"10.1109\/TCSI.2020.2981901","volume":"67","author":"M Ali","year":"2020","unstructured":"M. Ali, A. Jaiswal, S. Kodge, A. Agrawal, I. Chakraborty, K. Roy, IMAC: In-memory multi-bit multiplication and accumulation in 6T SRAM array. IEEE Trans. Circuits Syst. I Regul. Pap. 67(8), 2521\u20132531 (2020). https:\/\/doi.org\/10.1109\/TCSI.2020.2981901","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"3033_CR6","doi-asserted-by":"crossref","unstructured":"H.C. Chen, J.F. Li, C.L. Hsu, and C.T. Sun. 2019. Configurable 8T SRAM for enbling in-memory computing. 2019 2nd International Conference on Communication Engineering and Technology (ICCET): 139\u2013142","DOI":"10.1109\/ICCET.2019.8726871"},{"key":"3033_CR7","doi-asserted-by":"crossref","unstructured":"Y. Chen, L.\u00a0Lu, B.\u00a0Kim, and T.T.H. Kim. 2020. Reconfigurable 2T2R reram architecture for versatile data storage and computing in-memory","DOI":"10.1109\/TVLSI.2020.3028848"},{"issue":"11","key":"3033_CR8","doi-asserted-by":"publisher","first-page":"1484","DOI":"10.1109\/12.177318","volume":"41","author":"J Cortadella","year":"1992","unstructured":"J. Cortadella, J. Llaberia, Evaluation of A+B = K conditions without carry propagation. IEEE Trans. Comput. 41(11), 1484\u20131488 (1992). https:\/\/doi.org\/10.1109\/12.177318","journal-title":"IEEE Trans. Comput."},{"key":"3033_CR9","doi-asserted-by":"publisher","first-page":"674154","DOI":"10.3389\/fncom.2021.674154","volume":"15","author":"M Dazzi","year":"2021","unstructured":"M. Dazzi, A. Sebastian, L. Benini, E. Eleftheriou, Accelerating inference of convolutional neural networks using in-memory computing. Front. Comput. Neurosci. 15, 674154 (2021)","journal-title":"Front. Comput. Neurosci."},{"key":"3033_CR10","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1007\/s00034-023-02481-5","volume":"43","author":"N Dhakad","year":"2023","unstructured":"N. Dhakad, E. Chittora, G. Raut, V. Sharma, S. Vishvakarma, 08. In-memory computing with 6T SRAM for multi-operator logic design. Circ. Syst. Signal Process 43, 1\u201315 (2023). https:\/\/doi.org\/10.1007\/s00034-023-02481-5","journal-title":"Circ. Syst. Signal Process"},{"key":"3033_CR11","doi-asserted-by":"crossref","unstructured":"D. Fujiki, X.\u00a0Wang, A.\u00a0Subramaniyan, and R.\u00a0Das. 2021. In-\/near-memory computing. Springer Cham","DOI":"10.1007\/978-3-031-01772-8"},{"issue":"37","key":"3033_CR12","doi-asserted-by":"publisher","first-page":"2204944","DOI":"10.1002\/adma.202204944","volume":"35","author":"W Haensch","year":"2023","unstructured":"W. Haensch, A. Raghunathan, K. Roy, B. Chakrabarti, C.M. Phatak, C. Wang, S. Guha, Compute in-memory with non-volatile elements for neural networks: A review from a co-design perspective. Adv. Mater. 35(37), 2204944 (2023)","journal-title":"Adv. Mater."},{"issue":"7","key":"3033_CR13","doi-asserted-by":"publisher","first-page":"2000040","DOI":"10.1002\/aisy.202000040","volume":"2","author":"D Ielmini","year":"2020","unstructured":"D. Ielmini, G. Pedretti, Device and circuit architectures for in-memory computing. Adv. Intelli. Syst. 2(7), 2000040 (2020)","journal-title":"Adv. Intelli. Syst."},{"issue":"6","key":"3033_CR14","doi-asserted-by":"publisher","first-page":"327","DOI":"10.1038\/s41928-020-0410-3","volume":"3","author":"G Karunaratne","year":"2020","unstructured":"G. Karunaratne, M. Le Gallo, G. Cherubini, L. Benini, A. Rahimi, A. Sebastian, In-memory hyperdimensional computing. Nature Electron. 3(6), 327\u2013337 (2020)","journal-title":"Nature Electron."},{"key":"3033_CR15","doi-asserted-by":"publisher","first-page":"117249","DOI":"10.1016\/j.mseb.2024.117249","volume":"302","author":"SR Kassa","year":"2024","unstructured":"S.R. Kassa, S.S. Ahmadpour, V. Lamba, N.K. Misra, N.J. Navimipour, K. Kotecha, A cost- and energy-efficient sram design based on a new 5 i-p majority gate in qca nanotechnology. Mater. Sci. Eng. B 302, 117249 (2024). https:\/\/doi.org\/10.1016\/j.mseb.2024.117249","journal-title":"Mater. Sci. Eng. B"},{"key":"3033_CR16","doi-asserted-by":"publisher","first-page":"4369","DOI":"10.1140\/epjp\/s13360-023-04369-4","volume":"138","author":"SR Kassa","year":"2023","unstructured":"S.R. Kassa, N.K. Misra, S.S. Ahmadpour, V. Lamba, N. Vadthiya, A novel design of coplanar 8-bit ripple carry adder using field-coupled quantum-dot cellular automata nanotechnology. Europ. Phys. J. Plus 138, 4369 (2023). https:\/\/doi.org\/10.1140\/epjp\/s13360-023-04369-4","journal-title":"Europ. Phys. J. Plus"},{"key":"3033_CR17","doi-asserted-by":"publisher","first-page":"102276","DOI":"10.1016\/j.sysarc.2021.102276","volume":"119","author":"S Mittal","year":"2021","unstructured":"S. Mittal, G. Verma, B. Kaushik, F.A. Khanday, A survey of SRAM-based in-memory computing techniques and applications. J. Syst. Architect. 119, 102276 (2021)","journal-title":"J. Syst. Architect."},{"key":"3033_CR18","unstructured":"N. Muralimanohar, R.\u00a0Balasubramonian, and N.P. Jouppi. 2008. Cacti 6.0: A Tool to Understand Large Caches"},{"issue":"16","key":"3033_CR19","doi-asserted-by":"publisher","DOI":"10.3390\/ma13163532","volume":"13","author":"QF Ou","year":"2020","unstructured":"Q.F. Ou, B.S. Xiong, L. Yu, J. Wen, L. Wang, Y. Tong, In-memory logic operations and neuromorphic computing in non-volatile random access memory. Materials 13(16), 131635 (2020). https:\/\/doi.org\/10.3390\/ma13163532","journal-title":"Materials"},{"key":"3033_CR20","doi-asserted-by":"publisher","first-page":"100076","DOI":"10.1016\/j.memori.2023.100076","volume":"5","author":"AK Rajput","year":"2023","unstructured":"A.K. Rajput, M. Pattanaik, G. Kaushal, An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor. Memories - Mater. Dev. Circ. Syst. 5, 100076 (2023). https:\/\/doi.org\/10.1016\/j.memori.2023.100076","journal-title":"Memories - Mater. Dev. Circ. Syst."},{"issue":"3","key":"3033_CR21","doi-asserted-by":"publisher","first-page":"28","DOI":"10.3390\/jlpea10030028","volume":"10","author":"J Reuben","year":"2020","unstructured":"J. Reuben, Rediscovering majority logic in the post-CMOS era: a perspective from in-memory computing. J. Low Power Electron. Appl. 10(3), 28 (2020)","journal-title":"J. Low Power Electron. Appl."},{"issue":"7","key":"3033_CR22","doi-asserted-by":"publisher","first-page":"529","DOI":"10.1038\/s41565-020-0655-z","volume":"15","author":"A Sebastian","year":"2020","unstructured":"A. Sebastian, M. Le Gallo, R. Khaddam-Aljameh, E. Eleftheriou, Memory devices and applications for in-memory computing. Nat. Nanotechnol. 15(7), 529\u2013544 (2020)","journal-title":"Nat. Nanotechnol."},{"key":"3033_CR23","doi-asserted-by":"publisher","first-page":"97","DOI":"10.5121\/vlsic.2012.3108","volume":"3","author":"S Singh","year":"2012","unstructured":"S. Singh, 02. Performance evaluation of different SRAM cell structures at different technologies. Int. J. VLSI Des. Commun. Syst. 3, 97\u2013109 (2012). https:\/\/doi.org\/10.5121\/vlsic.2012.3108","journal-title":"Int. J. VLSI Des. Commun. Syst."},{"key":"3033_CR24","doi-asserted-by":"crossref","unstructured":"V. Snasel, T.K. Dang, J.\u00a0Kueng, and L.\u00a0Kong. 2023. A review of in-memory computing for machine learning: architectures, options. International Journal of Web Information Systems\u00a0(ahead-of-print)","DOI":"10.1108\/IJWIS-08-2023-0131"},{"key":"3033_CR25","doi-asserted-by":"publisher","first-page":"117040","DOI":"10.1016\/j.mseb.2023.117040","volume":"300","author":"A Taghavirashidizadeh","year":"2024","unstructured":"A. Taghavirashidizadeh, S.S. Ahmadpour, S. Ahmed, N.J. Navimipour, S.R. Kassa, S. Yalcin, A new design of a digital filter for an efficient field programmable gate array using quantum dot technology. Mater. Sci. Eng., B 300, 117040 (2024). https:\/\/doi.org\/10.1016\/j.mseb.2023.117040","journal-title":"Mater. Sci. Eng., B"},{"key":"3033_CR26","volume-title":"CMOS VLSI Design: A Circuits and Systems Perspective","author":"N Weste","year":"2010","unstructured":"N. Weste, D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th edn. (Addison-Wesley Publishing Company, USA, 2010)","edition":"4"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-025-03033-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-025-03033-9\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-025-03033-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T21:01:42Z","timestamp":1751403702000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-025-03033-9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,6]]},"references-count":26,"journal-issue":{"issue":"7","published-print":{"date-parts":[[2025,7]]}},"alternative-id":["3033"],"URL":"https:\/\/doi.org\/10.1007\/s00034-025-03033-9","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2025,3,6]]},"assertion":[{"value":"19 March 2024","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"2 February 2025","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"4 February 2025","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"6 March 2025","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors have no relevant financial or non-financial interests to disclose.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}]}}