{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T16:48:14Z","timestamp":1775666894687,"version":"3.50.1"},"reference-count":42,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2025,3,21]],"date-time":"2025-03-21T00:00:00Z","timestamp":1742515200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,3,21]],"date-time":"2025-03-21T00:00:00Z","timestamp":1742515200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2026,1]]},"DOI":"10.1007\/s00034-025-03047-3","type":"journal-article","created":{"date-parts":[[2025,3,22]],"date-time":"2025-03-22T22:05:41Z","timestamp":1742681141000},"page":"343-363","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["Novel Charge Plasma Vertically Stacked Dopingless Nanosheet Field-Effect Transistor (DL-NSFET): Proposal and Extensive Analysis"],"prefix":"10.1007","volume":"45","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7780-3114","authenticated-orcid":false,"given":"Abhishek","family":"Chauhan","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6720-373X","authenticated-orcid":false,"given":"Ashish","family":"Raman","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2025,3,21]]},"reference":[{"issue":"6","key":"3047_CR1","doi-asserted-by":"publisher","first-page":"2659","DOI":"10.1007\/s12633-024-02871-7","volume":"16","author":"A Angelin Delighta","year":"2024","unstructured":"A. Angelin Delighta, K. Binola, I.V. Jebalin, J. Ajayan, S. Angen Franklin, D. Nirmal, A new vertical c-shaped silicon channel nanosheet FET with stacked high-k dielectrics for low power applications. SILICON 16(6), 2659\u20132670 (2024). https:\/\/doi.org\/10.1007\/s12633-024-02871-7","journal-title":"SILICON"},{"key":"3047_CR2","doi-asserted-by":"publisher","first-page":"94","DOI":"10.1007\/S10825-015-0771-4\/METRICS","volume":"15","author":"S Anand","year":"2016","unstructured":"S. Anand, S.I. Amin, R.K. Sarin, Analog performance investigation of dual electrode based doping-less tunnel FET. J. Comput. Electron. 15, 94\u2013103 (2016). https:\/\/doi.org\/10.1007\/S10825-015-0771-4\/METRICS","journal-title":"J. Comput. Electron."},{"key":"3047_CR3","unstructured":"ATLAS User\u2019s Manual. ATLAS Device Simulation Software, Silvaco International (Santa Clara, California, 2014)."},{"key":"3047_CR4","doi-asserted-by":"publisher","first-page":"123","DOI":"10.1109\/TED.2013.2292852","volume":"61","author":"RK Baruah","year":"2014","unstructured":"R.K. Baruah, R.P. Paily, A dual-material gate junctionless transistor with high-$k$ spacer for enhanced analog performance. IEEE Trans. Electron Devices 61, 123\u2013128 (2014). https:\/\/doi.org\/10.1109\/TED.2013.2292852","journal-title":"IEEE Trans. Electron Devices"},{"issue":"3","key":"3047_CR5","doi-asserted-by":"publisher","first-page":"225","DOI":"10.1038\/nnano.2010.15","volume":"5","author":"JP Colinge","year":"2010","unstructured":"J.P. Colinge et al., Nanowire transistors without junctions. Nat. Nanotechnol. 5(3), 225\u2013229 (2010). https:\/\/doi.org\/10.1038\/nnano.2010.15","journal-title":"Nat. Nanotechnol."},{"key":"3047_CR6","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2009.5318737","author":"JP Colinge","year":"2009","unstructured":"J.P. Colinge et al., SOI gated resistor: CMOS without junctions. Proc. IEEE Int. SOI Conf. (2009). https:\/\/doi.org\/10.1109\/SOI.2009.5318737","journal-title":"Proc. IEEE Int. SOI Conf."},{"key":"3047_CR7","doi-asserted-by":"publisher","first-page":"2329","DOI":"10.1007\/s12633-019-00331-1","volume":"12","author":"AK Gupta","year":"2020","unstructured":"A.K. Gupta, A. Raman, N. Kumar, Cylindrical nanowire-TFET with core-shell channel architecture: design and investigation. SILICON 12, 2329\u20132336 (2020). https:\/\/doi.org\/10.1007\/s12633-019-00331-1","journal-title":"SILICON"},{"key":"3047_CR8","doi-asserted-by":"publisher","first-page":"1367","DOI":"10.1109\/LED.2008.2006864","volume":"29","author":"RJE Hueting","year":"2008","unstructured":"R.J.E. Hueting, B. Rajasekharan, C. Salm, J. Schmitz, The charge plasma P-N diode. IEEE Electron Device Lett. 29, 1367\u20131369 (2008). https:\/\/doi.org\/10.1109\/LED.2008.2006864","journal-title":"IEEE Electron Device Lett."},{"key":"3047_CR9","doi-asserted-by":"publisher","DOI":"10.1142\/S0129156417400018","author":"AP Jacob","year":"2017","unstructured":"A.P. Jacob et al., Scaling challenges for advanced CMOS devices. Int. J. High Speed Electron. Syst. (2017). https:\/\/doi.org\/10.1142\/S0129156417400018","journal-title":"Int. J. High Speed Electron. Syst."},{"key":"3047_CR10","doi-asserted-by":"publisher","first-page":"930","DOI":"10.1109\/TED.2022.3143473","volume":"69","author":"SG Jung","year":"2022","unstructured":"S.G. Jung, J.K. Kim, H.Y. Yu, Analytical model of contact resistance in vertically stacked nanosheet FETs for Sub-3-nm technology node. IEEE Trans. Electron Devices 69, 930\u2013935 (2022). https:\/\/doi.org\/10.1109\/TED.2022.3143473","journal-title":"IEEE Trans. Electron Devices"},{"key":"3047_CR11","doi-asserted-by":"publisher","first-page":"185","DOI":"10.1007\/1-4020-3013-4_19","volume-title":"Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment","author":"V Kilchytska","year":"2005","unstructured":"V. Kilchytska, L. Vancaillie, K. de Meyer, D. Flandre, MOSFETs scaling down: advantages and disadvantages for high temperature applications, in Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment. ed. by D. Flandre, A.N. Nazarov, P.L.F. Hemment (Springer Netherlands, Dordrecht, 2005), pp.185\u2013190. https:\/\/doi.org\/10.1007\/1-4020-3013-4_19"},{"key":"3047_CR12","doi-asserted-by":"publisher","unstructured":"S.R. Kola, Y.  Li, M.H. Chuang, Intrinsic Parameter Fluctuation and Process Variation Effect of Vertically Stacked Silicon Nanosheet Complementary Field-Effect Transistors. Proc. - Int. Symp. Qual. Electron. Des. ISQED 2023-April, 1\u20138 (2023). https:\/\/doi.org\/10.1109\/ISQED57927.2023.10129391","DOI":"10.1109\/ISQED57927.2023.10129391"},{"key":"3047_CR13","doi-asserted-by":"publisher","unstructured":"S.R. Kola, Y. Li, N.  Thoti,  Effects of spacer and single-charge trap on voltage transfer characteristics of gate-all-around silicon nanowire CMOS devices and circuits. In Proceedings of the IEEE Conference on Nanotechnology 217\u2013220 (IEEE Computer Society, 2020). https:\/\/doi.org\/10.1109\/NANO47656.2020.9183712.","DOI":"10.1109\/NANO47656.2020.9183712"},{"key":"3047_CR14","doi-asserted-by":"publisher","first-page":"3285","DOI":"10.1109\/TED.2013.2276888","volume":"60","author":"MJ Kumar","year":"2013","unstructured":"M.J. Kumar, S. Janardhanan, Doping-less tunnel field effect transistor: design and investigation. IEEE Trans. Electron Devices 60, 3285\u20133290 (2013). https:\/\/doi.org\/10.1109\/TED.2013.2276888","journal-title":"IEEE Trans. Electron Devices"},{"key":"3047_CR15","unstructured":"N. Kumar, A. Raman, Design and Investigation of Charge-Plasma- Based Work Function Engineered Dual-Metal- Cylindrical NWTFET for Ambipolar Analysis. 1\u20137."},{"key":"3047_CR16","doi-asserted-by":"publisher","first-page":"356","DOI":"10.1016\/j.spmi.2018.09.012","volume":"125","author":"N Kumar","year":"2019","unstructured":"N. Kumar, U. Mushtaq, S.I. Amin, S. Anand, Design and performance analysis of dual-gate all around core-shell nanotube TFET. Superlattices Microstruct. 125, 356\u2013364 (2019). https:\/\/doi.org\/10.1016\/j.spmi.2018.09.012","journal-title":"Superlattices Microstruct."},{"key":"3047_CR17","doi-asserted-by":"publisher","DOI":"10.1149\/2162-8777\/ACD65E","volume":"12","author":"NA Kumari","year":"2023","unstructured":"N.A. Kumari, V.B. Sreenivasulu, J. Ajayan, T.J. Reddy, P. Prithvi, Spacer engineering on nanosheet FETs towards device and circuit perspective. ECS J. Solid State Sci. Technol. 12, 053009 (2023). https:\/\/doi.org\/10.1149\/2162-8777\/ACD65E","journal-title":"ECS J. Solid State Sci. Technol."},{"key":"3047_CR18","doi-asserted-by":"publisher","DOI":"10.1063\/1.3079411","author":"CW Lee","year":"2009","unstructured":"C.W. Lee et al., Junctionless multigate field-effect transistor. Appl. Phys. Lett. (2009). https:\/\/doi.org\/10.1063\/1.3079411","journal-title":"Appl. Phys. Lett."},{"issue":"4","key":"3047_CR19","doi-asserted-by":"publisher","first-page":"2042","DOI":"10.1109\/TED.2023.3249650","volume":"70","author":"KS Lee","year":"2023","unstructured":"K.S. Lee, BDo. Yang, J.Y. Park, Trench gate nanosheet fet to suppress leakage current from substrate parasitic channel. IEEE Trans. Electron Devices 70(4), 2042\u20132046 (2023). https:\/\/doi.org\/10.1109\/TED.2023.3249650","journal-title":"IEEE Trans. Electron Devices"},{"issue":"3","key":"3047_CR20","doi-asserted-by":"publisher","first-page":"420","DOI":"10.3390\/mi15030420","volume":"15","author":"X Li","year":"2024","unstructured":"X. Li et al., Interaction of negative bias instability and self-heating effect on threshold voltage and SRAM (static random-access memory) stability of nanosheet field-effect transistors. Micromachines 15(3), 420 (2024). https:\/\/doi.org\/10.3390\/mi15030420","journal-title":"Micromachines"},{"key":"3047_CR21","doi-asserted-by":"publisher","first-page":"2135","DOI":"10.1109\/TED.2013.2262135","volume":"60","author":"B Liu","year":"2013","unstructured":"B. Liu et al., Germanium multiple-gate field-effect transistor with in situ boron-doped raised source\/drain. IEEE Trans. Electron Devices 60, 2135\u20132141 (2013). https:\/\/doi.org\/10.1109\/TED.2013.2262135","journal-title":"IEEE Trans. Electron Devices"},{"key":"3047_CR22","doi-asserted-by":"publisher","unstructured":"Loubet, N. et al. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. in Symposium on VLSI Technology T230\u2013T231 (Institute of Electrical and Electronics Engineers Inc., 2017). https:\/\/doi.org\/10.23919\/VLSIT.2017.7998183","DOI":"10.23919\/VLSIT.2017.7998183"},{"key":"3047_CR23","doi-asserted-by":"publisher","first-page":"2859","DOI":"10.1109\/TED.2008.2005158","volume":"55","author":"W Lu","year":"2008","unstructured":"W. Lu, P. Xie, C.M. Lieber, Nanowire transistor performance limits and applications. IEEE Trans. Electron Devices 55, 2859\u20132876 (2008). https:\/\/doi.org\/10.1109\/TED.2008.2005158","journal-title":"IEEE Trans. Electron Devices"},{"issue":"3","key":"3047_CR24","doi-asserted-by":"publisher","first-page":"33","DOI":"10.1109\/N-SSC.2006.4785860","volume":"11","author":"GE Moore","year":"2006","unstructured":"G.E. Moore, Cramming more components onto integrated circuits, Reprinted from Electronics, volume 38, number 8, April 19, 1965, pp.114 ff. IEEE Solid-State Circuits Soc Newslett 11(3), 33\u201335 (2006). https:\/\/doi.org\/10.1109\/N-SSC.2006.4785860","journal-title":"IEEE Solid-State Circuits Soc Newslett"},{"key":"3047_CR25","doi-asserted-by":"publisher","DOI":"10.1088\/1361-6641\/AC62FB","volume":"37","author":"S Rathore","year":"2022","unstructured":"S. Rathore, R.K. Jaisawal, P. Suryavanshi, P.N. Kondekar, Investigation of ambient temperature and thermal contact resistance induced self-heating effects in nanosheet FET. Semicond. Sci. Technol. 37, 055019 (2022). https:\/\/doi.org\/10.1088\/1361-6641\/AC62FB","journal-title":"Semicond. Sci. Technol."},{"key":"3047_CR26","doi-asserted-by":"publisher","DOI":"10.1016\/J.MSSP.2021.106002","author":"RK Ratnesh","year":"2021","unstructured":"R.K. Ratnesh et al., Advancement and challenges in MOSFET scaling. Mater. Sci. Semicond. Process. (2021). https:\/\/doi.org\/10.1016\/J.MSSP.2021.106002","journal-title":"Mater. Sci. Semicond. Process."},{"key":"3047_CR27","doi-asserted-by":"publisher","first-page":"411","DOI":"10.1109\/LED.2013.2297451","volume":"35","author":"C Sahu","year":"2014","unstructured":"C. Sahu, J. Singh, Charge-plasma based process variation immune junctionless transistor. IEEE Electron Device Lett. 35, 411\u2013413 (2014). https:\/\/doi.org\/10.1109\/LED.2013.2297451","journal-title":"IEEE Electron Device Lett."},{"key":"3047_CR28","doi-asserted-by":"publisher","first-page":"2655","DOI":"10.1007\/s12633-020-00618-8","volume":"13","author":"A Samal","year":"2021","unstructured":"A. Samal, K.P. Pradhan, S.K. Mohapatra, Improvising the switching ratio through Low-k \/ High-k spacer and dielectric gate stack in 3d finfet - a simulation perspective. SILICON 13, 2655\u20132660 (2021). https:\/\/doi.org\/10.1007\/s12633-020-00618-8","journal-title":"SILICON"},{"key":"3047_CR29","doi-asserted-by":"publisher","first-page":"1331","DOI":"10.1109\/LED.2011.2162577","volume":"32","author":"CH Shih","year":"2011","unstructured":"C.H. Shih, J.T. Liang, J.S. Wang, N.D. Chien, A source-side injection lucky electron model for schottky barrier metal-oxide-semiconductor devices. IEEE Electron Device Lett. 32, 1331\u20131333 (2011). https:\/\/doi.org\/10.1109\/LED.2011.2162577","journal-title":"IEEE Electron Device Lett."},{"key":"3047_CR30","doi-asserted-by":"publisher","first-page":"3294","DOI":"10.1109\/TED.2011.2161479","volume":"58","author":"X Sun","year":"2011","unstructured":"X. Sun, V. Moroz, N. Damrongplasit, C. Shin, T.J.K. Liu, Variation study of the planar ground-plane bulk MOSFET, SOI FinFET, and trigate bulk MOSFET designs. IEEE Trans. Electron Devices 58, 3294\u20133299 (2011). https:\/\/doi.org\/10.1109\/TED.2011.2161479","journal-title":"IEEE Trans. Electron Devices"},{"key":"3047_CR31","doi-asserted-by":"publisher","unstructured":"Tan, C. M., Chen, X. Random dopant fluctuation in gate-all-around nanowire FET. 2014 IEEE Int. Nanoelectron. Conf. INEC 2014 (2016) https:\/\/doi.org\/10.1109\/INEC.2014.7460459.","DOI":"10.1109\/INEC.2014.7460459"},{"key":"3047_CR32","doi-asserted-by":"publisher","first-page":"287","DOI":"10.1016\/J.SPMI.2017.09.031","volume":"112","author":"S Tayal","year":"2017","unstructured":"S. Tayal, A. Nandi, Analog\/RF performance analysis of channel engineered high-K gate-stack based junctionless Trigate-FinFET. Superlattices Microstruct. 112, 287\u2013295 (2017). https:\/\/doi.org\/10.1016\/J.SPMI.2017.09.031","journal-title":"Superlattices Microstruct."},{"key":"3047_CR33","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1007\/s00339-017-1176-y","volume":"123","author":"N Trivedi","year":"2017","unstructured":"N. Trivedi et al., Charge plasma technique based dopingless accumulation mode junctionless cylindrical surrounding gate MOSFET: analog performance improvement. Appl. Phys. A Mater. Sci. Process. 123, 1\u20137 (2017)","journal-title":"Appl. Phys. A Mater. Sci. Process."},{"key":"3047_CR34","doi-asserted-by":"publisher","first-page":"10347","DOI":"10.1007\/s12633-022-01793-6","volume":"14","author":"S Valasa","year":"2022","unstructured":"S. Valasa, S. Tayal, L.R. Thoutam, Optimization of design space for vertically stacked junctionless nanosheet FET for analog\/RF applications. SILICON 14, 10347\u201310356 (2022). https:\/\/doi.org\/10.1007\/s12633-022-01793-6","journal-title":"SILICON"},{"key":"3047_CR35","doi-asserted-by":"publisher","DOI":"10.1016\/J.MICRNA.2022.207374","volume":"170","author":"S Valasa","year":"2022","unstructured":"S. Valasa, S. Tayal, L.R. Thoutam, J. Ajayan, S. Bhattacharya, A critical review on performance, reliability, and fabrication challenges in nanosheet FET for future analog\/digital IC applications. Micro Nanostruct 170, 207374 (2022). https:\/\/doi.org\/10.1016\/J.MICRNA.2022.207374","journal-title":"Micro Nanostruct"},{"key":"3047_CR36","doi-asserted-by":"publisher","unstructured":"Wang, M. et al. Bias Temperature Instability Reliability in Stacked Gate-All-Around Nanosheet Transistor. IEEE Int. Reliab. Phys. Symp. Proc. 2019-March, 1\u20136 (2019). https:\/\/doi.org\/10.1109\/IRPS.2019.8720573","DOI":"10.1109\/IRPS.2019.8720573"},{"key":"3047_CR37","doi-asserted-by":"publisher","first-page":"1742","DOI":"10.1109\/16.536820","volume":"43","author":"CII Wann","year":"1996","unstructured":"C.I.I. Wann, K. Noda, T. Tanaka, M. Yoshida, C. Hu, A comparative study of advanced MOSFET concepts. IEEE Trans. Electron Devices 43, 1742\u20131753 (1996). https:\/\/doi.org\/10.1109\/16.536820","journal-title":"IEEE Trans. Electron Devices"},{"key":"3047_CR38","doi-asserted-by":"publisher","first-page":"217","DOI":"10.1007\/s12633-022-01989-w","volume":"15","author":"N Yadav","year":"2023","unstructured":"N. Yadav, S. Jadav, G. Saini, Impact of gate length and doping variation on the DC and analog\/RF performance of sub\u20143nm stacked si gate-all-around nanosheet FET. SILICON 15, 217\u2013228 (2023). https:\/\/doi.org\/10.1007\/s12633-022-01989-w","journal-title":"SILICON"},{"key":"3047_CR39","doi-asserted-by":"publisher","first-page":"5295","DOI":"10.1109\/TED.2018.2877415","volume":"65","author":"HY Ye","year":"2018","unstructured":"H.Y. Ye, C.C. Chung, C.W. Liu, Mobility calculation of ge nanowire junctionless and inversion-mode nanowire NFETs with size and shape dependence. IEEE Trans. Electron Devices 65, 5295\u20135300 (2018). https:\/\/doi.org\/10.1109\/TED.2018.2877415","journal-title":"IEEE Trans. Electron Devices"},{"key":"3047_CR40","doi-asserted-by":"publisher","first-page":"1739","DOI":"10.1007\/s12633-022-02137-0","volume":"15","author":"R Yuvaraj","year":"2023","unstructured":"R. Yuvaraj, A. Karuppannan, A.K. Panigrahy, R. Swain, Design and analysis of gate stack silicon-on-insulator nanosheet fet for low power applications. SILICON 15, 1739\u20131746 (2023). https:\/\/doi.org\/10.1007\/s12633-022-02137-0","journal-title":"SILICON"},{"key":"3047_CR41","doi-asserted-by":"publisher","first-page":"203","DOI":"10.1063\/1.2062964","volume":"788","author":"PM Zeitzoff","year":"2005","unstructured":"P.M. Zeitzoff, H.R. Huff, MOSFET scaling trends, challenges, and key associated metrology issues through the end of the roadmap. AIP Conf. Proc. 788, 203\u2013213 (2005). https:\/\/doi.org\/10.1063\/1.2062964","journal-title":"AIP Conf. Proc."},{"key":"3047_CR42","doi-asserted-by":"publisher","first-page":"1776","DOI":"10.1109\/TED.2024.3358251","volume":"71","author":"X Zhang","year":"2024","unstructured":"X. Zhang et al., Hybrid integration of gate-all-around stacked Si nanosheet FET and Si\/SiGe super-lattice FinFET to optimize 6T-SRAM for N3 node and beyond. IEEE Trans. Electron Devices 71, 1776\u20131783 (2024). https:\/\/doi.org\/10.1109\/TED.2024.3358251","journal-title":"IEEE Trans. Electron Devices"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-025-03047-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-025-03047-3","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-025-03047-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,2]],"date-time":"2026-02-02T01:26:21Z","timestamp":1769995581000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-025-03047-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,21]]},"references-count":42,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2026,1]]}},"alternative-id":["3047"],"URL":"https:\/\/doi.org\/10.1007\/s00034-025-03047-3","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,3,21]]},"assertion":[{"value":"25 November 2024","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"11 February 2025","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"12 February 2025","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"21 March 2025","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare that there is no financial and non financial interest associated with this publication.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Competing interests"}},{"value":"We declared that this manuscript entitled \u201cNovel Charge Plasma Vertically Stacked Dopingless Nanosheet Field-Effect Transistor (DL-NSFET): Proposal and Extensive Analysis\u201d by Abhishek Chauhan and Ashish Raman is original, has not been published before and is not currently being considered for publication.","order":3,"name":"Ethics","group":{"name":"EthicsHeading","label":"Ethics Approval"}}]}}