{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T16:39:18Z","timestamp":1775666358797,"version":"3.50.1"},"reference-count":43,"publisher":"Springer Science and Business Media LLC","issue":"7","license":[{"start":{"date-parts":[[2025,3,18]],"date-time":"2025-03-18T00:00:00Z","timestamp":1742256000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,3,18]],"date-time":"2025-03-18T00:00:00Z","timestamp":1742256000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62104001"],"award-info":[{"award-number":["62104001"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Science and Technology Key Project of Anhui Province","award":["2022AH050099"],"award-info":[{"award-number":["2022AH050099"]}]},{"name":"University Synergy Innovation Program of Anhui Province","award":["GXXT-2023-003"],"award-info":[{"award-number":["GXXT-2023-003"]}]},{"name":"University Synergy Innovation Program of Anhui Province","award":["GXXT-2023-013"],"award-info":[{"award-number":["GXXT-2023-013"]}]},{"name":"University Synergy Innovation Program of Anhui Province","award":["GXXT-2023-011"],"award-info":[{"award-number":["GXXT-2023-011"]}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2025,7]]},"DOI":"10.1007\/s00034-025-03052-6","type":"journal-article","created":{"date-parts":[[2025,3,18]],"date-time":"2025-03-18T18:21:27Z","timestamp":1742322087000},"page":"4607-4625","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["8T-SRAM Computing-in-Memory Macro with Bitline Leakage Compensation"],"prefix":"10.1007","volume":"44","author":[{"given":"Chunyu","family":"Peng","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Junbo","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mengyi","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wenjuan","family":"Lu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhiting","family":"Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Licai","family":"Hao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xin","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chenghu","family":"Dai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiulong","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2025,3,18]]},"reference":[{"issue":"5","key":"3052_CR1","doi-asserted-by":"publisher","first-page":"726","DOI":"10.1109\/4.918909","volume":"36","author":"K Agawa","year":"2001","unstructured":"K. Agawa, H. Hara, T. Takayanagi et al., A bitline leakage compensation scheme for low-voltage SRAMs. IEEE J. Solid-State Circuits 36(5), 726\u2013734 (2001)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"3052_CR2","doi-asserted-by":"crossref","unstructured":"A. Alvandpour, D. Somasekhar, R. Krishnamurthy, et al., Bitline leakage equalization for Sub-100nm caches, European Solid-State Circuits Conference, 2003:401\u2013404.","DOI":"10.1109\/ESSCIRC.2003.1257157"},{"issue":"8","key":"3052_CR3","doi-asserted-by":"publisher","first-page":"1208","DOI":"10.1109\/4.705359","volume":"33","author":"BS Amrutur","year":"1998","unstructured":"B.S. Amrutur, M.A. Horowitz, A replica technique for wordline and sense control in low-power SRAM\u2019s. IEEE J. Solid-State Circuits 33(8), 1208\u20131219 (1998)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"1","key":"3052_CR4","doi-asserted-by":"publisher","first-page":"217","DOI":"10.1109\/JSSC.2018.2880918","volume":"54","author":"A Biswas","year":"2019","unstructured":"A. Biswas, A.P. Chandrakasan, CONV-SRAM: an energy-efficient SRAM with in-memory dot-product computation for low-power Convo-Lutional neural networks. IEEE J. Solid-State Circuits 54(1), 217\u2013230 (2019)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"4","key":"3052_CR5","doi-asserted-by":"publisher","first-page":"1520","DOI":"10.1109\/TCSI.2021.3054972","volume":"68","author":"J Chen","year":"2021","unstructured":"J. Chen, W. Zhao, Y. Wang et al., Analysis and optimization strategies toward reliable and high-speed 6T compute SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 68(4), 1520\u20131531 (2021)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"issue":"6","key":"3052_CR6","doi-asserted-by":"publisher","first-page":"769","DOI":"10.1109\/TVLSI.2022.3164756","volume":"30","author":"J Chen","year":"2022","unstructured":"J. Chen, W. Zhao, Y. Wang et al., A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations. IEEE Trans. Very Large Scale Integr. (VLSI) Syst, 30(6), 769\u2013780 (2022)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst,"},{"key":"3052_CR7","doi-asserted-by":"crossref","unstructured":"Y.D. Chih, P.H. Lee, H. Fujiwara, et al., 16.4 an 89TOPS\/W and 16.3TOPS\/mm2 all-digital SRAM-based full-precision compute-in memory macro in 22nm for machine-learning edge applications, in IEEE International Solid-State Circuits Conference-(ISSCC) (2021), pp. 252\u2013254.","DOI":"10.1109\/ISSCC42613.2021.9365766"},{"key":"3052_CR8","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2023.105699","volume":"132","author":"CH Dai","year":"2023","unstructured":"C.H. Dai, Y.Y. Du, Q. Shi et al., Bit-line leakage current tracking and self-compensation circuit for SRAM reliability design. Microelectron. J. 132, 105699 (2023)","journal-title":"Microelectron. J."},{"issue":"4","key":"3052_CR9","doi-asserted-by":"publisher","first-page":"1006","DOI":"10.1109\/JSSC.2017.2776309","volume":"53","author":"Q Dong","year":"2018","unstructured":"Q. Dong, S. Jeloka, M. Saligane et al., A 4+2T SRAM for searching and in-memory computing with 03-V VDDmin. IEEE J. Solid-State Circuits 53(4), 1006\u20131015 (2018)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"3052_CR10","doi-asserted-by":"crossref","unstructured":"S. Huang, H. Jiang, X. Peng, et al., XOR-CIM: compute-in-memory SRAM architecture with embedded XOR encryption, Proceedings of the 39th International Conference on Computer-Aided Design (2020), pp. 1\u20136.","DOI":"10.1145\/3400302.3415678"},{"key":"3052_CR11","doi-asserted-by":"publisher","first-page":"2981","DOI":"10.1109\/JSSC.2021.3092759","volume":"56","author":"S Jain","year":"2021","unstructured":"S. Jain, L. Lin, M. Alioto, \u00b1CIM SRAM for signed in-memory broad-purpose computing from DSP to neural processing. IEEE J. Solid-State Circuits 56, 2981\u20132992 (2021)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"11","key":"3052_CR12","doi-asserted-by":"publisher","first-page":"2556","DOI":"10.1109\/TVLSI.2019.2929245","volume":"27","author":"A Jaiswal","year":"2019","unstructured":"A. Jaiswal, I. Chakraborty, A. Agrawal et al., 8T SRAM cell as a multibit dot-product engine for beyond Von Neumann computing. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 27(11), 2556\u20132567 (2019)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"3052_CR13","doi-asserted-by":"crossref","unstructured":"S. Jeloka, N. Akesh, D. Sylvester, et al., A configurable TCAM\/BCAM\/SRAM using 28nm push-rule 6T Bit cell, in IEEE Symposia on VLSI Technology and Circuits (2015), pp. C272\u2013C273.","DOI":"10.1109\/VLSIC.2015.7231285"},{"key":"3052_CR14","doi-asserted-by":"crossref","unstructured":"Z. Jiang, S. Yin, M. Seok, et al., XNOR-SRAM: in-memory computing SRAM macro for binary\/ternary deep neural networks, in IEEE Symposia on VLSI Technology and Circuits (2018) pp. 173\u2013174.","DOI":"10.1109\/VLSIT.2018.8510687"},{"key":"3052_CR15","doi-asserted-by":"crossref","unstructured":"H. Jiang, R. Liu, S. Yu, 8T XNOR-SRAM based parallel compute-in-memory for deep neural network accelerator, in International Midwest Symposium on Circuits and Systems (MWSCAS) (2020), pp. 257\u2013260.","DOI":"10.1109\/MWSCAS48704.2020.9184455"},{"issue":"7","key":"3052_CR16","doi-asserted-by":"publisher","first-page":"1888","DOI":"10.1109\/JSSC.2020.2992886","volume":"55","author":"Z Jiang","year":"2020","unstructured":"Z. Jiang, S. Yin, J.S. Seo et al., C3SRAM: an in-memory-computing SRAM macro based on robust capacitive coupling computing mechanism. IEEE J. Solid-State Circuits 55(7), 1888\u20131897 (2020)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"3052_CR17","doi-asserted-by":"crossref","unstructured":"M. Kang, S.K. Gonugondla, N.R. Shanbhag, A 19.4 nJ\/decision 364K decisions\/s in-memory random forest classifier in 6T SRAM Array, in ESSCIRC 2017\u201343rd IEEE European Solid State Circuits Conference (2017), pp. 263\u2013266.","DOI":"10.1109\/ESSCIRC.2017.8094576"},{"issue":"4","key":"3052_CR18","doi-asserted-by":"publisher","first-page":"855","DOI":"10.1109\/TBCAS.2016.2545402","volume":"10","author":"M Kang","year":"2016","unstructured":"M. Kang, N.R. Shanbhag, In-memory computing architectures for sparse distributed memory. IEEE Trans. Biomed. Circuits Syst. 10(4), 855\u2013863 (2016)","journal-title":"IEEE Trans. Biomed. Circuits Syst."},{"key":"3052_CR19","doi-asserted-by":"crossref","unstructured":"W.S. Khwa, J.J. Chen, J.F. Li, et al., A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8TOPS\/W fully parallel product-sum operation for binary DNN edge processors, in IEEE International Solid-State Circuits Conference-(ISSCC) (2018), pp. 496\u2013498.","DOI":"10.1109\/ISSCC.2018.8310401"},{"key":"3052_CR20","doi-asserted-by":"crossref","unstructured":"J. Kim, J. Koo, T. Kim, et al., Area-efficient and variation-tolerant in-memory BNN computing using 6T SRAM array, in IEEE Symposia on VLSI Technology and Circuits, (2019), pp. C118\u2013C119","DOI":"10.23919\/VLSIC.2019.8778160"},{"key":"3052_CR21","doi-asserted-by":"crossref","unstructured":"J. Koo, E. Kim, S. Yoo, et al., Configurable BCAM\/TCAM based on 6T SRAM bit cell and enhanced match line clamping, in IEEE Asian Solid-State Circuits Conference (A-SSCC) (2019), pp. 223\u2013226","DOI":"10.1109\/A-SSCC47793.2019.9056974"},{"issue":"9","key":"3052_CR22","doi-asserted-by":"publisher","first-page":"1964","DOI":"10.1109\/JSSC.2008.2001937","volume":"43","author":"YC Lai","year":"2008","unstructured":"Y.C. Lai, S.Y. Huang, X-calibration: a technique for combating excessive bitline leakage current in nanometer SRAM designs. IEEE J. Solid-State Circuits 43(9), 1964\u20131971 (2008)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"3052_CR23","doi-asserted-by":"publisher","first-page":"70214","DOI":"10.1109\/ACCESS.2021.3078531","volume":"9","author":"JS Lee","year":"2021","unstructured":"J.S. Lee, W.Y. Choi, Nanoelectromechanical-switch-based binary content-addressable memory (NEMBCAM). IEEE Access 9, 70214\u201370220 (2021)","journal-title":"IEEE Access"},{"key":"3052_CR24","doi-asserted-by":"crossref","unstructured":"R.X. Li, N. Bai, B.T. Lv, et al., Bitline leakage current compensation circuit for high-performance SRAM design, in IEEE Seventh International Conference on Networking, Architecture, and Storage (2012) pp. 109\u2013113","DOI":"10.1109\/NAS.2012.19"},{"key":"3052_CR25","doi-asserted-by":"crossref","unstructured":"R. Liu, X. Peng, X. Sun, et al., Parallelizing SRAM arrays with customized bit-cell for binary neural networks, in Proceedings of the 55th annual design automation conference (2018), pp. 1\u20136","DOI":"10.1145\/3195970.3196089"},{"issue":"5","key":"3052_CR26","doi-asserted-by":"publisher","first-page":"604","DOI":"10.1109\/TVLSI.2008.2006040","volume":"17","author":"N Mohan","year":"2009","unstructured":"N. Mohan, M. Sachdev, Low-leakage storage cells for ternary content addressable memories. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17(5), 604\u2013612 (2009)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"3052_CR27","doi-asserted-by":"crossref","unstructured":"C.Y. Peng, W. Hu, H. Zheng, et al., Real\u2013time bit\u2013line leakage balance circuit with four-input low-offset SA considering threshold voltage for SRAM stability design, Int. J. Circuit Theory Appl. 2024:cta.4248","DOI":"10.1002\/cta.4248"},{"key":"3052_CR28","doi-asserted-by":"crossref","unstructured":"A.K. Rajput, M. Pattanaik. Implementation of boolean and arithmetic functions with 8T SRAM cell for in-memory computation, in International Conference for Emerging Technology (INCET), (2020), pp. 1\u20135.","DOI":"10.1109\/INCET49848.2020.9154137"},{"key":"3052_CR29","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2022.105569","volume":"129","author":"AK Rajput","year":"2022","unstructured":"A.K. Rajput, M. Pattanaik, G. Kaushal, Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable in-memory computing architecture. Microelectron. J. 129, 105569 (2022)","journal-title":"Microelectron. J."},{"issue":"6","key":"3052_CR30","doi-asserted-by":"publisher","first-page":"861","DOI":"10.1109\/4.585288","volume":"32","author":"S Shigematsu","year":"1997","unstructured":"S. Shigematsu, S. Mutoh, Y. Matsuya et al., A 1-V high-speed MTCMOS circuit scheme for power-down application circuits. IEEE J. Solid-State Circuits 32(6), 861\u2013869 (1997)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"3052_CR31","doi-asserted-by":"crossref","unstructured":"N.K. Shukla, D. Mukherjee, S. Birla, et al., Leakage current minimization in deep-submicron conventional single cell SRAM, in International Conference on Recent Trends in Information, Telecommunication and Computing, (2010) pp. 381\u2013383","DOI":"10.1109\/ITC.2010.9"},{"issue":"11","key":"3052_CR32","doi-asserted-by":"publisher","first-page":"4172","DOI":"10.1109\/TCSI.2019.2928043","volume":"66","author":"X Si","year":"2019","unstructured":"X. Si, W.S. Khwa, J.J. Chen et al., A dual-split 6T SRAM-based computing-in-memory unit-macro with fully parallel product-sum operation for binarized DNN edge processors. IEEE Trans. Circuits Syst. I Regul. Pap. 66(11), 4172\u20134185 (2019)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"3052_CR33","doi-asserted-by":"crossref","unstructured":"X. Si, J.J. Chen, Y.N. Tu, et al., A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning, in IEEE international solid-state circuits conference-(ISSCC), (2019), pp. 396\u2013398","DOI":"10.1109\/ISSCC.2019.8662392"},{"key":"3052_CR34","doi-asserted-by":"crossref","unstructured":"J. Song, Y. Wang, X. Tang, et al., A 16Kb Transpose 6T SRAM in-memory-computing macro based on robust charge-domain computing, in IEEE Asian solid-state circuits conference (A-SSCC) (2021), pp. 1\u20133","DOI":"10.1109\/A-SSCC53895.2021.9634747"},{"key":"3052_CR35","doi-asserted-by":"crossref","unstructured":"X. Sun, R. Liu, X. Peng, et al., Computing-in-memory with SRAM and RRAM for binary neural networks, in IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) (2018), pp. 1\u20134.","DOI":"10.1109\/ICSICT.2018.8565811"},{"key":"3052_CR36","doi-asserted-by":"crossref","unstructured":"H. Valavi, P.J. Ramadge, E. Nestler, et al., A mixed-signal binarized convolutional-neural-network accelerator integrating dense weight storage and multiplication for reduced data movement, in IEEE Symposia on VLSI Technology and Circuits (2018), pp. 141\u2013142","DOI":"10.1109\/VLSIC.2018.8502421"},{"key":"3052_CR37","doi-asserted-by":"crossref","unstructured":"Y. Wang, H. Yu, D. Sylvester, et al., Energy efficient in-memory AES encryption based on Nonvolatile domain-wall nanowire, in Automation & Test in Europe Conference & Exhibition (DATE), (2014) (pp. 1\u20134).","DOI":"10.7873\/DATE2014.196"},{"key":"3052_CR38","doi-asserted-by":"crossref","unstructured":"Y. Wang, J. Chen, Y. Pu, et al., Energy-efficient arbitrary precision multi-bit multiplication with Bi-serial in\/near memory computing, in IEEE International Symposium on Circuits and Systems (ISCAS), (2020), pp. 1\u20135.","DOI":"10.1109\/ISCAS45731.2020.9180876"},{"key":"3052_CR39","unstructured":"P.C. Wu, J.W. Su, Y.L. Chung, et al., A 28\u00a0nm 1Mb time-domain computing-in-memory 6T-SRAM macro with a 6.6ns latency, 1241GOPS and 37.01TOPS\/W for 8b-MAC operations for edge-AI devices, in IEEE International Solid-State Circuits Conference (ISSCC), (2022) pp. 1\u20133"},{"issue":"11","key":"3052_CR40","doi-asserted-by":"publisher","first-page":"3466","DOI":"10.1109\/JSSC.2022.3162602","volume":"57","author":"C Yu","year":"2022","unstructured":"C. Yu, T. Yoo, K.T.C. Chai et al., A 65-nm 8T SRAM compute-in-memory macro with column ADCs for processing neural networks. IEEE J. Solid-State Circuits 57(11), 3466\u20133476 (2022)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"3052_CR41","unstructured":"C.S. Yu, T. Yoo, T.T. Kim, et al., A 16K current-based 8T SRAM compute-in-memory macro with decoupled read\/write and 1-5bit column ADC, in 2020 IEEE Custom Integrated Circuits Conference (CICC), (2020), pp. 1-4"},{"key":"3052_CR42","doi-asserted-by":"crossref","unstructured":"J.T. Zhang, Z. Wang, N. Verma. A machine-learning classifier implemented in a standard 6T SRAM Array, IEEE Symposia on VLSI Technology and Circuits (2016) pp.1\u20132.","DOI":"10.1109\/VLSIC.2016.7573556"},{"issue":"4","key":"3052_CR43","doi-asserted-by":"publisher","first-page":"915","DOI":"10.1109\/JSSC.2016.2642198","volume":"52","author":"J Zhang","year":"2017","unstructured":"J. Zhang, Z. Wang, N. Verma, In-memory computation of a machine-learning classifier in a standard 6T SRAM array. IEEE J. Solid-State Circuits 52(4), 915\u2013924 (2017)","journal-title":"IEEE J. Solid-State Circuits"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-025-03052-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-025-03052-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-025-03052-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T21:02:29Z","timestamp":1751403749000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-025-03052-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,18]]},"references-count":43,"journal-issue":{"issue":"7","published-print":{"date-parts":[[2025,7]]}},"alternative-id":["3052"],"URL":"https:\/\/doi.org\/10.1007\/s00034-025-03052-6","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,3,18]]},"assertion":[{"value":"12 November 2024","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"13 February 2025","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"14 February 2025","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"18 March 2025","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors have no conflict of interest to declare.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}]}}