{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,2]],"date-time":"2026-02-02T10:23:49Z","timestamp":1770027829789,"version":"3.49.0"},"reference-count":34,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2025,5,3]],"date-time":"2025-05-03T00:00:00Z","timestamp":1746230400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,5,3]],"date-time":"2025-05-03T00:00:00Z","timestamp":1746230400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2026,1]]},"DOI":"10.1007\/s00034-025-03117-6","type":"journal-article","created":{"date-parts":[[2025,5,3]],"date-time":"2025-05-03T15:20:41Z","timestamp":1746285641000},"page":"535-556","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["An Approach of ISI Elimination and High-Speed Data Reconstruction in Lossy On-Chip Serial Link"],"prefix":"10.1007","volume":"45","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8201-0314","authenticated-orcid":false,"given":"Anirban","family":"Tarafdar","sequence":"first","affiliation":[]},{"given":"Alak","family":"Majumder","sequence":"additional","affiliation":[]},{"given":"Biman","family":"Debbarma","sequence":"additional","affiliation":[]},{"given":"Bidyut K.","family":"Bhattacharyya","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2025,5,3]]},"reference":[{"issue":"12","key":"3117_CR1","doi-asserted-by":"publisher","first-page":"3220","DOI":"10.1109\/JSSC.2012.2216412","volume":"47","author":"A Agrawal","year":"2012","unstructured":"A. Agrawal, J.F. Bulzacchelli, T.O. Dickson, Y. Liu, J.A. Tierno, D.J. Friedman, A 19-Gb\/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45-nm SOI CMOS. IEEE j. solid-state circuits 47(12), 3220\u20133231 (2012)","journal-title":"IEEE j. solid-state circuits"},{"issue":"12","key":"3117_CR2","doi-asserted-by":"publisher","first-page":"2633","DOI":"10.1109\/JSSC.2005.856584","volume":"40","author":"T Beukema","year":"2005","unstructured":"T. Beukema, M. Sorna, K. Selander, S. Zier, B.L. Ji, P. Murfet, J. Mason, W. Rhee, H. Ainspan, B. Parker, M. Beakes, A 6.4-Gb\/s CMOS SerDes core with feed-forward and decision-feedback equalization. IEEE J. solid-state circuits 40(12), 2633\u20132645 (2005)","journal-title":"IEEE J. solid-state circuits"},{"key":"3117_CR3","doi-asserted-by":"crossref","unstructured":"B. K. Bhattacharyya, S. Bhattacharya, Comparison of the output voltage at the receiving end of the lossy transmission line due to the equalized pulse and sinusoidal input voltage. Proceedings Electronic Components and Technology. ECTC\u201905. (pp. 1752\u20131755). IEEE, (2005)","DOI":"10.1109\/ECTC.2005.1442031"},{"key":"3117_CR4","doi-asserted-by":"crossref","unstructured":"M. Bichan, C. Ting, B. Zand, J. Wang, R. Shulyzki, J. Guthrie, K. Tyshchenko, J. Zhao, A. parsafar, E. Liu, A. Vatankhahghadim, S. Sharifian, A. Tyshchenko, M. D. Vita, S. Rubab, S. Iyer, F. Spagna, N. Dolev, A 32Gb\/s NRZ 37dB SerDes in 10nm CMOS to support PCI express gen 5 protocol.\u00a02020 IEEE Custom Integrated Circuits Conference (CICC)\u00a0(pp. 1\u20134). IEEE (2020)","DOI":"10.1109\/CICC48029.2020.9075947"},{"issue":"4","key":"3117_CR5","doi-asserted-by":"publisher","first-page":"23","DOI":"10.1109\/MSSC.2015.2475996","volume":"7","author":"JF Bulzacchelli","year":"2015","unstructured":"J.F. Bulzacchelli, Equalization for electrical links: current design techniques and future directions. IEEE Solid-State Circuits Mag. 7(4), 23\u201331 (2015)","journal-title":"IEEE Solid-State Circuits Mag."},{"issue":"1","key":"3117_CR6","doi-asserted-by":"publisher","first-page":"318","DOI":"10.1007\/s00034-023-02473-5","volume":"43","author":"Y Chen","year":"2024","unstructured":"Y. Chen, Y. Chen, W. Fan, Q. Zhao, E. Zhu, Z. Hu, A 2\u201320 Gbps clock and data recovery based on phase interpolation and delay locked loop. Circuits Syst. Signal Process. 43(1), 318\u2013330 (2024)","journal-title":"Circuits Syst. Signal Process."},{"issue":"4","key":"3117_CR7","doi-asserted-by":"publisher","first-page":"1203","DOI":"10.1109\/JSSC.2017.2774276","volume":"53","author":"P-W Chiu","year":"2018","unstructured":"P.-W. Chiu, S. Kundu, Q. Tang, C.H. Kim, A 65-nm 10-Gb\/s 10-mm on-chip serial link featuring a digital-intensive time-based decision feedback equalizer. IEEE J. solid-state circuits 53(4), 1203\u20131213 (2018)","journal-title":"IEEE J. solid-state circuits"},{"issue":"2","key":"3117_CR8","doi-asserted-by":"publisher","first-page":"940","DOI":"10.1109\/TCSI.2022.3226320","volume":"70","author":"A Cortiula","year":"2022","unstructured":"A. Cortiula, D. Menin, A. Bandiziol, W. Grollitsch, R. Nonis, R.P. Palestri, A time-domain simulation framework for the modeling of jitter in high-speed serial interfaces. IEEE Trans. Circuits Syst. I Regular Papers 70(2), 940\u2013951 (2022)","journal-title":"IEEE Trans. Circuits Syst. I Regular Papers"},{"key":"3117_CR9","doi-asserted-by":"crossref","unstructured":"A. Cortiula, M. Dazzi, M. Marcon, D. Menin, M. Scapol, A. Bandiziol, A. Cristofoli, W. Grollitsch, R. nonis, P. Palestri, A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces. 42nd International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO)\u00a0(pp. 112\u2013116). IEEE (2019)","DOI":"10.23919\/MIPRO.2019.8756752"},{"key":"3117_CR10","doi-asserted-by":"crossref","unstructured":"N. Dikhaminjia, M. Tsiklauri, Z. Kiguradze, J. He, J. Drewniak, A. Chada, B. Mutnury, Combined optimization of FFE and DFE equalizations. In\u00a02018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)\u00a0(pp. 21\u201323). IEEE (2018)","DOI":"10.1109\/EPEPS.2018.8534279"},{"issue":"1","key":"3117_CR11","doi-asserted-by":"publisher","first-page":"52","DOI":"10.1109\/JSSC.2007.910807","volume":"43","author":"R Ho","year":"2008","unstructured":"R. Ho, T. Ono, R.D. Hopkins, A. Chow, J. Schauer, F.Y. Liu, R. Drost, High speed and low energy capacitively driven on-chip wires. IEEE j. solid-state circuits 43(1), 52\u201360 (2008)","journal-title":"IEEE j. solid-state circuits"},{"issue":"11","key":"3117_CR12","doi-asserted-by":"publisher","first-page":"1768","DOI":"10.3390\/electronics11111768","volume":"11","author":"Y Huang","year":"2022","unstructured":"Y. Huang, H. Yang, W. Chen, Z. Yang, S. Qiao, An 8-Gbps, low-jitter, four-channel transmitter with a fractional-spaced feed-forward equalizer. Electronics 11(11), 1768 (2022)","journal-title":"Electronics"},{"issue":"12","key":"3117_CR13","doi-asserted-by":"publisher","first-page":"8110","DOI":"10.1109\/TWC.2021.3090221","volume":"20","author":"N Iqbal","year":"2021","unstructured":"N. Iqbal, A. Zerguine, S. Alouini, A robust frequency domain decision feedback equalization system for uplink SC-FDMA systems. IEEE Trans. Wirel. Commun.Wirel. Commun. 20(12), 8110\u20138118 (2021)","journal-title":"IEEE Trans. Wirel. Commun.Wirel. Commun."},{"key":"3117_CR14","doi-asserted-by":"crossref","unstructured":"S. Y. Kao, S. I. Liu, A 7.5-Gb\/s one-tap-FFE transmitter with adaptive far-end crosstalk cancellation using duty cycle detection.\u00a0IEEE j. solid-state circuits,\u00a048(2), 391\u2013404 (2012)","DOI":"10.1109\/JSSC.2012.2227604"},{"key":"3117_CR15","unstructured":"B. Kim, V. Stojanovi\u0107, A 4Gb\/s\/ch 356 fJ\/b 10nm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm CMOS. ISSCC Dig. Tech. Papers., pp. 412\u2013413 (2007)"},{"issue":"8","key":"3117_CR16","doi-asserted-by":"publisher","first-page":"1875","DOI":"10.1109\/JSSC.2013.2259033","volume":"48","author":"N Kocaman","year":"2013","unstructured":"N. Kocaman, S. Fallahi, M. Kargar, M. Khanpour, A. Nazemi, U. Singh, A. Momtaz, An 8.5\u201311.5-Gbps SONET transceiver with referenceless frequency acquisition. IEEE J. Solid-State Circuits 48(8), 1875\u20131884 (2013)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"3117_CR17","doi-asserted-by":"crossref","unstructured":"S. M. Lee, J. Lim, J. Jang, H. Kim, K. Min, W. Min, H. Han, G. Kim, J. Kim, C. Kim, S. Jeon, J. Park, H. Chae, S. Han, H. Pham, X. Zhao, Q. Gu, C. W. Yao, S. Kim, J. Lee, A 64Gb\/s downlink and 32Gb\/s uplink NRZ wireline transceiver with supply regulation, background clock correction and EOM-based channel adaptation for mid-reach cellular mobile interface in 8nm FinFET. ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC) (pp. 509\u2013512). IEEE (2022)","DOI":"10.1109\/ESSCIRC55480.2022.9911419"},{"issue":"2","key":"3117_CR18","doi-asserted-by":"publisher","first-page":"109","DOI":"10.23919\/ICS.2024.3423852","volume":"1","author":"S Li","year":"2024","unstructured":"S. Li, R. Ma, M. Deng, J. Xue, W. Deng, B. Chi, H. Jia, A 312.5 Mbps-32 Gbps JESD204C wireline transceiver back-compatible with JESD204B in 28 nm CMOS. Integrated Circuits Syst. 1(2), 109\u2013118 (2024). https:\/\/doi.org\/10.23919\/ICS.2024.3423852","journal-title":"Integrated Circuits Syst."},{"key":"3117_CR19","doi-asserted-by":"crossref","unstructured":"M. Meghelli, S. Rylov, J. Bulzacchelli, W. Rhee, A. Rylyakov, H. Ainspan, B. Parker, M. Beakes, A. Chung, T. Beukema, P. pepelijugoski, L. Shan, Y. kwark, S. Gowda, D. Friedman, A 10Gb\/s 5-Tap-DFE\/4-Tap-FFE Transceiver in 90nm CMOS.\u00a02006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, pp. 213\u2013222 (2006)","DOI":"10.1109\/ISSCC.2006.1696051"},{"key":"3117_CR20","doi-asserted-by":"crossref","unstructured":"H. Park, Y. Choi, J. Sim, J. Choi, Y. Kwon, J. Song, C. Kim, A 0.385-pJ\/bit 10-Gb\/s TIA-terminated di-code transceiver with edge-delayed equalization, ECC, and mismatch calibration for HBM interfaces.\u00a02022 IEEE International Solid-State Circuits Conference (ISSCC) (pp. 1\u20133). IEEE (2022).","DOI":"10.1109\/ISSCC42614.2022.9731740"},{"key":"3117_CR21","first-page":"119","volume":"3","author":"J Poirrier","year":"2000","unstructured":"J. Poirrier, A. Gnauck, J. Winters, Experimental nonlinear cancellation of polarization-mode dispersion. Optical Fiber Commun. Conf. 3, 119\u2013121 (2000)","journal-title":"Optical Fiber Commun. Conf."},{"key":"3117_CR22","doi-asserted-by":"crossref","unstructured":"H. G. Rhew, M. P. Flynn and J. Park, A 22Gb\/s, 10mm on-chip serial link over lossy transmission line with resistive termination. Proceedings of the ESSCIRC (ESSCIRC), pp. 233\u2013236 (2012).","DOI":"10.1109\/ESSCIRC.2012.6341301"},{"issue":"2","key":"3117_CR23","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1007\/s11082-025-08055-w","volume":"57","author":"S Sarita","year":"2025","unstructured":"S. Sarita, N. Sharma, S. Agrawal, S. Budhiraja, Analysis and performance improvement of 60 GHz mm-wave based hybrid RoF and RoFSO system under atmospheric turbulence using FFE+ DFE electronic equalizer. Opt. Quant. Electron. 57(2), 1\u201341 (2025)","journal-title":"Opt. Quant. Electron."},{"key":"3117_CR24","doi-asserted-by":"crossref","unstructured":"A. M. Sawaby; A. M. Elshorbge, O. T. Abdelhalim, M. A. Farghaly, Md S. Taha, Y. H. Yehia, A 10 Gb\/s SerDes Transceiver. 3rd Novel Intelligent and Leading Emerging Sciences Conference (NILES), 2021, pp. 389\u2013393, (2021)","DOI":"10.1109\/NILES53778.2021.9600520"},{"key":"3117_CR25","doi-asserted-by":"crossref","unstructured":"J. S. Seo, R. Ho, J. Lexau, M. Dayringer, D. Sylvester, D. Blaauw, High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS. In 2010 IEEE International Solid-State Circuits Conference-(ISSCC) (pp. 182\u2013183). IEEE (2010)","DOI":"10.1109\/ISSCC.2010.5433993"},{"issue":"2","key":"3117_CR26","first-page":"428","volume":"51","author":"G Shu","year":"2015","unstructured":"G. Shu, W.S. Choi, S. Saxena, M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, P.K. Hanumolu, A 4-to-10.5 Gb\/s continuous-rate digital clock and data recovery with automatic frequency acquisition. IEEE J. Solid-State Circuits 51(2), 428\u2013439 (2015)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"2","key":"3117_CR27","first-page":"404","volume":"69","author":"J Sim","year":"2021","unstructured":"J. Sim, Y. Lee, H. Park, Y. Choi, J. Choi, C. Kim, A 25 Gb\/s wireline receiver with feedforward and feedback equalizers at analog front-end. IEEE Trans. Circuits Syst. II Express Briefs 69(2), 404\u2013408 (2021)","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"issue":"3","key":"3117_CR28","doi-asserted-by":"publisher","first-page":"1980","DOI":"10.1007\/s00034-023-02553-6","volume":"43","author":"JT Wang","year":"2024","unstructured":"J.T. Wang, Sequence detection with variable sampling rate and block length under ISI channels. Circuits Syst. Signal Process 43(3), 1980\u20131992 (2024)","journal-title":"Circuits Syst. Signal Process"},{"issue":"1","key":"3117_CR29","first-page":"52","volume":"31","author":"T Wang","year":"2022","unstructured":"T. Wang, J. Zou, H. Qi, X. Wang, J. Wang, H. Zhang, A programmable pre-emphasis technique with combined rlc source degeneration for high-speed serial link transmitters[J]. Chinese J. of Electronics 31(1), 52\u201358 (2022)","journal-title":"Chinese J. of Electronics"},{"issue":"1","key":"3117_CR30","doi-asserted-by":"publisher","first-page":"31760","DOI":"10.1038\/srep31760","volume":"6","author":"Y Wu","year":"2016","unstructured":"Y. Wu, M. Qu, Y. Liu, A generalized lossy transmission-line model for tunable graphene-based transmission lines with attenuation phenomenon. Sci. Rep. 6(1), 31760 (2016)","journal-title":"Sci. Rep."},{"key":"3117_CR31","doi-asserted-by":"crossref","unstructured":"J. H. Yoon, K. Kwon, H. M. Bae, 3.125-to-28.125 Gb\/s 4.72 mW\/Gb\/s multi-standard parallel transceiver supporting channel-independent operation in 40-nm CMOS. IEEE Trans. on Circuits and Systems I: Regular Papers, 67(8), 2647-2658 (2020)","DOI":"10.1109\/TCSI.2020.2980139"},{"issue":"11","key":"3117_CR32","doi-asserted-by":"publisher","first-page":"420","DOI":"10.1049\/ell2.12494","volume":"58","author":"K Yoon","year":"2022","unstructured":"K. Yoon, H. Park, Y. Choi, J. Sim, J. Choi, C. Kim, A 4.5 Gb\/s\/pin transceiver with hybrid inter-symbol interference and far-end crosstalk equalization for next-generation high-bandwidth memory interface. Electron. Lett. 58(11), 420\u2013422 (2022)","journal-title":"Electron. Lett."},{"issue":"10","key":"3117_CR33","doi-asserted-by":"publisher","first-page":"6537","DOI":"10.1007\/s00034-024-02755-6","volume":"43","author":"X Zhang","year":"2024","unstructured":"X. Zhang, L. Lei, D. Feng, J. Wu, Robust equalizer based on new lower-order statistic under impulsive noise cases. Circuits Syst. Signal Process. 43(10), 6537\u20136552 (2024)","journal-title":"Circuits Syst. Signal Process."},{"issue":"3","key":"3117_CR34","doi-asserted-by":"publisher","first-page":"20220527","DOI":"10.1587\/elex.19.20220527","volume":"20","author":"K Zhu","year":"2023","unstructured":"K. Zhu, S. Li, G. Chu, A 25Gb\/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology. IEICE Electron. Express 20(3), 20220527\u201320220527 (2023)","journal-title":"IEICE Electron. Express"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-025-03117-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-025-03117-6","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-025-03117-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,2]],"date-time":"2026-02-02T01:26:18Z","timestamp":1769995578000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-025-03117-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5,3]]},"references-count":34,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2026,1]]}},"alternative-id":["3117"],"URL":"https:\/\/doi.org\/10.1007\/s00034-025-03117-6","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,5,3]]},"assertion":[{"value":"24 September 2024","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"27 March 2025","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"27 March 2025","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"3 May 2025","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors affirm that they have no known financial or interpersonal conflicts that would have appeared to have an impact on the research presented in this study.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}]}}