{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T16:32:41Z","timestamp":1694622761038},"reference-count":18,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2004,4,1]],"date-time":"2004-04-01T00:00:00Z","timestamp":1080777600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Form. Asp. Comput."],"published-print":{"date-parts":[[2004,4]]},"abstract":"<jats:title>Abstract.<\/jats:title>\n          <jats:p>This paper details a new object-oriented methodology that permits a unified modelling language (UML) behavioural representation of analogue circuits at system level. The proposed method demonstrates a novel approach to the problem of behavioural representation of an analogue topology, by constructing a consistent set of rules for automated mapping of the UML model to a VHDL-AMS specification. The VHDL-AMS specification enables behavioural simulation of the UML model and the methodology is validated using an analogue subsystem level application.<\/jats:p>","DOI":"10.1007\/s00165-003-0027-0","type":"journal-article","created":{"date-parts":[[2004,3,29]],"date-time":"2004-03-29T12:36:13Z","timestamp":1080563773000},"page":"80-94","source":"Crossref","is-referenced-by-count":2,"title":["Integration of UML and VHDL-AMS for analogue system modelling"],"prefix":"10.1145","volume":"16","author":[{"given":"C. T.","family":"Carr","sequence":"first","affiliation":[{"name":"Intelligent Systems Engineering Laboratory, University of Ulster, Northern Ireland, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T. 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