{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T04:29:06Z","timestamp":1648960146261},"reference-count":38,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2014,4,29]],"date-time":"2014-04-29T00:00:00Z","timestamp":1398729600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Distrib. Comput."],"published-print":{"date-parts":[[2015,4]]},"DOI":"10.1007\/s00446-014-0215-6","type":"journal-article","created":{"date-parts":[[2014,4,28]],"date-time":"2014-04-28T19:26:21Z","timestamp":1398713181000},"page":"75-90","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Soft-error mitigation by means of decoupled transactional memory threads"],"prefix":"10.1007","volume":"28","author":[{"given":"Daniel","family":"S\u00e1nchez","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Juan M.","family":"Cebri\u00e1n","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jos\u00e9 M.","family":"Garc\u00eda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Juan L.","family":"Arag\u00f3n","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2014,4,29]]},"reference":[{"key":"215_CR1","doi-asserted-by":"crossref","unstructured":"Agarwal, R., Garg, P., Torrellas, J.: Rebound: scalable checkpointing for coherent shared memory. In: Proceeding of the 38th Annual International Symposium on Computer Architecture, ISCA \u201911, pp. 153\u2013164. ACM, New York (2011)","DOI":"10.1145\/2000064.2000083"},{"key":"215_CR2","doi-asserted-by":"crossref","unstructured":"Bartlett, J., Gray, J., Horst, B.: Fault tolerance in tandem computer systems. In: The Evolution of Fault-Tolerant Systems (1987)","DOI":"10.1007\/978-3-7091-8871-2_3"},{"key":"215_CR3","doi-asserted-by":"crossref","unstructured":"Bernick, D., Bruckert, B., Vigna, P. D., Garcia, D., Jardine, R., Klecka, J., Smullen, J.: Nonstop advanced architecture. In: Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN\u201905), pp. 12\u201321. Yokohama, Japan (2005)","DOI":"10.1109\/DSN.2005.70"},{"key":"215_CR4","doi-asserted-by":"crossref","unstructured":"Bienia, C., Kumar, S., Singh, J.P., Li, K.: The parsec benchmark suite: characterization and architectural implications. In: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, pp. 72\u201381 (2008)","DOI":"10.1145\/1454115.1454128"},{"issue":"4","key":"215_CR5","doi-asserted-by":"crossref","first-page":"23","DOI":"10.1109\/40.782564","volume":"19","author":"S Borkar","year":"1999","unstructured":"Borkar, S.: Design challenges of technology scaling. IEEE Micro 19(4), 23\u201329 (1999)","journal-title":"IEEE Micro"},{"key":"215_CR6","doi-asserted-by":"crossref","unstructured":"Borkar, S., Karnik, T., Narendra, S., Tschanz, J., Keshavarzi, A., De, V.: Parameter variations and impact on circuits and microarchitecture. In: DAC \u201903: Proceedings of the 40th Annual Design Automation Conference, pp. 338\u2013342, ACM, New York (2003)","DOI":"10.1145\/775832.775920"},{"key":"215_CR7","doi-asserted-by":"crossref","unstructured":"Bowman, K., Tschanz, J., Wilkerson, C., Lu, S.-L., Karnik, T., De, V., Borkar, S.: Circuit techniques for dynamic variation tolerance. In: DAC \u201909: Proceedings of the 46th Annual Design Automation Conference, pp. 4\u20137. ACM, NY (2009)","DOI":"10.1145\/1629911.1629915"},{"key":"215_CR8","unstructured":"Censier, L.M., Feautrier, P.: Readings in computer architecture. chapter a new solution to coherence problems in multicache systems, pp. 576\u2013582. Morgan Kaufmann Publishers Inc., San Francisco (2000)"},{"key":"215_CR9","doi-asserted-by":"crossref","unstructured":"Ceze, L., Tuck, J., Montesinos, P., Torrellas, J.: Bulksc: bulk enforcement of sequential consistency. In: Proceedings of the 34th International Symposium on Computer Architecture, pp. 278\u2013289 (2007)","DOI":"10.1145\/1250662.1250697"},{"key":"215_CR10","unstructured":"Culler, D., Singh, J.P., Gupta, A.: Parallel Computer Architecture: A Hardware\/Software Approach (1998)"},{"key":"215_CR11","doi-asserted-by":"crossref","unstructured":"Esmaeilzadeh, H., Blem, E., St. Amant, R., Sankaralingam, K., Burger, D.: Dark silicon and the end of multicore scaling. In: Proceedings of the 38th Annual International Symposium on Computer Architecture, pp. 365\u2013376 (2011)","DOI":"10.1145\/2000064.2000108"},{"issue":"2\/3","key":"215_CR12","doi-asserted-by":"crossref","first-page":"235","DOI":"10.1147\/rd.462.0235","volume":"46","author":"DJ Frank","year":"2002","unstructured":"Frank, D.J.: Power-constrained CMOS scaling limits. IBM J. Res. Dev. 46(2\/3), 235\u2013244 (2002)","journal-title":"IBM J. Res. Dev."},{"key":"215_CR13","doi-asserted-by":"crossref","unstructured":"Gomaa, M., Scarbrough, C., Vijaykumar, T.N., Pomeranz, I.: Transient-fault recovery for chip multiprocessors. In: Proceedings of the 30th International Symposium on Computer Architecture, pp. 98\u2013109. San Diego, California (2003)","DOI":"10.1145\/859630.859631"},{"issue":"2","key":"215_CR14","doi-asserted-by":"crossref","first-page":"518","DOI":"10.1109\/JSSC.2007.914328","volume":"43","author":"T-H Kim","year":"2008","unstructured":"Kim, T.-H., Liu, J., Keane, J., Kim, C.: A 0.2 v, 480 kb subthreshold sram with 1 k cells per bitline for ultra-low-voltage computing. IEEE J. Solid-State Circuits 43(2), 518\u2013529 (2008)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"215_CR15","doi-asserted-by":"crossref","unstructured":"Kumar, R., Zyuban, V., Tullsen, D.M.: Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling. In: Proceedings of the 32th International Symposium on Computer Architecture (ISCA\u201905), pp. 408\u2013419. Madison, Wisconsin (2005)","DOI":"10.1145\/1080695.1070004"},{"key":"215_CR16","doi-asserted-by":"crossref","unstructured":"LaFrieda, C., Ipek, E., Martinez, J.F., Manohar, R.: Utilizing dynamically coupled cores to form a resilient chip multiprocessor. In: Proceedings of the 37th International Conference on Dependable Systems and Networks, pp. 317\u2013326. Edinburgh, UK (2007)","DOI":"10.1109\/DSN.2007.100"},{"key":"215_CR17","doi-asserted-by":"crossref","unstructured":"Li, M.-L., Ramachandran, P., Sahoo, S., Adve, S., Adve, V., Zhou, Y.: Understanding the propagation of hard errors to software and implications for resilient system design. In: Proceedings of the 13th International Conference on Architectural Support for Programming Language and Operating Systems, pp. 265\u2013276. Seattle, WA, USA (2008)","DOI":"10.1145\/1346281.1346315"},{"key":"215_CR18","unstructured":"Li, M.-L., Sasanka, R., Adve, S.V., Kuang Chen, Y., Debes, E.: The alpbench benchmark suite for complex multimedia applications. In: Proceedings of the IEEE International Symposium on Workload Characterization, pp. 34\u201345 (2005)"},{"key":"215_CR19","doi-asserted-by":"crossref","unstructured":"Magnusson, P.S., Christensson, M., Eskilson, J., Forsgren, D., Hallberg, G., Hogberg, J., Larsson, F., Moestedt, A., Werner, B., Werner, B.: Simics: a full system simulation platform. Computer 35(2), 50\u201358 (2002)","DOI":"10.1109\/2.982916"},{"key":"215_CR20","doi-asserted-by":"crossref","unstructured":"Martin, M.M.K., Sorin, D.J., Beckmann, B.M., Marty, M.R., Xu, M., Alameldeen, A.R., Moore, K.E., Hill, M.D., Wood, D.A.: Multifacet\u2019s general execution-driven multiprocessor simulator (gems) toolset. SIGARCH Comput. Archit. News 33(4), 92\u201399 (2005)","DOI":"10.1145\/1105734.1105747"},{"key":"215_CR21","doi-asserted-by":"crossref","unstructured":"Mukherjee, S., Kontz, M., Reinhardt, S.K.: Detailed design and evaluation of redundant multithreading alternatives. In: Proceedings of the 29th International Symposium on Computer Architecture, pp. 99\u2013110. Anchorage, Alaska, USA (2002)","DOI":"10.1109\/ISCA.2002.1003566"},{"key":"215_CR22","doi-asserted-by":"crossref","first-page":"2","DOI":"10.1145\/248209.237140","volume":"31","author":"K Olukotun","year":"1996","unstructured":"Olukotun, K., Nayfeh, B.A., Hammond, L., Wilson, K., Chang, K.: The case for a single-chip multiprocessor. SIGPLAN Not. 31, 2\u201311 (1996)","journal-title":"SIGPLAN Not."},{"key":"215_CR23","doi-asserted-by":"crossref","unstructured":"Rashid, M., Huang, M.: Supporting highly-decoupled thread-level redundancy for parallel programs. In: Proceedings of the 14th International Symposium on High Performance Computer Architecture, pp. 393\u2013404. Salt Lake City, USA (2008)","DOI":"10.1109\/HPCA.2008.4658655"},{"key":"215_CR24","doi-asserted-by":"crossref","unstructured":"Reinhardt, S.K., Mukherjee, S.: Transient fault detection via simultaneous multithreading. In: Proceedings of the 27th International Symposium on Computer Architecture, pp. 25\u201336. Vancouver, British Columbia, Canada (2000)","DOI":"10.1109\/ISCA.2000.854375"},{"key":"215_CR25","doi-asserted-by":"crossref","unstructured":"S\u00e1nchez, D., Arag\u00f3n, J.L., Garc\u00eda, J.M.: Repas: reliable execution for parallel applications in tiled-cmps. In: 15th International European Conference on Parallel and Distributed Computing (Euro-Par 2009), pp. 321\u2013333 (2009)","DOI":"10.1007\/978-3-642-03869-3_32"},{"key":"215_CR26","doi-asserted-by":"crossref","unstructured":"S\u00e1nchez, D., Arag\u00f3n, J.L., Garc\u00eda, J.M.: A log-based redundant architecture for reliable parallel computation. In: 17th International Conference on High Performance Computing (HiPC), pp. 1\u201310. Goa (India) (2010)","DOI":"10.1109\/HIPC.2010.5713183"},{"key":"215_CR27","doi-asserted-by":"crossref","unstructured":"Sasanka, R., Adve, S.V., Chen, Y.-K., Debes, E.: The energy efficiency of cmp vs. smt for multimedia workloads. In: Proceedings of the 18th Annual International Conference on Supercomputing, ICS \u201904, pp. 196\u2013206. ACM, NY (2004)","DOI":"10.1145\/1006209.1006238"},{"key":"215_CR28","doi-asserted-by":"crossref","unstructured":"Smolens, J.C., Gold, B.T., Falsafi, B., Hoe, J.C.: Reunion: complexity-effective multicore redundancy. In: Proceedings of the 39th International Symposium on Microarchitecture, pp. 223\u2013234. Orlando, Florida, USA (2006)","DOI":"10.1109\/MICRO.2006.42"},{"key":"215_CR29","doi-asserted-by":"crossref","unstructured":"Smolens, J.C., Gold, B.T., Kim, J., Falsafi, B., Hoe, J.C., Nowatzyk, A.G.: Fingerprinting: bounding soft-error-detection latency and bandwidth. IEEE Micro. 24(6), 22\u201329 (2004)","DOI":"10.1109\/MM.2004.72"},{"key":"215_CR30","doi-asserted-by":"crossref","first-page":"863","DOI":"10.1147\/rd.435.0863","volume":"43","author":"L Spainhower","year":"1999","unstructured":"Spainhower, L., Gregg, T.A.: Ibm s\/390 parallel enterprise server g5 fault tolerance: a historical perspective. IBM J. Res. Dev. 43, 863\u2013873 (1999)","journal-title":"IBM J. Res. Dev."},{"issue":"2\/3","key":"215_CR31","doi-asserted-by":"crossref","first-page":"213","DOI":"10.1147\/rd.462.0213","volume":"46","author":"Y Taur","year":"2002","unstructured":"Taur, Y.: CMOS design near to the limit of scaling. IBM J. Res. Dev. 46(2\/3), 213\u2013222 (2002)","journal-title":"IBM J. Res. Dev."},{"issue":"2","key":"215_CR32","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1109\/MM.2002.997877","volume":"22","author":"MB Taylor","year":"2002","unstructured":"Taylor, M.B., Kim, J., Miller, J., Wentzlaff, D., Ghodrat, F., Greenwald, B., Hoffman, H., Johnson, P., Lee, J.-W., Lee, W., Ma, A., Saraf, A., Seneski, M., Shnidman, N., Strumpen, V., Frank, M., Amarasinghe, S., Agarwal, A.: The raw microprocessor: a computational fabric for software circuits and general-purpose programs. IEEE Micro 22(2), 25\u201335 (2002)","journal-title":"IEEE Micro"},{"key":"215_CR33","doi-asserted-by":"crossref","unstructured":"Vangal, S., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Iyer, P., Singh, A., Jacob, T., Jain, S., Venkataraman, S., Hoskote, Y., Borkar, N.: An 80-tile 1.28tflops network-on-chip in 65nm cmos. In: Solid-State Circuits Conference, 2007, ISSCC 2007. Digest of Technical Papers. IEEE, International, pp. 98\u2013589 (2007)","DOI":"10.1109\/ISSCC.2007.373606"},{"key":"215_CR34","doi-asserted-by":"crossref","unstructured":"Vijaykumar, T., Pomeranz, I., Cheng, K.: Transient fault recovery using simultaneous multithreading. In: Proceedings of the 29th International Symposium on Computer Architecture, pp. 98\u2013109. Anchorage, Alaska (2002)","DOI":"10.1109\/ISCA.2002.1003565"},{"key":"215_CR35","doi-asserted-by":"crossref","unstructured":"Wang, N.J., Patel, S.J.: Restore: symptom-based soft error detection in microprocessors. IEEE Trans. Dependable Secur. Comput. 3(3), 188\u2013201 (2006)","DOI":"10.1109\/TDSC.2006.40"},{"key":"215_CR36","doi-asserted-by":"crossref","unstructured":"Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: The SPLASH-2 programs: characterization and methodological considerations. In: Proceedings of the 22th International Symposium on Computer Architecture (ISCA\u201995), pp. 24\u201336. Santa Margherita Ligure, Italy (1995)","DOI":"10.1145\/223982.223990"},{"key":"215_CR37","unstructured":"Yalcin, G., Unsal, O., Hur, I., Cristal, A., Valero, M.: Faultm: fault-tolerance using hardware transactional memory. In: The 3nd Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures (PESPMA 2010), pp. 34\u201347 (2010)"},{"key":"215_CR38","doi-asserted-by":"crossref","unstructured":"Yen, L., Bobba, J., Marty, M. R. Moore, K.E., Volos, H., Hill, M.D., Swift, M.M., Wood, D.A.: Logtm-se: decoupling hardware transactional memory from caches. In: Proceedings of the 19th International Symposium on High-Performance Computer Architecture, pp. 261\u2013272 (2007)","DOI":"10.1109\/HPCA.2007.346204"}],"container-title":["Distributed Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00446-014-0215-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00446-014-0215-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00446-014-0215-6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,9]],"date-time":"2019-08-09T23:26:30Z","timestamp":1565393190000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00446-014-0215-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,4,29]]},"references-count":38,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2015,4]]}},"alternative-id":["215"],"URL":"https:\/\/doi.org\/10.1007\/s00446-014-0215-6","relation":{},"ISSN":["0178-2770","1432-0452"],"issn-type":[{"value":"0178-2770","type":"print"},{"value":"1432-0452","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,4,29]]}}}