{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,31]],"date-time":"2025-10-31T07:31:41Z","timestamp":1761895901025,"version":"3.40.4"},"reference-count":10,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2014,7,5]],"date-time":"2014-07-05T00:00:00Z","timestamp":1404518400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Comput Sci Res Dev"],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1007\/s00450-014-0266-8","type":"journal-article","created":{"date-parts":[[2014,7,4]],"date-time":"2014-07-04T05:26:31Z","timestamp":1404451591000},"page":"115-124","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":10,"title":["A power measurement environment for PCIe accelerators"],"prefix":"10.1007","volume":"30","author":[{"given":"Francisco D.","family":"Igual","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luis M.","family":"Jara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jos\u00e9 I.","family":"G\u00f3mez-P\u00e9rez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luis","family":"Pi\u00f1uel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manuel","family":"Prieto-Mat\u00edas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2014,7,5]]},"reference":[{"unstructured":"(1999) Standard commands for programmable instruments, vol 1. SCPI Consortium","key":"266_CR1"},{"doi-asserted-by":"crossref","unstructured":"(2013) How a single chip causes massive power bills. GPUSimPow: a GPGPU power simulator. In: ISPASS 2013, IEEE, pp 97\u2013106","key":"266_CR2","DOI":"10.1109\/ISPASS.2013.6557150"},{"unstructured":"(2013) Intel Xeon Phi Coprocessor Datasheet. Intel Corporation","key":"266_CR3"},{"unstructured":"Barrachina S, Barreda M, Catal\u00e1n S, Dolz MF, Fabregat G, Mayo R, Quintana-Ort\u00ed ES (2013) An integrated framework for power-performance analysis of parallel scientific workloads. In: 3rd int conf on smart grids, green communications and IT energy-aware technologies, pp 114\u2013119","key":"266_CR4"},{"doi-asserted-by":"crossref","unstructured":"Chan E, Quintana-Ort\u00ed ES, Quintana-Ort\u00ed G, van de Geijn R (2007) SuperMatrix out-of-order scheduling of matrix operations for SMP and multi-core architectures. SPAA \u201907. San Diego, CA, USA, pp 116\u2013125","key":"266_CR5","DOI":"10.1145\/1248377.1248397"},{"doi-asserted-by":"crossref","unstructured":"Dongarra JJ, Luszczek P, Petitet A (2003) The linpack benchmark: Past, present, and future. CC: P&E 15:2003","key":"266_CR6","DOI":"10.1002\/cpe.728"},{"unstructured":"Jackson J (2013) Comparison and analysis of GPU energy efficiency for CUDA and OpenCL","key":"266_CR7"},{"doi-asserted-by":"crossref","unstructured":"Shao Y, Brooks D (2013) Energy characterization and instruction-level energy model of Intel\u2019s Xeon Phi processor. In: Low power electronics and design, pp 1\u20136","key":"266_CR8","DOI":"10.1109\/ISLPED.2013.6629328"},{"doi-asserted-by":"crossref","unstructured":"Ukidave Y, Ziabari AK, Mistry P, Schirner G, Kaeli D (2013) Quantifying the energy efficiency of FFT on heterogeneous platforms. In: ISPASS 2013, IEEE, pp 235\u2013244","key":"266_CR9","DOI":"10.1109\/ISPASS.2013.6557174"},{"unstructured":"Zee FGV (2009) libflame: the complete reference. http:\/\/www.lulu.com","key":"266_CR10"}],"container-title":["Computer Science - Research and Development"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00450-014-0266-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00450-014-0266-8\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00450-014-0266-8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,3]],"date-time":"2025-05-03T17:28:58Z","timestamp":1746293338000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00450-014-0266-8"}},"subtitle":["Application to the Intel Xeon Phi"],"short-title":[],"issued":{"date-parts":[[2014,7,5]]},"references-count":10,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2015,5]]}},"alternative-id":["266"],"URL":"https:\/\/doi.org\/10.1007\/s00450-014-0266-8","relation":{},"ISSN":["1865-2034","1865-2042"],"issn-type":[{"type":"print","value":"1865-2034"},{"type":"electronic","value":"1865-2042"}],"subject":[],"published":{"date-parts":[[2014,7,5]]}}}