{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T03:17:31Z","timestamp":1740107851044,"version":"3.37.3"},"reference-count":45,"publisher":"Springer Science and Business Media LLC","issue":"13","license":[{"start":{"date-parts":[[2023,4,24]],"date-time":"2023-04-24T00:00:00Z","timestamp":1682294400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,4,24]],"date-time":"2023-04-24T00:00:00Z","timestamp":1682294400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key R &D Program of China","doi-asserted-by":"crossref","award":["No. 2020YFC0832500"],"award-info":[{"award-number":["No. 2020YFC0832500"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["No. 61402210"],"award-info":[{"award-number":["No. 61402210"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100012226","name":"Fundamental Research Funds for the Central Universities","doi-asserted-by":"publisher","award":["No. lzujbky-2021-sp57","No. lzujbky-2021-sp43"],"award-info":[{"award-number":["No. lzujbky-2021-sp57","No. lzujbky-2021-sp43"]}],"id":[{"id":"10.13039\/501100012226","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Gansu Provincial Science and Technology Major Special Innovation Consortium Project","award":["No. 21ZD3GA002"],"award-info":[{"award-number":["No. 21ZD3GA002"]}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Soft Comput"],"published-print":{"date-parts":[[2023,7]]},"DOI":"10.1007\/s00500-023-08020-3","type":"journal-article","created":{"date-parts":[[2023,4,24]],"date-time":"2023-04-24T18:02:36Z","timestamp":1682359356000},"page":"8775-8787","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["A shared libraries aware and bank partitioning-based mechanism for multicore architecture"],"prefix":"10.1007","volume":"27","author":[{"given":"Hubin","family":"Yang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuaixin","family":"Xu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yucong","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gang","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rui","family":"Zhou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3955-7765","authenticated-orcid":false,"given":"Qingguo","family":"Zhou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kuan-Ching","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2023,4,24]]},"reference":[{"unstructured":"AMD (2013) Bios and kernel developer\u2019s guide (bkdg) for amd family 10h processors. https:\/\/www.amd.com\/system\/files\/TechDocs\/31116.pdf","key":"8020_CR1"},{"doi-asserted-by":"crossref","unstructured":"Bao Y, Chen M, Ruan Y, et\u00a0al (2008) HMTT: a platform independent full-system memory trace monitoring system. In: Proceedings of the 2008 ACM SIGMETRICS international conference on measurement and modeling of computer systems, SIGMETRICS 2008, Annapolis, MD, USA, June 2\u20136, 2008. ACM, pp 229\u2013240","key":"8020_CR2","DOI":"10.1145\/1384529.1375484"},{"issue":"5","key":"8020_CR3","doi-asserted-by":"publisher","first-page":"90","DOI":"10.1109\/5992.947112","volume":"3","author":"DM Beazley","year":"2001","unstructured":"Beazley DM, Ward BD, Cooke IR (2001) The inside story on shared libraries and dynamic loading. Comput Sci Eng 3(5):90\u201397","journal-title":"Comput Sci Eng"},{"doi-asserted-by":"crossref","unstructured":"Chandru V, Mueller F (2016) Reducing noc and memory contention for manycores. In: Architecture of Computing Systems - ARCS 2016 - 29th international conference, Nuremberg, Germany, April 4\u20137, 2016, Proceedings, lecture notes in computer science, vol 9637. Springer, pp 293\u2013305","key":"8020_CR4","DOI":"10.1007\/978-3-319-30695-7_22"},{"issue":"3","key":"8020_CR5","doi-asserted-by":"publisher","first-page":"189","DOI":"10.1080\/09540091.2017.1310181","volume":"29","author":"Buning M de Cock","year":"2017","unstructured":"de Cock Buning M, de Bruin R (2017) Autonomous intelligent cars: proof that the EPSRC principles are future-proof. Connect Sci 29(3):189\u2013199","journal-title":"Connect Sci"},{"doi-asserted-by":"crossref","unstructured":"Do H, Hayot-Sasson V, da\u00a0Silva RF, et\u00a0al (2021) Modeling the linux page cache for accurate simulation of data-intensive applications. In: IEEE International conference on cluster computing, CLUSTER 2021, Portland, OR, USA, September 7-10, 2021. IEEE, pp 398\u2013408","key":"8020_CR6","DOI":"10.1109\/Cluster48925.2021.00058"},{"doi-asserted-by":"crossref","unstructured":"Fang J, Lu J, Cai M (2015) Bank partitioning based adaptive page policy in multi-core memory systems. In: International symposium on distributed computing and applications for business engineering and science (DCABES). IEEE, pp 240\u2013243","key":"8020_CR7","DOI":"10.1109\/DCABES.2015.67"},{"issue":"4","key":"8020_CR8","doi-asserted-by":"publisher","first-page":"3129","DOI":"10.1007\/s11227-019-03135-7","volume":"76","author":"J Fang","year":"2020","unstructured":"Fang J, Wang M, Wei Z (2020) A memory scheduling strategy for eliminating memory access interference in heterogeneous system. J Supercomput 76(4):3129\u20133154","journal-title":"J Supercomput"},{"unstructured":"Farshchi F, Valsan PK, Mancuso R, et\u00a0al (2018) Deterministic memory abstraction and supporting multicore system architecture. In: 30th Euromicro conference on real-time systems, ECRTS 2018, July 3\u20136, 2018, Barcelona, Spain, LIPIcs, vol 106. Schloss Dagstuhl - Leibniz-Zentrum f\u00fcr Informatik, pp 1:1\u20131:25","key":"8020_CR9"},{"issue":"12","key":"8020_CR10","doi-asserted-by":"publisher","first-page":"1597","DOI":"10.1002\/spe.2294","volume":"45","author":"N Goonasekera","year":"2015","unstructured":"Goonasekera N, Caelli WJ, Fidge CJ (2015) Libvm: an architecture for shared library sandboxing. Softw Pract Exp 45(12):1597\u20131617","journal-title":"Softw Pract Exp"},{"doi-asserted-by":"crossref","unstructured":"Hassan M, Kaushik AM, Patel HD (2015) Reverse-engineering embedded memory controllers through latency-based analysis. In: 21st IEEE real-time and embedded technology and applications symposium, Seattle, WA, USA, April 13\u201316, 2015. IEEE Computer Society, pp 297\u2013306","key":"8020_CR11","DOI":"10.1109\/RTAS.2015.7108453"},{"doi-asserted-by":"crossref","unstructured":"Helm C, Akiyama S, Taura K (2020) Reliable reverse engineering of intel DRAM addressing using performance counters. In: 28th international symposium on modeling, analysis, and simulation of computer and telecommunication systems, MASCOTS 2020, Nice, France, November 17-19, 2020. IEEE, pp 1\u20138","key":"8020_CR12","DOI":"10.1109\/MASCOTS50786.2020.9285962"},{"doi-asserted-by":"crossref","unstructured":"Ikeda T, Kise K (2013) Application aware DRAM bank partitioning in CMP. In: 19th IEEE international conference on parallel and distributed systems, ICPADS 2013, Seoul, Korea, December 15\u201318, 2013. IEEE Computer Society, pp 349\u2013356","key":"8020_CR13","DOI":"10.1109\/ICPADS.2013.56"},{"doi-asserted-by":"crossref","unstructured":"Jeong MK, Yoon DH, Sunwoo D, et\u00a0al (2012) Balancing DRAM locality and parallelism in shared memory CMP systems. In: 18th IEEE international symposium on high performance computer architecture, HPCA 2012, New Orleans, LA, USA, 25\u201329 February, 2012. IEEE Computer Society, pp 53\u201364","key":"8020_CR14","DOI":"10.1109\/HPCA.2012.6168944"},{"unstructured":"Jia G, Li X, Yuan Y, et\u00a0al (2014) Pseudonuma for reducing memory interference in multi-core systems. In: 2014 Spring simulation multiconference, SpringSim \u201914, Tampa, FL, USA, April 13-16, 2014, Proceedings of the high performance computing symposium. ACM, p\u00a06","key":"8020_CR15"},{"issue":"2","key":"8020_CR16","doi-asserted-by":"publisher","first-page":"113","DOI":"10.1080\/09540091.2020.1758924","volume":"33","author":"J Jiao","year":"2021","unstructured":"Jiao J, Wang L, Li Y et al (2021) CASH: correlation-aware scheduling to mitigate soft error impact on heterogeneous multicores. Connect Sci 33(2):113\u2013135","journal-title":"Connect Sci"},{"unstructured":"Jonggyu P, Oh K, Eom YI (2020) Towards application-level i\/o proportionality with a weight-aware page cache management. In: 36th international conference on massive storage systems and technology, MSST 2020, October 29\u201330, 2020, pp 1\u201311","key":"8020_CR17"},{"issue":"2","key":"8020_CR18","doi-asserted-by":"publisher","first-page":"101","DOI":"10.1109\/LCA.2015.2495103","volume":"15","author":"D Jung","year":"2016","unstructured":"Jung D, Li S, Ahn JH (2016) Large pages on steroids: small ideas to accelerate big memory applications. IEEE Comput Archit Lett 15(2):101\u2013104","journal-title":"IEEE Comput Archit Lett"},{"doi-asserted-by":"crossref","unstructured":"Kim H, Kandhalu A, Rajkumar R (2013) A coordinated approach for practical os-level cache management in multi-core real-time systems. In: 25th Euromicro conference on real-time systems, ECRTS 2013, Paris, France, July 9\u201312, 2013. IEEE Computer Society, pp 80\u201389","key":"8020_CR19","DOI":"10.1109\/ECRTS.2013.19"},{"doi-asserted-by":"crossref","unstructured":"Kim H, de\u00a0Niz D, Andersson B, et\u00a0al (2014) Bounding memory interference delay in cots-based multi-core systems. In: 20th IEEE real-time and embedded technology and applications symposium, RTAS 2014, Berlin, Germany, April 15-17, 2014. IEEE Computer Society, pp 145\u2013154","key":"8020_CR20","DOI":"10.1109\/RTAS.2014.6925998"},{"doi-asserted-by":"crossref","unstructured":"Kim N, Chisholm M, Otterness N, et\u00a0al (2017) Allowing shared libraries while supporting hardware isolation in multicore real-time systems. In: 2017 IEEE real-time and embedded technology and applications symposium, RTAS 2017, Pittsburg, PA, USA, April 18-21, 2017. IEEE Computer Society, pp 223\u2013234","key":"8020_CR21","DOI":"10.1109\/RTAS.2017.14"},{"doi-asserted-by":"crossref","unstructured":"Liu L, Cui Z, Xing M, et\u00a0al (2012) A software memory partition approach for eliminating bank-level interference in multicore systems. In: International conference on parallel architectures and compilation techniques, PACT \u201912, Minneapolis, MN, USA - September 19 - 23, 2012. ACM, pp 367\u2013376","key":"8020_CR22","DOI":"10.1145\/2370816.2370869"},{"issue":"3","key":"8020_CR23","doi-asserted-by":"publisher","first-page":"347","DOI":"10.26599\/TST.2019.9010077","volume":"26","author":"W Liu","year":"2021","unstructured":"Liu W, Zhou K, Huang P et al (2021) Rbc: a memory architecture for improved performance and energy efficiency. Tsinghua Sci Technol 26(3):347\u2013360","journal-title":"Tsinghua Sci Technol"},{"doi-asserted-by":"crossref","unstructured":"Liu Y, Lu J, Tong D, et\u00a0al (2017) Locality-aware bank partitioning for shared DRAM mpsocs. In: 22nd Asia and south pacific design automation conference, ASP-DAC 2017, Chiba, Japan, January 16\u201319, 2017. IEEE, pp 770\u2013775","key":"8020_CR24","DOI":"10.1109\/ASPDAC.2017.7858417"},{"doi-asserted-by":"crossref","unstructured":"Margaritov A, Ustiugov D, Bugnion E, et\u00a0al (2019) Prefetched address translation. In: Proceedings of the 52nd annual IEEE\/ACM international symposium on microarchitecture, MICRO 2019, Columbus, OH, USA, October 12\u201316, 2019. ACM, pp 1023\u20131036","key":"8020_CR25","DOI":"10.1145\/3352460.3358294"},{"doi-asserted-by":"crossref","unstructured":"Margaritov A, Ustiugov D, Shahab A, et\u00a0al (2021) Ptemagnet: fine-grained physical memory reservation for faster page walks in public clouds. In: Sherwood T, Berger ED, Kozyrakis C (eds) ASPLOS \u201921: 26th ACM international conference on architectural support for programming languages and operating systems, Virtual Event, USA, April 19\u201323, 2021. ACM, pp 211\u2013223","key":"8020_CR26","DOI":"10.1145\/3445814.3446704"},{"doi-asserted-by":"crossref","unstructured":"Mi W, Feng X, Xue J, et\u00a0al (2010) Software-hardware cooperative DRAM bank partitioning for chip multiprocessors. In: Network and parallel computing, IFIP international conference, NPC 2010, Zhengzhou, China, September 13-15, 2010. Proceedings, Lecture Notes in Computer Science, vol 6289. Springer, pp 329\u2013343","key":"8020_CR27","DOI":"10.1007\/978-3-642-15672-4_28"},{"doi-asserted-by":"crossref","unstructured":"Pan X, Mueller F (2018) Controller-aware memory coloring for multicore real-time systems. In: Proceedings of the 33rd annual ACM symposium on applied computing, SAC 2018, Pau, France, April 09-13, 2018. ACM, pp 584\u2013592","key":"8020_CR28","DOI":"10.1145\/3167132.3167196"},{"doi-asserted-by":"crossref","unstructured":"Pan X, Gownivaripalli YJ, Mueller F (2016) Tintmalloc: reducing memory access divergence via controller-aware coloring. In: 2016 IEEE international parallel and distributed processing symposium, IPDPS 2016, Chicago, IL, USA, May 23\u201327, 2016. IEEE Computer Society, pp 363\u2013372","key":"8020_CR29","DOI":"10.1109\/IPDPS.2016.26"},{"doi-asserted-by":"crossref","unstructured":"Panwar A, Gopinath K (2015) Towards practical page placement for a green memory manager. In: 22nd IEEE international conference on high performance computing, HiPC 2015, Bengaluru, India, December 16-19, 2015. IEEE Computer Society, pp 155\u2013164","key":"8020_CR30","DOI":"10.1109\/HiPC.2015.42"},{"doi-asserted-by":"crossref","unstructured":"Park H, Baek S, Choi J, et\u00a0al (2013) Regularities considered harmful: forcing randomness to memory accesses to reduce row buffer conflicts for multi-core, multi-bank systems. In: Architectural support for programming languages and operating systems, ASPLOS \u201913, Houston, TX, USA - March 16 - 20, 2013. ACM, pp 181\u2013192","key":"8020_CR31","DOI":"10.1145\/2499368.2451137"},{"unstructured":"Pessl P, Gruss D, Maurice C, et\u00a0al (2016) DRAMA: exploiting DRAM addressing for cross-cpu attacks. In: 25th USENIX security symposium, USENIX Security 16, Austin, TX, USA, August 10-12, 2016. USENIX Association, pp 565\u2013581","key":"8020_CR32"},{"doi-asserted-by":"crossref","unstructured":"Qiang W, Cao Y, Dai W, et\u00a0al (2017) Libsec: A hardware virtualization-based isolation for shared library. In: 19th IEEE international conference on high performance computing and communications; 15th IEEE international conference on smart city; 3rd IEEE International Conference on Data Science and Systems, HPCC\/SmartCity\/DSS 2017, Bangkok, Thailand, December 18-20, 2017. IEEE Computer Society, pp 34\u201341","key":"8020_CR33","DOI":"10.1109\/HPCC-SmartCity-DSS.2017.5"},{"unstructured":"SPEC (2018) Spec cpu 2006. https:\/\/www.spec.org\/cpu2006\/","key":"8020_CR34"},{"doi-asserted-by":"crossref","unstructured":"Suzuki N, Kim H, de\u00a0Niz D, et\u00a0al (2013) Coordinated bank and cache coloring for temporal protection of memory accesses. In: 16th IEEE international conference on computational science and engineering, CSE 2013, December 3\u20135, 2013, Sydney, Australia. IEEE Computer Society, pp 685\u2013692","key":"8020_CR35","DOI":"10.1109\/CSE.2013.106"},{"doi-asserted-by":"crossref","unstructured":"Suzuki N, Kim H, de\u00a0Niz D, et\u00a0al (2013) Coordinated bank and cache coloring for temporal protection of memory accesses. In: 16th IEEE international conference on computational science and engineering, CSE 2013, December 3-5, 2013, Sydney, Australia. IEEE Computer Society, pp 685\u2013692","key":"8020_CR36","DOI":"10.1109\/CSE.2013.106"},{"doi-asserted-by":"crossref","unstructured":"Wang X, Wang X, Zhu F, et\u00a0al (2016) Mei: a light weight memory error injection tool for validating online memory testers. In: 2016 International symposium on system and software reliability (ISSSR) pp 129\u2013136","key":"8020_CR37","DOI":"10.1109\/ISSSR.2016.028"},{"doi-asserted-by":"crossref","unstructured":"Wu Y, Sathyanarayan S, Yap RHC, et\u00a0al (2012) Codejail: Application-transparent isolation of libraries with tight program interactions. In: Computer security - ESORICS 2012 - 17th European symposium on research in computer security, Pisa, Italy, September 10\u201312, 2012. Proceedings, Lecture Notes in Computer Science, vol 7459. Springer, pp 859\u2013876","key":"8020_CR38","DOI":"10.1007\/978-3-642-33167-1_49"},{"unstructured":"Xiao Y, Zhang X, Zhang Y, et\u00a0al (2016) One bit flips, one cloud flops: cross-vm row hammer attacks and privilege escalation. In: 25th USENIX security symposium, USENIX security 16, Austin, TX, USA, August 10-12, 2016. USENIX Association, pp 19\u201335","key":"8020_CR39"},{"doi-asserted-by":"crossref","unstructured":"Xie M, Tong D, Feng Y, et\u00a0al (2013) Page policy control with memory partitioning for DRAM performance and power efficiency. In: International symposium on low power electronics and design (ISLPED), Beijing, China, September 4-6, 2013. IEEE, pp 298\u2013303","key":"8020_CR40","DOI":"10.1109\/ISLPED.2013.6629312"},{"doi-asserted-by":"crossref","unstructured":"Xie M, Tong D, Huang K, et\u00a0al (2014) Improving system throughput and fairness simultaneously in shared memory CMP systems via dynamic bank partitioning. In: 20th IEEE international symposium on high performance computer architecture, HPCA 2014, Orlando, FL, USA, February 15-19, 2014. IEEE Computer Society, pp 344\u2013355","key":"8020_CR41","DOI":"10.1109\/HPCA.2014.6835945"},{"issue":"5","key":"8020_CR42","doi-asserted-by":"publisher","first-page":"535","DOI":"10.26599\/TST.2018.9010134","volume":"24","author":"L Xu","year":"2019","unstructured":"Xu L, Yu R, Wang L et al (2019) Memway: in-memorywaylaying acceleration for practical rowhammer attacks against binaries. Tsinghua Sci Technol 24(5):535\u2013545","journal-title":"Tsinghua Sci Technol"},{"doi-asserted-by":"crossref","unstructured":"Yun H, Mancuso R, Wu ZP, et\u00a0al (2014) PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms. In: 20th IEEE real-time and embedded technology and applications symposium, RTAS 2014, Berlin, Germany, April 15\u201317, 2014. IEEE Computer Society, pp 155\u2013166","key":"8020_CR43","DOI":"10.1109\/RTAS.2014.6925999"},{"issue":"2","key":"8020_CR44","doi-asserted-by":"publisher","first-page":"173","DOI":"10.1080\/09540091.2020.1782840","volume":"33","author":"H Zhao","year":"2021","unstructured":"Zhao H, Yao L, Zeng Z et al (2021) An edge streaming data processing framework for autonomous driving. Connect Sci 33(2):173\u2013200","journal-title":"Connect Sci"},{"doi-asserted-by":"crossref","unstructured":"Zheng H, Lin J, Zhang Z et al (2008) Mini-rank: adaptive DRAM architecture for improving memory power efficiency. In: 41st annual IEEE\/ACM international symposium on microarchitecture (MICRO-41 2008), November 8\u201312, 2008. Italy. IEEE Computer Society, Lake Como, pp 210\u2013221","key":"8020_CR45","DOI":"10.1109\/MICRO.2008.4771792"}],"container-title":["Soft Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00500-023-08020-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00500-023-08020-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00500-023-08020-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,5,29]],"date-time":"2023-05-29T06:08:16Z","timestamp":1685340496000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00500-023-08020-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,4,24]]},"references-count":45,"journal-issue":{"issue":"13","published-print":{"date-parts":[[2023,7]]}},"alternative-id":["8020"],"URL":"https:\/\/doi.org\/10.1007\/s00500-023-08020-3","relation":{},"ISSN":["1432-7643","1433-7479"],"issn-type":[{"type":"print","value":"1432-7643"},{"type":"electronic","value":"1433-7479"}],"subject":[],"published":{"date-parts":[[2023,4,24]]},"assertion":[{"value":"7 March 2023","order":1,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"24 April 2023","order":2,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors have no competing interests to declare relevant to this article\u2019s content.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}},{"value":"This article does not contain any studies with human participants or animals performed by any authors.","order":3,"name":"Ethics","group":{"name":"EthicsHeading","label":"Ethical approval"}},{"value":"Not applicable.","order":4,"name":"Ethics","group":{"name":"EthicsHeading","label":"Informed consent"}}]}}