{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T13:45:20Z","timestamp":1740145520559,"version":"3.37.3"},"reference-count":5,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2015,8,15]],"date-time":"2015-08-15T00:00:00Z","timestamp":1439596800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Elektrotech. Inftech."],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1007\/s00502-015-0314-5","type":"journal-article","created":{"date-parts":[[2015,8,14]],"date-time":"2015-08-14T05:52:23Z","timestamp":1439531543000},"page":"269-273","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Verification challenges of complex system-on-chip devices","Herausforderungen an die Verifikation komplexer System-on-Chips"],"prefix":"10.1007","volume":"132","author":[{"given":"Martin","family":"Horauer","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dominik","family":"Widhalm","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefan","family":"Tauner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefan","family":"Mirtl","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2015,8,15]]},"reference":[{"key":"314_CR1","first-page":"1","volume-title":"Design, automation test in Europe exhibition","author":"A. Adir","year":"2011","unstructured":"Adir, A., Copty, S., Landa, S., Nahir, A., Shurek, G., Ziv, A., Meissner, C., Schumann, J. (2011): A unified methodology for pre-silicon verification and post-silicon validation. In Design, automation test in Europe exhibition, DATE (pp. 1\u20136). Available online at: http:\/\/dx.doi.org\/10.1109\/DATE.2011.5763252 . doi: 10.1109\/DATE.2011.5763252 ."},{"key":"314_CR2","doi-asserted-by":"crossref","first-page":"569","DOI":"10.1145\/2024724.2024856","volume-title":"48th ACM\/EDAC\/IEEE design automation conference","author":"A. Adir","year":"2011","unstructured":"Adir, A., Nahir, A., Shurek, G., Ziv, A., Meissner, C., Schumann, J. (2011): Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor. In 48th ACM\/EDAC\/IEEE design automation conference, DAC (pp. 569\u2013574). Available online at: http:\/\/ieeexplore.ieee.org\/xpls\/abs_all.jsp?arnumber=5981978 ."},{"key":"314_CR3","first-page":"205","volume-title":"Ph.D. research in microelectronics and electronics","author":"M. Melani","year":"2006","unstructured":"Melani, M., D\u2019Ascoli, F., Marino, C., Fanucci, L., Giambastiani, A., Rocchi, A., De Marinis, M., Monterastelli, A. (2006): An integrated flow from pre-silicon simulation to post-silicon verification. In Ph.D. research in microelectronics and electronics (pp. 205\u2013208). Available online at: http:\/\/dx.doi.org\/10.1109\/RME.2006.1689932 . doi: 10.1109\/RME.2006.1689932 ."},{"issue":"2","key":"314_CR4","doi-asserted-by":"crossref","first-page":"139","DOI":"10.1023\/A:1011173710479","volume":"17","author":"F. Aza\u00efs","year":"2001","unstructured":"Aza\u00efs, F., Bernard, S., Bertrand, Y., Renovell, M. (2001): A low-cost BIST architecture for linear histogram testing of ADCs. J. Electron. Test., 17(2), 139\u2013147. Available online at: http:\/\/dx.doi.org\/10.1023\/A:1011173710479 . doi: 10.1023\/A:1011173710479 .","journal-title":"J. Electron. Test."},{"key":"314_CR5","first-page":"590","volume-title":"Design, automation and test in Europe proceedings","author":"F. Aza\u00efs","year":"2001","unstructured":"Aza\u00efs, F., Bernard, S., Bertrand, Y., Renovell, M. (2001): Implementation of a linear histogram BIST for ADCs. In Design, automation and test in Europe proceedings, DATE (pp. 590\u2013595). New York: IEEE Press. Available online at: http:\/\/dl.acm.org\/citation.cfm?id=367072.367829 ."}],"container-title":["e &amp; i Elektrotechnik und Informationstechnik"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00502-015-0314-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00502-015-0314-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00502-015-0314-5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,20]],"date-time":"2022-05-20T12:09:38Z","timestamp":1653048578000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00502-015-0314-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,8,15]]},"references-count":5,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2015,9]]}},"alternative-id":["314"],"URL":"https:\/\/doi.org\/10.1007\/s00502-015-0314-5","relation":{},"ISSN":["0932-383X","1613-7620"],"issn-type":[{"type":"print","value":"0932-383X"},{"type":"electronic","value":"1613-7620"}],"subject":[],"published":{"date-parts":[[2015,8,15]]}}}