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Inftech."],"published-print":{"date-parts":[[2024,3]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>Analog circuit design automation remains an intense area of attention and has seen both new and existing tools continuing to be developed and targeting different phases of the analog design flow to reduce development time and cost. One of the promising tools is the Berkeley Analog Generator (BAG2) framework which is an open-source analog layout generator for automating and verifying circuit layouts. It promises a\u00a0process-independent flow and it encourages design reuse due to using parameterized generators which can be scaled as required. This reduces the layout development time compared to manual handmade layouts. This work describes the effort and results of evaluating the BAG2 framework for the TSMC 65\u202fnm and Cadence GPDK 45\u202fnm processes. A\u00a0case study is made with a\u00a0number of circuits to discuss the problems in setting up and using BAG2 for the above technologies as well as the limitations and solutions required to utilize the framework effectively.<\/jats:p>","DOI":"10.1007\/s00502-023-01203-8","type":"journal-article","created":{"date-parts":[[2024,1,31]],"date-time":"2024-01-31T14:03:16Z","timestamp":1706709796000},"page":"88-100","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["BAG2-assisted analog layout synthesis for TSMC 65\u202fnm and GPDK 45\u202fnm","BAG2-unterst\u00fctzte analoge Layout-Synthese f\u00fcr TSMC 65\u202fnm und GPDK 45\u202fnm"],"prefix":"10.1007","volume":"141","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-0155-569X","authenticated-orcid":false,"given":"Matthew","family":"Bio","sequence":"first","affiliation":[]},{"given":"Wolfgang","family":"Scherr","sequence":"additional","affiliation":[]},{"given":"A. S.","family":"Agbemenu","sequence":"additional","affiliation":[]},{"given":"Santiago Martin","family":"Sond\u00f3n","sequence":"additional","affiliation":[]},{"given":"Vinayak","family":"Hande","sequence":"additional","affiliation":[]},{"given":"Johannes","family":"Sturm","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2024,1,31]]},"reference":[{"key":"1203_CR1","series-title":"GitHub June 2023","volume-title":"HDL21: Hardware Description Python Library","author":"D Fritchman","year":"2023","unstructured":"Fritchman D (2023) HDL21: Hardware Description Python Library. GitHub June 2023 (https:\/\/github.com\/dan-fritchman\/Hdl21)"},{"key":"1203_CR2","volume-title":"2nd International Conference on Micro-Electronics and Telecommunication Engineering (ICMETE)","author":"SL Pinjare","year":"2018","unstructured":"Pinjare SL, Nithya G, Nagaraja VS, Sthuthi A (2018) A Gm\/id based methodology for designing common source amplifier. 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