{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:46:10Z","timestamp":1780674370372,"version":"3.54.1"},"reference-count":35,"publisher":"Springer Science and Business Media LLC","issue":"18","license":[{"start":{"date-parts":[[2021,3,16]],"date-time":"2021-03-16T00:00:00Z","timestamp":1615852800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,3,16]],"date-time":"2021-03-16T00:00:00Z","timestamp":1615852800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61976063"],"award-info":[{"award-number":["61976063"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Neural Comput &amp; Applic"],"published-print":{"date-parts":[[2021,9]]},"DOI":"10.1007\/s00521-021-05817-x","type":"journal-article","created":{"date-parts":[[2021,3,16]],"date-time":"2021-03-16T15:04:10Z","timestamp":1615907050000},"page":"11753-11764","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":8,"title":["Minimally buffered deflection router for spiking neural network hardware implementations"],"prefix":"10.1007","volume":"33","author":[{"given":"Junxiu","family":"Liu","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dong","family":"Jiang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0117-4614","authenticated-orcid":false,"given":"Yuling","family":"Luo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Senhui","family":"Qiu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yongchuang","family":"Huang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2021,3,16]]},"reference":[{"issue":"12","key":"5817_CR1","doi-asserted-by":"publisher","first-page":"2451","DOI":"10.1109\/TPDS.2012.289","volume":"24","author":"S Carrillo","year":"2013","unstructured":"Carrillo S et al (2013) Scalable hierarchical network-on-chip architecture for spiking neural network hardware implementations. IEEE Trans Parallel Distrib Syst 24(12):2451\u20132461","journal-title":"IEEE Trans Parallel Distrib Syst"},{"issue":"2012","key":"5817_CR2","doi-asserted-by":"publisher","first-page":"42","DOI":"10.1016\/j.neunet.2012.04.004","volume":"33","author":"S Carrillo","year":"2012","unstructured":"Carrillo S et al (2012) Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers. Neural Netw 33(2012):42\u201357","journal-title":"Neural Netw"},{"issue":"1","key":"5817_CR3","first-page":"1","volume":"12","author":"Y Luo","year":"2018","unstructured":"Luo Y et al (2018) Low cost interconnected architecture for the hardware spiking neural networks. Front Neurosci 12(1):1\u201314","journal-title":"Front Neurosci"},{"issue":"1","key":"5817_CR4","doi-asserted-by":"publisher","first-page":"67","DOI":"10.1016\/S0020-0255(01)00068-8","volume":"132","author":"B Roche","year":"2001","unstructured":"Roche B, Ginnity TMM, Maguire L, Daid LJM (2001) Signalling techniques and their effect on neural network implementation sizes. Inf Sci (Ny) 132(1):67\u201382","journal-title":"Inf Sci (Ny)"},{"issue":"6","key":"5817_CR5","doi-asserted-by":"publisher","first-page":"358","DOI":"10.1016\/j.micpro.2015.06.002","volume":"39","author":"J Liu","year":"2015","unstructured":"Liu J, Harkin J, Li Y, Maguire L (2015) Low cost fault-tolerant routing algorithm for networks-on-chip. Microprocess Microsyst 39(6):358\u2013372","journal-title":"Microprocess Microsyst"},{"issue":"3","key":"5817_CR6","doi-asserted-by":"publisher","first-page":"1777","DOI":"10.1007\/s11063-018-9797-5","volume":"48","author":"Y Luo","year":"2018","unstructured":"Luo Y, Wan L, Liu J, Harkin J, Cao Y (2018) An efficient, low-cost routing architecture for spiking neural network hardware implementations. Neural Process Lett 48(3):1777\u20131788","journal-title":"Neural Process Lett"},{"issue":"12","key":"5817_CR7","doi-asserted-by":"publisher","first-page":"2290","DOI":"10.1109\/TCSI.2016.2615051","volume":"63","author":"J Liu","year":"2016","unstructured":"Liu J, Harkin J, Maguire L, McDaid L, Wade J, Martin G (2016) Scalable networks-on-chip interconnected architecture for astrocyte-neuron networks. IEEE Trans Circuits Syst I-Regul Pap 63(12):2290\u20132303","journal-title":"IEEE Trans Circuits Syst I-Regul Pap"},{"key":"5817_CR8","unstructured":"Wan L, Luo Y, Song S, Harkin J, Liu J (2016) Efficient neuron architecture for FPGA-based spiking neural networks. In: Irish signals and systems conference, pp 1\u20136"},{"issue":"1","key":"5817_CR9","doi-asserted-by":"publisher","first-page":"473","DOI":"10.1016\/j.neucom.2018.11.078","volume":"331","author":"J Liu","year":"2019","unstructured":"Liu J, Huang Y, Luo Y, Harkin J, Mcdaid L (2019) Bio-inspired fault detection circuits based on synapse and spiking neuron models. Neurocomputing 331(1):473\u2013482","journal-title":"Neurocomputing"},{"issue":"5","key":"5817_CR10","doi-asserted-by":"publisher","first-page":"3117","DOI":"10.1166\/jnn.2020.17390","volume":"20","author":"S Hwang","year":"2020","unstructured":"Hwang S et al (2020) Analog complementary metal-oxide-semiconductor integrate-and-fire neuron circuit for overflow retaining in hardware spiking neural networks. J Nanosci Nanotechnol 20(5):3117\u20133122","journal-title":"J Nanosci Nanotechnol"},{"issue":"1","key":"5817_CR11","doi-asserted-by":"publisher","first-page":"70","DOI":"10.1109\/2.976921","volume":"35","author":"L Benini","year":"2002","unstructured":"Benini L, De Micheli G (2002) Networks on chips: a new SoC paradigm. IEEE Comput 35(1):70\u201378","journal-title":"IEEE Comput"},{"issue":"6","key":"5817_CR12","first-page":"2","volume":"2009","author":"J Harkin","year":"2009","unstructured":"Harkin J, Morgan F, McDaid L, Hall S, McGinley B, Cawley S (2009) A reconfigurable and biologically inspired paradigm for computation using network-on-chip and spiking neural networks. Int J Reconfig Comput 2009(6):2","journal-title":"Int J Reconfig Comput"},{"key":"5817_CR13","doi-asserted-by":"crossref","unstructured":"Moscibroda T, Mutlu O (2009) A case for bufferless routing in on-chip networks. In: International symposium on computer architecture, pp 196\u2013207","DOI":"10.1145\/1555815.1555781"},{"issue":"7","key":"5817_CR14","doi-asserted-by":"publisher","first-page":"669","DOI":"10.1016\/j.micpro.2014.07.007","volume":"38","author":"Y Li","year":"2014","unstructured":"Li Y, Mei K, Liu Y, Zheng N, Xu Y (2014) LDBR: low-deflection bufferless router for cost-sensitive network-on-chip design. Microprocess Microsyst 38(7):669\u2013680","journal-title":"Microprocess Microsyst"},{"issue":"2","key":"5817_CR15","doi-asserted-by":"publisher","first-page":"260","DOI":"10.1109\/TCAD.2015.2459050","volume":"35","author":"J Liu","year":"2016","unstructured":"Liu J, Harkin J, Li Y, Maguire L (2016) Fault-tolerant networks-on-chip routing with coarse and fine-grained look-ahead . IEEE Trans Comput Des Integr Circuits Syst 35(2):260\u2013273","journal-title":"IEEE Trans Comput Des Integr Circuits Syst"},{"key":"5817_CR16","doi-asserted-by":"crossref","unstructured":"Shayani H, Bentley PJ, Tyrrell AM (2008) A cellular structure for online routing of digital spiking neuron axons and dendrites on FPGAs. In: International conference on evolvable systems, pp 273\u2013284","DOI":"10.1007\/978-3-540-85857-7_24"},{"key":"5817_CR17","doi-asserted-by":"crossref","unstructured":"Gomez C, Gomez ME, Lopez P, Duato J (2008) Reducing packet dropping in a bufferless NoC. In: European conference on parallel processing, pp 899\u2013909","DOI":"10.1007\/978-3-540-85451-7_97"},{"key":"5817_CR18","doi-asserted-by":"crossref","unstructured":"Fallin C, Craik C, Mutlu O (2011)CHIPPER: a low-complexity bufferless deflection router. In: International symposium on high-performance computer architecture, pp 144\u2013155","DOI":"10.1109\/HPCA.2011.5749724"},{"issue":"2","key":"5817_CR19","doi-asserted-by":"publisher","first-page":"47","DOI":"10.1109\/L-CA.2012.22","volume":"12","author":"H Kim","year":"2013","unstructured":"Kim H, Kim Y, Kim J (2013) Clumsy flow control for high-throughput bufferless on-chip networks. IEEE Comput Archit Lett 12(2):47\u201350","journal-title":"IEEE Comput Archit Lett"},{"issue":"6","key":"5817_CR20","doi-asserted-by":"publisher","first-page":"751","DOI":"10.1016\/j.mejo.2014.04.015","volume":"45","author":"N Zhang","year":"2014","unstructured":"Zhang N, Gu H, Yang Y, Fan D (2014) QBNoC: QoS-aware bufferless NoC architecture. Microelectronics J 45(6):751\u2013758","journal-title":"Microelectronics J"},{"issue":"1","key":"5817_CR21","doi-asserted-by":"publisher","first-page":"13","DOI":"10.1016\/j.neucom.2006.11.029","volume":"71","author":"L Maguire","year":"2007","unstructured":"Maguire L, Mcginnity TM, Glackin B, Ghani A, Belatreche A, Harkin J (2007) Challenges for large-scale implementations of spiking neural networks on FPGAs. Neurocomputing 71(1):13\u201329","journal-title":"Neurocomputing"},{"issue":"2","key":"5817_CR22","doi-asserted-by":"publisher","first-page":"153","DOI":"10.1038\/nrn1848","volume":"7","author":"S Hill","year":"2006","unstructured":"Hill S, Markram H (2006) The blue brain project. Nat Rev Neurosci 7(2):153\u2013159","journal-title":"Nat Rev Neurosci"},{"key":"5817_CR23","doi-asserted-by":"crossref","unstructured":"Dang KN, Ben Abdallah A (2019) An efficient software-hardware design framework for spiking neural network systems. In: International conference on internet of things, embedded systems and communications (IINTEC), pp 155\u2013162","DOI":"10.1109\/IINTEC48298.2019.9112123"},{"issue":"1","key":"5817_CR24","doi-asserted-by":"publisher","first-page":"3","DOI":"10.1016\/j.neucom.2010.08.004","volume":"74","author":"H De Garis","year":"2010","unstructured":"De Garis H, Shuo C, Goertzel B, Ruiting L (2010) A world survey of artificial brain projects, part I: large-scale brain simulations. Neurocomputing 74(1):3\u201329","journal-title":"Neurocomputing"},{"key":"5817_CR25","doi-asserted-by":"crossref","unstructured":"Khan MM, et al. (2008) SpiNNaker: mapping neural networks onto a massively-parallel chip multiprocessor. In: International joint conference on neural network, 2849\u20132856","DOI":"10.1109\/IJCNN.2008.4634199"},{"issue":"10","key":"5817_CR26","doi-asserted-by":"publisher","first-page":"1537","DOI":"10.1109\/TCAD.2015.2474396","volume":"34","author":"F Akopyan","year":"2015","unstructured":"Akopyan F et al (2015) \u201cTrueNorth: design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip. IEEE Trans Comput Des Integr Circuits Syst 34(10):1537\u20131557","journal-title":"IEEE Trans Comput Des Integr Circuits Syst"},{"issue":"8","key":"5817_CR27","doi-asserted-by":"publisher","first-page":"1943","DOI":"10.1109\/JSSC.2013.2259038","volume":"48","author":"E Painkras","year":"2013","unstructured":"Painkras E et al (2013) SpiNNaker: a 1-w 18-core system-on-chip for massively-parallel neural network simulation. IEEE J Solid-State Circuits 48(8):1943\u20131953","journal-title":"IEEE J Solid-State Circuits"},{"issue":"5","key":"5817_CR28","first-page":"1","volume":"99","author":"Z Zhao","year":"2020","unstructured":"Zhao Z et al (2020) \u201cA memristor-based spiking neural network with high scalability and learning efficiency. IEEE Trans Circuits Syst II Express Briefs 99(5):1\u20135","journal-title":"IEEE Trans Circuits Syst II Express Briefs"},{"key":"5817_CR29","doi-asserted-by":"crossref","unstructured":"Fallin C, Nazario G, Yu X, Chang KK, Ausavarungnirun R, Mutlu O (2012) MinBD: minimally-buffered deflection routing for energy-efficient interconnect. In: International symposium on networks-on-chip, pp 1\u201310","DOI":"10.1109\/NOCS.2012.8"},{"issue":"8","key":"5817_CR30","doi-asserted-by":"publisher","first-page":"835","DOI":"10.3389\/fnins.2019.00835","volume":"13","author":"K Liu","year":"2019","unstructured":"Liu K et al (2019) A hardware implementation of SNN-based spatio-temporal memory model. Front Neurosci 13(8):835\u2013845","journal-title":"Front Neurosci"},{"issue":"1","key":"5817_CR31","doi-asserted-by":"publisher","first-page":"51","DOI":"10.1016\/j.mejo.2018.08.013","volume":"81","author":"K Helal","year":"2018","unstructured":"Helal K, Attia S, Fahmy HAH, Ismail T, Ismail Y, Mostafa H (2018) Dual split-merge: a high throughput router architecture for FPGAs. Microelectronics J 81(1):51\u201357","journal-title":"Microelectronics J"},{"key":"5817_CR32","doi-asserted-by":"crossref","unstructured":"Alazemi F, Azizimazreah A, Bose B, Chen L (2018) Routerless networks-on-chip. In: IEEE international symposium on high performance computer architecture, pp 492\u2013503","DOI":"10.1109\/HPCA.2018.00049"},{"issue":"6","key":"5817_CR33","doi-asserted-by":"publisher","first-page":"1053","DOI":"10.1109\/TVLSI.2012.2204909","volume":"21","author":"C Feng","year":"2013","unstructured":"Feng C, Lu Z, Jantsch A, Zhang M, Xing Z (2013) \u201cAddressing transient and permanent faults in NoC with efficient fault-tolerant deflection router. IEEE Trans Very Large Scale Integr Syst 21(6):1053\u20131066","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"5817_CR34","doi-asserted-by":"crossref","unstructured":"Kunthara RG, James RK, Sleeba SZ, Jose J (2018) ReDC: reduced deflection CHIPPER router for bufferless NoCs. In: International symposium on embedded computing and system design (ISED), pp 204\u2013209","DOI":"10.1109\/ISED.2018.8704012"},{"issue":"1","key":"5817_CR35","doi-asserted-by":"publisher","first-page":"141516","DOI":"10.1109\/ACCESS.2019.2943922","volume":"7","author":"L Wang","year":"2019","unstructured":"Wang L, Wang X, Wang Y (2019) An approximate bufferless network-on-chip. IEEE Access 7(1):141516\u2013141532","journal-title":"IEEE Access"}],"container-title":["Neural Computing and Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00521-021-05817-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00521-021-05817-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00521-021-05817-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,8,23]],"date-time":"2021-08-23T20:12:43Z","timestamp":1629749563000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00521-021-05817-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,3,16]]},"references-count":35,"journal-issue":{"issue":"18","published-print":{"date-parts":[[2021,9]]}},"alternative-id":["5817"],"URL":"https:\/\/doi.org\/10.1007\/s00521-021-05817-x","relation":{},"ISSN":["0941-0643","1433-3058"],"issn-type":[{"value":"0941-0643","type":"print"},{"value":"1433-3058","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,3,16]]},"assertion":[{"value":"16 June 2020","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"10 February 2021","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"16 March 2021","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Compliance with ethical standards"}},{"value":"The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}]}}