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The main challenge here is the sheer complexity: with state spaces exceeding <jats:inline-formula>\n              <jats:alternatives>\n                <jats:tex-math>$10^{10}$<\/jats:tex-math>\n                <mml:math xmlns:mml=\"http:\/\/www.w3.org\/1998\/Math\/MathML\">\n                  <mml:msup>\n                    <mml:mrow>\n                      <mml:mn>10<\/mml:mn>\n                    <\/mml:mrow>\n                    <mml:mrow>\n                      <mml:mn>10<\/mml:mn>\n                    <\/mml:mrow>\n                  <\/mml:msup>\n                <\/mml:math>\n              <\/jats:alternatives>\n            <\/jats:inline-formula> states, it is hard to derive test suites that achieve a meaningful type of coverage. We tackle this problem by moving away from the traditional interleaving semantics for SysML. Instead, we propose a synchronous semantics in terms of Finite State Machines (FSMs), leveraging the fact that EULYNX is implemented on Programmable Logic Controllers (PLCs). Then, we deploy Single-Input-Change Deterministic Finite State Machines (SIC-DFSMs), which ensures fully deterministic tests, thus minimizing scalability issues. Our focus lies on the EULYNX specification for <jats:italic>point controllers<\/jats:italic>. The generated test suite achieves maximal transition coverage, but test execution time remains substantial. We introduce an additional test suite that achieves maximal transition <jats:italic>label<\/jats:italic> coverage. Remarkably, this smaller suite successfully identifies the same four faults as the larger suite.<\/jats:p>","DOI":"10.1007\/s10009-025-00790-5","type":"journal-article","created":{"date-parts":[[2025,4,22]],"date-time":"2025-04-22T15:10:17Z","timestamp":1745334617000},"page":"377-395","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Conformance in the railway industry: Single-Input-Change testing a EULYNX controller"],"prefix":"10.1007","volume":"27","author":[{"given":"Djurre","family":"van\u00a0der Wal","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Marcus","family":"Gerhold","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mari\u00eblle","family":"Stoelinga","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Arend","family":"Rensink","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2025,4,22]]},"reference":[{"key":"790_CR1","doi-asserted-by":"publisher","first-page":"355","DOI":"10.1109\/ICST53961.2022.00044","volume-title":"15th IEEE Conference on Software Testing, Verification and Validation, (ICST)","author":"T. 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