{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T14:56:09Z","timestamp":1649084169746},"reference-count":10,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2006,11,29]],"date-time":"2006-11-29T00:00:00Z","timestamp":1164758400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Appl Intell"],"published-print":{"date-parts":[[2007,1,18]]},"DOI":"10.1007\/s10489-006-0005-3","type":"journal-article","created":{"date-parts":[[2006,11,28]],"date-time":"2006-11-28T18:08:50Z","timestamp":1164737330000},"page":"53-67","source":"Crossref","is-referenced-by-count":1,"title":["Assigning data to dual memory banks in DSPs with a genetic algorithm using a repair heuristic"],"prefix":"10.1007","volume":"26","author":[{"given":"G.","family":"Gr\u00e9Wal","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Coros","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Banerji","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Morton","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2006,11,29]]},"reference":[{"key":"5_CR1","doi-asserted-by":"crossref","unstructured":"Cho J, Paek Y, Whalley W (2002) Efficient register and memory assignment for non-orthogonal architectures via graph coloring and MST algorithms. In: Proceedings of the international conference on LCTES and SCOPES, Berlin, Germany","DOI":"10.1145\/513829.513853"},{"key":"5_CR2","volume-title":"Computers and intractability. A guide to the theory of NP-completeness","author":"M Garey","year":"1979","unstructured":"Garey M, Johnson D (1979) Computers and intractability. A guide to the theory of NP-completeness, W.H. Freeman and Company, New York"},{"key":"5_CR3","unstructured":"Benchmark Programs, DSP56000\/DSP56001 Digital Signal Processor User\u2019s Manual, Motorola INC., Semiconductor Products Sector, DSP Division, Austin Texas"},{"key":"5_CR4","unstructured":"Orvosh D, Davis L (1993) Shall we repair? Genetic algorithms, combinatorial optimization, and feasibility constraints. In: Proceedings of the fifth internatinal conference on genetic algorithms, Morgan Kaufmann, San Mateo, CA, p 650"},{"key":"5_CR5","doi-asserted-by":"crossref","unstructured":"Saghir M, Chow P, Lee C (1996) Exploiting dual data-memory banks in digital signal processors. In: Proceedings of the 7th international conference on architectural support for programming languages and operating systems, vol 30, no 5, pp 234\u2013243","DOI":"10.1145\/237090.237193"},{"key":"5_CR6","unstructured":"Saghir M, Chow P, Lee C (1995) Automatic data partitioning for HLL DSP compilers. In: Proceedings of the 7th international conference on signal processing applications and technology, pp I-658\u2013664"},{"key":"5_CR7","unstructured":"Sudarsanum A, Malik S (1997) Memory bank and register allocation in software synthesis for ASIPs. In: International conference on computer-aided design, pp 388\u2013392"},{"key":"5_CR8","doi-asserted-by":"crossref","unstructured":"Sudarsanam A, Malik S, Simultaneous reference allocation in code generation for dual data memory bank ASIPs. J ACM Trans Autom Electron Syst (TOADES) 5:242\u2013264","DOI":"10.1145\/335043.335047"},{"key":"5_CR9","doi-asserted-by":"crossref","unstructured":"Zhuge Q, Xiao B, Sha E (2002) Variable partitioning and scheduling of multiple memory architectures for DSP. In: Proceedings of the IEEE international parallel and distributed processing symposium (IPDPS)","DOI":"10.1109\/IPDPS.2002.1016516"},{"key":"5_CR10","unstructured":"Zivojnovic V, Velarde J, Schaeger C, Meyr H (1994) DSPstone\u2014A DSP oriented benchmarking methodology. In: Proceedings of the 6th international conference on signal processing applications and technology"}],"container-title":["Applied Intelligence"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10489-006-0005-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10489-006-0005-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10489-006-0005-3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,29]],"date-time":"2019-05-29T18:26:25Z","timestamp":1559154385000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10489-006-0005-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,11,29]]},"references-count":10,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2007,1,18]]}},"alternative-id":["5"],"URL":"https:\/\/doi.org\/10.1007\/s10489-006-0005-3","relation":{},"ISSN":["0924-669X","1573-7497"],"issn-type":[{"value":"0924-669X","type":"print"},{"value":"1573-7497","type":"electronic"}],"subject":[],"published":{"date-parts":[[2006,11,29]]}}}