{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,2]],"date-time":"2025-08-02T05:13:33Z","timestamp":1754111613045,"version":"3.37.3"},"reference-count":100,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2019,3,15]],"date-time":"2019-03-15T00:00:00Z","timestamp":1552608000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Cluster Comput"],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.1007\/s10586-019-02924-2","type":"journal-article","created":{"date-parts":[[2019,3,15]],"date-time":"2019-03-15T19:44:55Z","timestamp":1552679095000},"page":"321-346","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Network adapter architectures in network on chip: comprehensive literature review"],"prefix":"10.1007","volume":"23","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2209-9967","authenticated-orcid":false,"given":"Babak","family":"Aghaei","sequence":"first","affiliation":[]},{"given":"Midia","family":"Reshadi","sequence":"additional","affiliation":[]},{"given":"Mohammad","family":"Masdari","sequence":"additional","affiliation":[]},{"given":"Seyed Hadi","family":"Sajadi","sequence":"additional","affiliation":[]},{"given":"Mehdi","family":"Hosseinzadeh","sequence":"additional","affiliation":[]},{"given":"Aso","family":"Darwesh","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2019,3,15]]},"reference":[{"key":"2924_CR1","doi-asserted-by":"crossref","unstructured":"Chang, K.-C., Shen, J.-S., Chen, T.-F.: Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs. In: Proceedings of the 43rd annual Design Automation Conference, ACM, pp. 143\u2013148 (2006)","DOI":"10.1145\/1146909.1146950"},{"key":"2924_CR2","volume-title":"On-chip communication architectures: system on chip interconnect","author":"S Pasricha","year":"2010","unstructured":"Pasricha, S., Dutt, N.: On-chip communication architectures: system on chip interconnect. Morgan Kaufmann, Burlington (2010)"},{"key":"2924_CR3","unstructured":"Zeferino, C.A., Kreutz, M.E., Carro, L., Susin, A.A.: A study on communication issues for systems-on-chip. In: Integrated Circuits and Systems Design, 2002. In: Proceedings of the 15th Symposium, IEEE, pp. 121\u2013126 (2002)"},{"key":"2924_CR4","unstructured":"Liang, J., Swaminathan, S., Tessier, R.: aSOC: a scalable, single-chip communications architecture. In: Parallel Architectures and Compilation Techniques, 2000. In: Proceedings of the International Conference, IEEE, pp. 37\u201346 (2000)"},{"key":"2924_CR5","unstructured":"Dehyadgari, M., Nickray, M., Afzali-Kusha, A., Navabi, Z.: A new protocol stack model for network on chip. In: Proceeding of the IEEE Computer Society Annual Symposium Emerging VLSI Technologies and Architectures, IEEE, p. 3 (2006)"},{"issue":"1","key":"2924_CR6","first-page":"21","volume":"3","author":"A Agarwal","year":"2009","unstructured":"Agarwal, A., Iskander, C., Shankar, R.: Survey of network on chip (noc) architectures & contributions. J. Eng. Comput. Archit. 3(1), 21\u201327 (2009)","journal-title":"J. Eng. Comput. Archit."},{"key":"2924_CR7","unstructured":"De Micheli, G., Benini, L.: Networks on chip: a new paradigm for systems on chip design. In: Proceeding of the IEEE Computer Society on Design, Automation & Test in Europe Conference & Exhibition, pp. 0418\u20130418 (2002)"},{"key":"2924_CR8","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-4274-5","volume-title":"Designing 2D and 3D network-on-chip architectures","author":"K Tatas","year":"2014","unstructured":"Tatas, K., Siozios, K., Soudris, D., Jantsch, A.: Designing 2D and 3D network-on-chip architectures. Springer, New York (2014)"},{"issue":"1","key":"2924_CR9","doi-asserted-by":"publisher","first-page":"70","DOI":"10.1109\/2.976921","volume":"35","author":"L Benini","year":"2002","unstructured":"Benini, L., De Micheli, G.: Networks on chips: a new SoC paradigm. Computer 35(1), 70\u201378 (2002)","journal-title":"Computer"},{"key":"2924_CR10","unstructured":"Grecu, C., Ivanov, A., Saleh, R., De Micheli, G.: Design, synthesis, and test of networks on chips. (2005)"},{"key":"2924_CR11","volume-title":"Networks on chips: technology and tools","author":"G Micheli De","year":"2006","unstructured":"De Micheli, G., Benini, L.: Networks on chips: technology and tools. Academic Press, Cambridge (2006)"},{"key":"2924_CR12","unstructured":"Poluri, P., Louri, A.: A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-core Systems"},{"key":"2924_CR13","unstructured":"Kumar, S., Jantsch, A., Soininen, J.-P., Forsell, M., Millberg, M., Oberg, J., Tiensyrja, K., Hemani, A.: A network on chip architecture and design methodology. In: VLSI, 2002. In: Proceedings of the IEEE Computer Society Annual Symposium, IEEE, pp. 105\u2013112 (2002)"},{"key":"2924_CR14","doi-asserted-by":"publisher","DOI":"10.1007\/b105353","volume-title":"Networks on chip","author":"A Jantsch","year":"2003","unstructured":"Jantsch, A., Tenhunen, H.: Networks on chip, vol. 396. Springer, New York (2003)"},{"key":"2924_CR15","doi-asserted-by":"crossref","unstructured":"Goossens, K., Dielissen, J., van Meerbergen, J., Poplavko, P., R\u0103dulescu, A., Rijpkema, E., Waterlander, E., Wielage, P.: Guaranteeing the quality of services in networks on chip. In: Networks on chip. pp. 61-82. Springer, (2003)","DOI":"10.1007\/0-306-48727-6_4"},{"issue":"1","key":"2924_CR16","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1132952.1132953","volume":"38","author":"T Bjerregaard","year":"2006","unstructured":"Bjerregaard, T., Mahadevan, S.: A survey of research and practices of network-on-chip. ACM Comput. Surv. (CSUR) 38(1), 1 (2006)","journal-title":"ACM Comput. Surv. (CSUR)"},{"key":"2924_CR17","unstructured":"Hemani, A., Jantsch, A., Kumar, S., Postula, A., Oberg, J., Millberg, M., Lindqvist, D.: Network on chip: An architecture for billion transistor era. In: Proceeding of the IEEE NorChip Conference (2000)"},{"key":"2924_CR18","volume-title":"Principles and practices of interconnection networks","author":"WJ Dally","year":"2004","unstructured":"Dally, W.J., Towles, B.P.: Principles and practices of interconnection networks. Elsevier, Amsterdam (2004)"},{"key":"2924_CR19","unstructured":"Henkel, J., Wolf, W., Chakradhar, S.: On-chip networks: A scalable, communication-centric embedded system design paradigm. In: Proceedings 17th International Conference on VLSI Design, IEEE, pp. 845\u2013851 (2004)"},{"key":"2924_CR20","doi-asserted-by":"crossref","unstructured":"Ramanujam, R.S., Soteriou, V., Lin, B., Peh, L.-S.: Design of a high-throughput distributed shared-buffer NoC router. In: Proceeding of the 2010 Fourth ACM\/IEEE International Symposium on Networks-on-Chip (NOCS), IEEE, pp. 69\u201378 (2010)","DOI":"10.1109\/NOCS.2010.17"},{"key":"2924_CR21","doi-asserted-by":"crossref","unstructured":"Chan, C.-H., Tsai, K.-L., Lai, F., Tsai, S.-H.: A priority based output arbiter for NoC router. In: Proceedings of the Circuits and Systems (ISCAS) on IEEE International Symposium, IEEE, pp. 1928\u20131931 (2011)","DOI":"10.1109\/ISCAS.2011.5937966"},{"key":"2924_CR22","doi-asserted-by":"publisher","first-page":"105","DOI":"10.1007\/978-94-007-0638-5_8","volume-title":"Solutions on embedded systems","author":"S Saponara","year":"2011","unstructured":"Saponara, S., Vitullo, F., Petri, E., Fanucci, L., Coppola, M., Locatelli, R.: Coverage-driven verification of HDL IP cores. In: Conti, M. (ed.) Solutions on embedded systems, pp. 105\u2013119. Springer, New York (2011)"},{"key":"2924_CR23","doi-asserted-by":"crossref","unstructured":"Sgroi, M., Sheets, M., Mihal, A., Keutzer, K., Malik, S., Rabaey, J., Sangiovanni-Vencentelli, A.: Addressing the system-on-a-chip interconnect woes through communication-based design. In: Proceedings of the 38th annual Design Automation Conference, ACM, pp. 667\u2013672 (2001)","DOI":"10.1145\/378239.379045"},{"key":"2924_CR24","unstructured":"Bertozzi, D.: Network interface architecture and design issues. Networks on Chips: Technology and Tools, The Morgan Kaufmann Series in Systems on Silicon, pp.147\u2013202 (2006)"},{"issue":"4","key":"2924_CR25","doi-asserted-by":"publisher","first-page":"425","DOI":"10.1109\/TCOM.1980.1094702","volume":"28","author":"H Zimmermann","year":"1980","unstructured":"Zimmermann, H.: OSI reference model\u2013The ISO model of architecture for open systems interconnection. IEEE Trans. Commun. 28(4), 425\u2013432 (1980)","journal-title":"IEEE Trans. Commun."},{"key":"2924_CR26","doi-asserted-by":"crossref","unstructured":"Wang, J., Yang, Z.J.: Design of network adapter compatible OCP for high-throughput NOC. In: Applied Mechanics and Materials, pp. 1341\u20131346. Trans Tech Publ (2013)","DOI":"10.4028\/www.scientific.net\/AMM.313-314.1341"},{"key":"2924_CR27","doi-asserted-by":"crossref","unstructured":"Steenhof, F., Duque, H., Nilsson, B., Goossens, K., Llopis, R.P.: Networks on chips for high-end consumer-electronics TV system architectures. In: Proceedings of the conference on Design, automation and test in Europe: Designers\u2019 forum, European Design and Automation Association, pp. 148\u2013153 (2006)","DOI":"10.1109\/DATE.2006.243840"},{"key":"2924_CR28","doi-asserted-by":"crossref","unstructured":"Angiolini, F., Meloni, P., Carta, S., Benini, L., Raffo, L.: Contrasting a NoC and a traditional interconnect fabric with layout awareness. In: Proceedings of the conference on Design, automation and test in Europe, European Design and Automation Association, pp. 124\u2013129 (2006)","DOI":"10.1109\/DATE.2006.244033"},{"key":"2924_CR29","unstructured":"Alliance, O.: Open core protocol specification. In. Release, (2003)"},{"key":"2924_CR30","unstructured":"Alliance, V.: Virtual component interface standard. \nhttp:\/\/www.vsi.org\/library\/specs\/summary.html\n\n. (2001)"},{"key":"2924_CR31","doi-asserted-by":"crossref","unstructured":"Guerrier, P., Greiner, A.: A generic architecture for on-chip packet-switched interconnections. In: Proceedings of the conference on Design, automation and test in Europe, ACM, pp. 250\u2013256 (2000)","DOI":"10.1145\/343647.343776"},{"key":"2924_CR32","doi-asserted-by":"crossref","unstructured":"Ahonen, T., Sig\u00fcenza-Tortosa, D.A., Bin, H., Nurmi, J.: Topology optimization for application-specific networks-on-chip. In: Proceedings of the 2004 international workshop on System level interconnect prediction, ACM, pp. 53\u201360 (2004)","DOI":"10.1145\/966747.966758"},{"key":"2924_CR33","unstructured":"ARM, A.: AXI Protocol Specification, version 1.0 \nwww.arm.com\n\n, ARM. In. March, (2004)"},{"key":"2924_CR34","unstructured":"Radulescu, A., Dielissen, J., Goossens, K., Rijpkema, E., Wielage, P.: An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration. In: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, IEEE, pp. 878\u2013883 (2004)"},{"key":"2924_CR35","unstructured":"Opencores, S.: Wishbone system-on-chip (soc) interconnection architecture for portable ip cores. \nhttp:\/\/cdn.opencores.org\/downloads\/wbspec_b3.pdf\n\n (2002)"},{"key":"2924_CR36","volume-title":"Computer networks","author":"AS Tanenbaum","year":"2003","unstructured":"Tanenbaum, A.S.: Computer networks, 4th edn. Prentice Hall, Upper Saddle River (2003)","edition":"4"},{"key":"2924_CR37","doi-asserted-by":"crossref","unstructured":"Gangwal, O., R\u0103dulescu, A., Goossens, K., Gonz\u00e1lez Pestana, S., Rijpkema, E.: Building predictable systems on chip: An analysis of guaranteed communication in the \u00c6thereal network on chip. Dynamic and Robust Streaming in and between Connected Consumer-Electronic Devices, 1\u201336 (2005)","DOI":"10.1007\/1-4020-3454-7_1"},{"issue":"1","key":"2924_CR38","doi-asserted-by":"publisher","first-page":"4","DOI":"10.1109\/TCAD.2004.839493","volume":"24","author":"A Radulescu","year":"2005","unstructured":"Radulescu, A., Dielissen, J., Pestana, S.G., Gangwal, O.P., Rijpkema, E., Wielage, P., Goossens, K.: An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. Comput.-Aided Des. Integr. Circuits Syst. IEEE Trans. 24(1), 4\u201317 (2005)","journal-title":"Comput.-Aided Des. Integr. Circuits Syst. IEEE Trans."},{"key":"2924_CR39","unstructured":"Millberg, M., Nilsson, E., Thid, R., Kumar, S., Jantsch, A.: The Nostrum backbone-a communication protocol stack for networks on chip. In: Proceedings of the VLSI Design on 17th International Conference, IEEE, pp. 693\u2013696 (2004)"},{"key":"2924_CR40","doi-asserted-by":"crossref","unstructured":"Radulescu, A., Goossens, K.: Communication services for networks on chip. Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation, 193\u2013213 (2004)","DOI":"10.1201\/9780203913185.ch10"},{"issue":"1","key":"2924_CR41","doi-asserted-by":"publisher","first-page":"4","DOI":"10.1109\/TCAD.2004.839493","volume":"24","author":"A Radulescu","year":"2005","unstructured":"Radulescu, A., Dielissen, J., Pestana, S.G., Gangwal, O.P., Rijpkema, E., Wielage, P., Goossens, K.: An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1), 4\u201317 (2005)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"issue":"5","key":"2924_CR42","doi-asserted-by":"publisher","first-page":"414","DOI":"10.1109\/MDT.2005.99","volume":"22","author":"K Goossens","year":"2005","unstructured":"Goossens, K., Dielissen, J., Radulescu, A.: \u00c6thereal network on chip: concepts, architectures, and implementations. Des. Test Comput. IEEE 22(5), 414\u2013421 (2005)","journal-title":"Des. Test Comput. IEEE"},{"key":"2924_CR43","unstructured":"Scherrer, A., Fraboulet, A., Risset, T.: Hardware wrapper classification and requirements for on-chip interconnects. In: Signaux, Circuits et Syst\u00e8mes 2004, p. 4"},{"key":"2924_CR44","unstructured":"Chapiro, D.M.: Globally-Asynchronous Locally-Synchronous Systems. In. Stanford Univ CA Dept of Computer Science (1984)"},{"key":"2924_CR45","doi-asserted-by":"crossref","unstructured":"Dally, W.J., Seitz, C.L.: Deadlock-free message routing in multiprocessor interconnection networks. (1988)","DOI":"10.1109\/TC.1987.1676939"},{"key":"2924_CR46","doi-asserted-by":"crossref","unstructured":"Dally, W.J., Towles, B.: Route packets, not wires: On-chip interconnection networks. In: Proceedings of the Design Automation Conference, IEEE, pp. 684\u2013689 (2001)","DOI":"10.1145\/378239.379048"},{"key":"2924_CR47","doi-asserted-by":"crossref","unstructured":"Feige, U., Raghavan, P.: Exact analysis of hot-potato routing. In: Proceedings of the Foundations of Computer Science, 33rd Annual Symposium, IEEE, pp. 553\u2013562 (1992)","DOI":"10.1109\/SFCS.1992.267796"},{"issue":"7","key":"2924_CR48","doi-asserted-by":"publisher","first-page":"626","DOI":"10.1109\/71.707539","volume":"9","author":"E Fleury","year":"1998","unstructured":"Fleury, E., Fraigniaud, P.: A general theory for deadlock avoidance in wormhole-routed networks. IEEE Trans. Parallel Distrib. Syst. 9(7), 626\u2013638 (1998)","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"2924_CR49","doi-asserted-by":"crossref","unstructured":"Ciordas, C., Basten, T., Radulescu, A., Goossens, K., Meerbergen, J.: An event-based network-on-chip monitoring service. In: Proceedings of the High-Level Design Validation and Test Workshop on Ninth IEEE International, pp. 149\u2013154 (2004)","DOI":"10.1109\/HLDVT.2004.1431260"},{"key":"2924_CR50","doi-asserted-by":"publisher","first-page":"164","DOI":"10.1016\/j.micpro.2017.03.002","volume":"50","author":"J Sepulveda","year":"2017","unstructured":"Sepulveda, J., Fl\u00f3rez, D., Immler, V., Gogniat, G., Sigl, G.: Efficient security zones implementation through hierarchical group key management at NoC-based MPSoCs. Microprocess. Microsyst. 50, 164\u2013174 (2017)","journal-title":"Microprocess. Microsyst."},{"key":"2924_CR51","doi-asserted-by":"crossref","unstructured":"Fiorin, L., Silvano, C., Sami, M.: Security aspects in networks-on-chips: Overview and proposals for secure implementations. In: Proceedings of the Digital System Design Architectures, Methods and Tools. DSD 2007 on 10th Euromicro Conference, IEEE, pp. 539\u2013542 (2007)","DOI":"10.1109\/DSD.2007.4341520"},{"issue":"9","key":"2924_CR52","doi-asserted-by":"publisher","first-page":"1216","DOI":"10.1109\/TC.2008.69","volume":"57","author":"L Fiorin","year":"2008","unstructured":"Fiorin, L., Palermo, G., Lukovic, S., Catalano, V., Silvano, C.: Secure memory accesses on networks-on-chip. Comput. IEEE Trans. 57(9), 1216\u20131229 (2008)","journal-title":"Comput. IEEE Trans."},{"issue":"6","key":"2924_CR53","doi-asserted-by":"publisher","first-page":"2605","DOI":"10.1007\/s00034-013-9568-5","volume":"32","author":"HK Kapoor","year":"2013","unstructured":"Kapoor, H.K., Rao, G.B., Arshi, S., Trivedi, G.: A security framework for noc using authenticated encryption and session keys. Circuits Syst. Sign. Process. 32(6), 2605\u20132622 (2013)","journal-title":"Circuits Syst. Sign. Process."},{"key":"2924_CR54","doi-asserted-by":"crossref","unstructured":"Baron, S., Wangham, M.S., Zeferino, C.A.: Security mechanisms to improve the availability of a Network-on-Chip. In: Proceedings of the Electronics, Circuits, and Systems (ICECS) on IEEE 20th International Conference, pp. 609\u2013612 (2013)","DOI":"10.1109\/ICECS.2013.6815488"},{"key":"2924_CR55","doi-asserted-by":"crossref","unstructured":"Ghofrani, A., Parikh, R., Shamshiri, S., DeOrio, A., Cheng, K.-T., Bertacco, V.: Comprehensive online defect diagnosis in on-chip networks. In: VTS, pp. 44\u201349 (2012)","DOI":"10.1109\/VTS.2012.6231078"},{"issue":"9","key":"2924_CR56","first-page":"1374","volume":"14","author":"S Babaei","year":"2011","unstructured":"Babaei, S., Mansouri, M., Aghaei, B., Khadem-Zadeh, A.: Online-structural testing of routers in network on chip. World Applied Sci. J. 14(9), 1374\u20131383 (2011)","journal-title":"World Applied Sci. J."},{"key":"2924_CR57","doi-asserted-by":"crossref","unstructured":"Alaghi, A., Karimi, N., Sedghi, M., Navabi, Z.: Online NoC switch fault detection and diagnosis using a high level fault model. In: Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), IEEE, pp. 21\u201329 (2007)","DOI":"10.1109\/DFT.2007.55"},{"key":"2924_CR58","doi-asserted-by":"crossref","unstructured":"Alamian, S.S., Fallahzadeh, R., Hessabi, S., Alirezaie, J.: A novel test strategy and fault-tolerant routing algorithm for NoC routers. In: Proceedings of the 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013), IEEE, pp. 133\u2013136 (2013)","DOI":"10.1109\/CADS.2013.6714252"},{"key":"2924_CR59","series-title":"Availability and serviceability of networks-on-chip","first-page":"115","volume-title":"Reliability","author":"\u00c9 Cota","year":"2012","unstructured":"Cota, \u00c9., de Morais Amory, A., Lubaszewski, M.S.: Test and diagnosis of routers. In: Cota, \u00c9. (ed.) Reliability. Availability and serviceability of networks-on-chip, pp. 115\u2013132. Springer, New York (2012)"},{"key":"2924_CR60","doi-asserted-by":"crossref","unstructured":"Hosseinabady, M., Dalirsani, A., Navabi, Z.: Using the inter-and intra-switch regularity in NoC switch testing. In: Proceedings of the conference on Design, automation and test in Europe, pp. 361\u2013366. EDA Consortium (2007)","DOI":"10.1109\/DATE.2007.364618"},{"key":"2924_CR61","unstructured":"Nazari, M., Zolfy Lighvan, M., Daie Koozekonani, Z., Sadeghi, A.: a novel HW\/SW based NoC router self-testing methodology. \narXiv:1609.04569\n\n (2016)"},{"key":"2924_CR62","volume-title":"On-line testing of routers in networks-on-chip","author":"G Nazarian","year":"2008","unstructured":"Nazarian, G.: On-line testing of routers in networks-on-chip. Delft University of Technology, Delft (2008)"},{"key":"2924_CR63","doi-asserted-by":"publisher","first-page":"209","DOI":"10.1007\/s10836-017-5646-0","volume":"33","author":"B Aghaei","year":"2017","unstructured":"Aghaei, B., Khademzadeh, A., Reshadi, M., Badie, K.: Link testing: a survey of current trends in network on chip. J. Electron. Test. 33, 209\u2013225 (2017)","journal-title":"J. Electron. Test."},{"key":"2924_CR64","doi-asserted-by":"publisher","first-page":"5034","DOI":"10.1007\/s11227-017-2070-2","volume":"73","author":"B Aghaei","year":"2017","unstructured":"Aghaei, B., Badie, K., Khademzadeh, A., Reshadi, M.: The cost-effective fault detection and fault location approach for communication channels in NoC. J. Supercomput. 73, 5034\u20135052 (2017)","journal-title":"J. Supercomput."},{"key":"2924_CR65","doi-asserted-by":"publisher","first-page":"501","DOI":"10.1007\/s10836-017-5666-9","volume":"33","author":"B Aghaei","year":"2017","unstructured":"Aghaei, B., Khademzadeh, A., Reshadi, M., Badie, K.: A new BIST-based test approach with the fault location capability for communication channels in network-on-chip. J. Electron. Test. 33, 501\u2013513 (2017)","journal-title":"J. Electron. Test."},{"key":"2924_CR66","doi-asserted-by":"publisher","first-page":"178","DOI":"10.1016\/j.microrel.2017.07.010","volume":"75","author":"B Aghaei","year":"2017","unstructured":"Aghaei, B.: A high fault coverage test approach for communication channels in network on chip. Microelectron. Reliab. 75, 178\u2013186 (2017)","journal-title":"Microelectron. Reliab."},{"key":"2924_CR67","doi-asserted-by":"crossref","unstructured":"Aghaei, B., Babaei, S.: The new test wrapper design for core testing in Packet-Switched Micro-Network on Chip. In: Proceedings of the 2nd International Conference on Power Electronics and Intelligent Transportation System (PEITS), pp. 19\u201320 (2009)","DOI":"10.1109\/PEITS.2009.5406770"},{"issue":"3","key":"2924_CR68","doi-asserted-by":"publisher","first-page":"197","DOI":"10.1049\/iet-cdt:20060152","volume":"1","author":"AM Amory","year":"2007","unstructured":"Amory, A.M., Goossens, K., Marinissen, E.J., Lubaszewski, M., Moraes, F.: Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism. Comput Digit Tech IET 1(3), 197\u2013206 (2007)","journal-title":"Comput Digit Tech IET"},{"issue":"4","key":"2924_CR69","doi-asserted-by":"publisher","first-page":"471","DOI":"10.1145\/1027084.1027088","volume":"9","author":"\u00c9 Cota","year":"2004","unstructured":"Cota, \u00c9., Carro, L., Lubaszewski, M.: Reusing an on-chip network for the test of core-based systems. ACM Trans Des Autom Electron Syst (TODAES) 9(4), 471\u2013499 (2004)","journal-title":"ACM Trans Des Autom Electron Syst (TODAES)"},{"issue":"1","key":"2924_CR70","doi-asserted-by":"publisher","first-page":"135","DOI":"10.1109\/TCAD.2010.2066070","volume":"30","author":"D Xiang","year":"2011","unstructured":"Xiang, D., Zhang, Y.: Cost-effective power-aware core testing in NoCs based on a new unicast-based multicast scheme. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1), 135\u2013147 (2011)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"issue":"1","key":"2924_CR71","doi-asserted-by":"publisher","first-page":"16","DOI":"10.1109\/TDSC.2013.28","volume":"11","author":"L Fiorin","year":"2014","unstructured":"Fiorin, L., Sami, M.: Fault-Tolerant Network Interfaces for Networks-on-Chip. Depend Secure Comput. IEEE Trans. 11(1), 16\u201329 (2014)","journal-title":"Depend Secure Comput. IEEE Trans."},{"key":"2924_CR72","doi-asserted-by":"crossref","unstructured":"Thonnart, Y., Beign\u00e9, E., Vivet, P.: Design and implementation of a GALS adapter for ANoC based architectures. In: Proceedings of the Asynchronous Circuits and Systems on ASYNC\u201909 15th IEEE Symposium, IEEE, pp. 13\u201322 (2009)","DOI":"10.1109\/ASYNC.2009.13"},{"key":"2924_CR73","doi-asserted-by":"crossref","unstructured":"Matos, D., Carro, L., Susin, A.: Associating packets of heterogeneous cores using a synchronizer wrapper for NoCs. In: Proceedings of the Circuits and Systems (ISCAS) on IEEE International Symposium, IEEE, pp. 4177\u20134180 (2010)","DOI":"10.1109\/ISCAS.2010.5537596"},{"key":"2924_CR74","doi-asserted-by":"crossref","unstructured":"Fattah, M., Daneshtalab, M., Liljeberg, P., Plosila, J.: Transport layer aware design of network interface in many-core systems. In: Proceedings of the Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) on 7th International Workshop, IEEE, pp. 1\u20137 (2012)","DOI":"10.1109\/ReCoSoC.2012.6322895"},{"key":"2924_CR75","doi-asserted-by":"crossref","unstructured":"Lee, S.E., Bahn, J.H., Yang, Y.S., Bagherzadeh, N.: A generic network interface architecture for a networked processor array (NePA). In: Proceedings of the International Conference on Architecture of Computing Systems, pp. 247\u2013260. Springer (2008)","DOI":"10.1007\/978-3-540-78153-0_19"},{"key":"2924_CR76","doi-asserted-by":"crossref","unstructured":"Spars\u00f8, J., Kasapaki, E., Schoeberl, M.: An area-efficient network interface for a TDM-based network-on-chip. In: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 1044\u20131047. EDA Consortium (2013)","DOI":"10.7873\/DATE.2013.217"},{"key":"2924_CR77","doi-asserted-by":"crossref","unstructured":"Ruaro, M., Lazzarotto, F.B., Marcon, C.A., Moraes, F.G.: DMNI: A specialized network interface for NoC-based MPSoCs. In: Proceedings of the Circuits and Systems (ISCAS) on IEEE International Symposium, IEEE, pp. 1202\u20131205 (2016)","DOI":"10.1109\/ISCAS.2016.7527462"},{"key":"2924_CR78","doi-asserted-by":"crossref","unstructured":"Bjerregaard, T., Mahadevan, S., Olsen, R.G., Sparso, J.: An OCP compliant network adapter for GALS-based SoC design using the MANGO network-on-chip. In: Proceedings of the System-on-Chip on International Symposium, IEEE, pp. 171\u2013174 (2005)","DOI":"10.1109\/ISSOC.2005.1595670"},{"key":"2924_CR79","unstructured":"Bjerregaard, T., Sparso, J.: A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip. In: Proceedings of the Design, Automation and Test in Europe, IEEE, pp. 1226\u20131231 (2005)"},{"key":"2924_CR80","doi-asserted-by":"crossref","unstructured":"Fiorin, L., Palermo, G., Silvano, C.: A security monitoring service for NoCs. In: Proceedings of the 6th IEEE\/ACM\/IFIP International Conference on Hardware\/Software codesign and system synthesis, ACM, pp. 197\u2013202 (2008)","DOI":"10.1145\/1450135.1450180"},{"issue":"3\u20134","key":"2924_CR81","doi-asserted-by":"publisher","first-page":"168","DOI":"10.1504\/IJHPSA.2010.034538","volume":"2","author":"B Xia","year":"2010","unstructured":"Xia, B., Wu, K., Xiang, C., Yang, M., Liu, P., Yao, Q.: Network interface design based on mutual interface definition. Int. J. High Perform. Syst. Archit. 2(3\u20134), 168\u2013176 (2010)","journal-title":"Int. J. High Perform. Syst. Archit."},{"key":"2924_CR82","doi-asserted-by":"crossref","unstructured":"Attia, B., Wissem, C., Noureddine, A., Zitouni, A., Torki, K., Tourki, R.: A new pipelined network interface for Network on Chip with latency and jitter optimization. In: Proceedings of the Microelectronics (ICM) on International Conference, IEEE, pp. 1\u20136 (2011)","DOI":"10.1109\/ICM.2011.6177348"},{"key":"2924_CR83","doi-asserted-by":"crossref","unstructured":"Chouchene, W., Attia, B., Zitouni, A., Abid, N., Tourki, R.: A low power network interface for network on chip. In: Proceedings of the Systems, Signals and Devices (SSD) on 8th International Multi-Conference, IEEE, pp. 1\u20136 (2011)","DOI":"10.1109\/SSD.2011.5767464"},{"issue":"6","key":"2924_CR84","doi-asserted-by":"publisher","first-page":"1838","DOI":"10.1016\/j.compeleceng.2014.05.006","volume":"40","author":"K Swaminathan","year":"2014","unstructured":"Swaminathan, K., Lakshminarayanan, G., Ko, S.-B.: Design and verification of an efficient WISHBONE-based network interface for network on chip. Comput. Electr. Eng. 40(6), 1838\u20131857 (2014)","journal-title":"Comput. Electr. Eng."},{"key":"2924_CR85","unstructured":"Bhojwani, P., Mahapatra, R.: Interfacing cores with on-chip packet-switched networks. In: Proceedings of the VLSI Design on 16th International Conference, IEEE, pp. 382\u2013387 (2003)"},{"key":"2924_CR86","doi-asserted-by":"crossref","unstructured":"Lai, Y.-L., Yang, S.-W., Sheu, M.-H., Hwang, Y.-T., Tang, H.-Y., Huang, P.-Z.: A high-speed network interface design for packet-based NoC. In: Proceedings of the Communications, Circuits and Systems on International Conference, IEEE, pp. 2667\u20132671 (2006)","DOI":"10.1109\/ICCCAS.2006.285220"},{"key":"2924_CR87","unstructured":"Yang, X., Qing-li, Z., Fang-fa, F., Ming-yan, Y., Cheng, L.: NISAR: An AXI compliant on-chip NI architecture offering transaction reordering processing. In: Proceedings of the ASIC. ASICON\u201907. 7th International Conference, IEEE, pp. 890\u2013893 (2007)"},{"key":"2924_CR88","doi-asserted-by":"crossref","unstructured":"Ebrahimi, M., Daneshtalab, M., Liljeberg, P., Plosila, J., Tenhunen, H.: A high-performance network interface architecture for NoCs using reorder buffer sharing. In: Proceedings of the Parallel, Distributed and Network-Based Processing (PDP), 2010 18th Euromicro International Conference, IEEE, pp. 546\u2013550 (2010)","DOI":"10.1109\/PDP.2010.77"},{"key":"2924_CR89","doi-asserted-by":"crossref","unstructured":"Daneshtalab, M., Ebrahimi, M., Plosila, J., Tenhunen, H.: CARS: Congestion-aware request scheduler for network interfaces in NoC-based manycore systems. In: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 1048\u20131051. EDA Consortium (2013)","DOI":"10.7873\/DATE.2013.218"},{"issue":"8","key":"2924_CR90","doi-asserted-by":"publisher","first-page":"1650","DOI":"10.1587\/transfun.E100.A.1650","volume":"100","author":"X-T Tran","year":"2017","unstructured":"Tran, X.-T., Nguyen, T., Phan, H.-P., Bui, D.-H.: AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures. IEICE Trans. Fund. Electron. Commun. Comput. Sci. 100(8), 1650\u20131660 (2017)","journal-title":"IEICE Trans. Fund. Electron. Commun. Comput. Sci."},{"key":"2924_CR91","doi-asserted-by":"crossref","unstructured":"Hu, J., Marculescu, R.: Energy-aware mapping for tile-based NoC architectures under performance constraints. In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ACM, pp. 233\u2013239 (2003)","DOI":"10.1145\/1119772.1119818"},{"issue":"1","key":"2924_CR92","doi-asserted-by":"publisher","first-page":"29","DOI":"10.1109\/JSSC.2007.910957","volume":"43","author":"SR Vangal","year":"2008","unstructured":"Vangal, S.R., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Singh, A., Jacob, T., Jain, S.: An 80-tile sub-100-w teraflops processor in 65-nm cmos. IEEE J. Solid-State Circuits 43(1), 29\u201341 (2008)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"2924_CR93","unstructured":"Bhojwani, P., Mahapatra, R.N.: Core network interface architecture and latency constrained on-chip communication. In: Proceeding of the Quality Electronic Design on ISQED\u201906. 7th International Symposium, IEEE, pp. 6\u2013363 (2006)"},{"key":"2924_CR94","doi-asserted-by":"crossref","unstructured":"Ost, L., Mello, A., Palma, J., Moraes, F., Calazans, N.: MAIA: a framework for networks on chip generation and verification. In: Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ACM, pp. 49\u201352 (2005)","DOI":"10.1145\/1120725.1120741"},{"key":"2924_CR95","doi-asserted-by":"crossref","unstructured":"Fiorin, L., Palermo, G., Lukovic, S., Silvano, C.: A data protection unit for NoC-based architectures. In: Proceedings of the 5th IEEE\/ACM international conference on Hardware\/software codesign and system synthesis, ACM, pp. 167\u2013172 (2007)","DOI":"10.1145\/1289816.1289858"},{"issue":"5","key":"2924_CR96","doi-asserted-by":"publisher","first-page":"404","DOI":"10.1109\/MDT.2005.108","volume":"22","author":"PP Pande","year":"2005","unstructured":"Pande, P.P., Grecu, C., Ivanov, A., Saleh, R., De Micheli, G.: Design, synthesis, and test of networks on chips. IEEE Des. Test Comput. 22(5), 404\u2013413 (2005)","journal-title":"IEEE Des. Test Comput."},{"key":"2924_CR97","doi-asserted-by":"crossref","unstructured":"Furber, S., Bainbridge, J.: Future trends in SoC interconnect. In: Proceedings of the System-on-Chip, International Symposium, IEEE, pp. 183\u2013186 (2005)","DOI":"10.1109\/ISSOC.2005.1595673"},{"key":"2924_CR98","doi-asserted-by":"publisher","first-page":"147","DOI":"10.1007\/978-1-4614-4274-5_6","volume-title":"Designing 2D and 3D network-on-chip architectures","author":"K Tatas","year":"2014","unstructured":"Tatas, K., Siozios, K., Soudris, D., Jantsch, A.: NoC Verification and Testing. In: Jantsh, A. (ed.) Designing 2D and 3D network-on-chip architectures, pp. 147\u2013159. Springer, New York (2014)"},{"issue":"8","key":"2924_CR99","doi-asserted-by":"publisher","first-page":"1344","DOI":"10.1109\/TCAD.2015.2448684","volume":"34","author":"MD Grammatikakis","year":"2015","unstructured":"Grammatikakis, M.D., Papadimitriou, K., Petrakis, P., Papagrigoriou, A., Kornaros, G., Christoforakis, I., Tomoutzoglou, O., Tsamis, G., Coppola, M.: Security in MPSoCs: a NoC firewall and an evaluation framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(8), 1344\u20131357 (2015)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"2924_CR100","unstructured":"Compiler, S.D.: Synopsys Corporation. In. (1999)"}],"container-title":["Cluster Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10586-019-02924-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10586-019-02924-2\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10586-019-02924-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,3,14]],"date-time":"2020-03-14T00:18:57Z","timestamp":1584145137000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10586-019-02924-2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3,15]]},"references-count":100,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2020,3]]}},"alternative-id":["2924"],"URL":"https:\/\/doi.org\/10.1007\/s10586-019-02924-2","relation":{},"ISSN":["1386-7857","1573-7543"],"issn-type":[{"type":"print","value":"1386-7857"},{"type":"electronic","value":"1573-7543"}],"subject":[],"published":{"date-parts":[[2019,3,15]]},"assertion":[{"value":"3 December 2017","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"2 January 2019","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"9 March 2019","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"15 March 2019","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}