{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T16:46:43Z","timestamp":1780332403743,"version":"3.54.1"},"reference-count":70,"publisher":"Springer Science and Business Media LLC","issue":"5","license":[{"start":{"date-parts":[[2025,4,28]],"date-time":"2025-04-28T00:00:00Z","timestamp":1745798400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"},{"start":{"date-parts":[[2025,4,28]],"date-time":"2025-04-28T00:00:00Z","timestamp":1745798400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"}],"funder":[{"name":"Kadir Has University"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Cluster Comput"],"published-print":{"date-parts":[[2025,8]]},"abstract":"<jats:title>Abstract<\/jats:title>\n          <jats:p>Signal processing had a significant impact on the development of many elements of modern life, including telecommunications, education, healthcare, industry, and security. The semiconductor industry is the primary driver of signal processing innovation, producing ever-more sophisticated electronic devices and circuits in response to global demand. In addition, the central processing unit (CPU) is described as the \u201cbrain\u201d of a computer or all electronic devices and signal processing. CPU is a critical electronic device that includes vital components such as memory, multiplier, adder, etc. Also, one of the essential components of the CPU is the arithmetic and logic unit (ALU), which executes the arithmetic and logical operations within all types of CPU operations, such as addition, multiplication, and subtraction. However, delay, occupied areas, and energy consumption are essential parameters in ALU circuits. Since the recent ALU designs experienced problems like high delay, high occupied area, and high energy consumption, implementing electronic circuits based on new technology can significantly boost the performance of entire signal processing devices, including microcontrollers, microprocessors, and printed devices, with high-speed and low occupied space. Quantum dot cellular automata (QCA) is an effective technology for implementing all electronic circuits and signal processing applications to solve these shortcomings. It is a transistor-less nanotechnology being explored as a successor to established technologies like CMOS and VLSI due to its ultra-low power dissipation, high device density, fast operating speed in THz, and reduced circuit complexity. This research proposes a ground-breaking ALU that upgrades electrical devices such as microcontrollers by applying cutting-edge QCA nanotechnology. The primary goal is to offer a novel ALU architecture that fully utilizes the potential of QCA nanotechnology. Using a new and efficient approach, the fundamental gates are skillfully utilized with a coplanar layout based on a single cell not rotated. Furthermore, this work presents an enhanced 1-bit and 2-bit arithmetic logic unit in quantum dot cellular automata. The recommended design includes logic, arithmetic operations, full adder (FA) design, and multiplexers. Using the powerful simulation tools QCADesigner, all proposed designs are evaluated and verified. The simulation outcomes indicates that the suggested ALU has 42.48 and 64.28% improvements concerning cell count and total occupied area in comparison to the best earlier single-layer and multi-layer designs.<\/jats:p>","DOI":"10.1007\/s10586-024-05073-3","type":"journal-article","created":{"date-parts":[[2025,4,28]],"date-time":"2025-04-28T15:21:28Z","timestamp":1745853688000},"update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":25,"title":["A nano-scale design of arithmetic and logic unit for energy-efficient signal processing devices based on a quantum-based technology"],"prefix":"10.1007","volume":"28","author":[{"given":"Muhammad","family":"Zohaib","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nima Jafari","family":"Navimipour","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mehmet Timur","family":"Aydemir","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Seyed-Sajad","family":"Ahmadpour","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2025,4,28]]},"reference":[{"key":"5073_CR1","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9781139172837","volume-title":"A Practical Introduction to Electronic Circuits","author":"MH Jones","year":"1995","unstructured":"Jones, M.H.: A Practical Introduction to Electronic Circuits. Cambridge University Press, Cambridge (1995)"},{"key":"5073_CR2","volume-title":"Electronic Circuits: Handbook for Design and Application","author":"U Tietze","year":"2015","unstructured":"Tietze, U., Schenk, C., Gamm, E.: Electronic Circuits: Handbook for Design and Application. Springer, Cham (2015)"},{"key":"5073_CR3","doi-asserted-by":"publisher","DOI":"10.1201\/9781420039559","volume-title":"Low-Power Electronics Design","author":"C Piguet","year":"2018","unstructured":"Piguet, C.: Low-Power Electronics Design. CRC Press, Boca Raton (2018)"},{"key":"5073_CR4","doi-asserted-by":"crossref","unstructured":"Ursu\u0163iu, D., et al.: Microcontroller technologies in low power applications. In: 2012 15th International Conference on Interactive Collaborative Learning (ICL) (2012). IEEE","DOI":"10.1109\/ICL.2012.6402096"},{"key":"5073_CR5","doi-asserted-by":"crossref","unstructured":"Y\u0131ld\u0131z, A., et al.: CPU design simplified. In: 2018 3rd International Conference on Computer Science and Engineering (UBMK) (2018). IEEE","DOI":"10.1109\/UBMK.2018.8566475"},{"issue":"2","key":"5073_CR6","doi-asserted-by":"publisher","first-page":"1908","DOI":"10.1007\/s11227-022-04740-9","volume":"79","author":"RKR Venna","year":"2023","unstructured":"Venna, R.K.R., Jayakumar, G.D.: Design of novel area-efficient coplanar reversible arithmetic and logic unit with an energy estimation in quantum-dot cellular automata. J. Supercomput. 79(2), 1908\u20131925 (2023)","journal-title":"J. Supercomput."},{"issue":"1","key":"5073_CR7","doi-asserted-by":"publisher","first-page":"1","DOI":"10.13189\/ujeee.2019.060101","volume":"6","author":"JR Shinde","year":"2019","unstructured":"Shinde, J.R., Shinde, S.J.: An optimization design strategy for arithmetic logic unit. Univers. J. Electr. Electron. Eng. 6(1), 1\u201313 (2019)","journal-title":"Univers. J. Electr. Electron. Eng."},{"key":"5073_CR8","doi-asserted-by":"crossref","unstructured":"Kalpana, K., et al.: A novel design of nano scale TIEO based single layer full adder and full subractor in QCA paradigm. In: 2021 5th International Conference on Intelligent Computing and Control Systems (ICICCS) (2021). IEEE","DOI":"10.1109\/ICICCS51141.2021.9432098"},{"issue":"7","key":"5073_CR9","doi-asserted-by":"publisher","first-page":"392","DOI":"10.1002\/jcc.27247","volume":"45","author":"N Liza","year":"2024","unstructured":"Liza, N., et al.: Ab initio studies of counterion effects in molecular quantum-dot cellular automata. J. Comput. Chem. 45(7), 392\u2013404 (2024)","journal-title":"J. Comput. Chem."},{"key":"5073_CR10","doi-asserted-by":"crossref","unstructured":"Das, J. C., De, D. (2017). Circuit switching with quantum-dot cellular automata. Nano Commun. Netw. 14, 16\u201328","DOI":"10.1016\/j.nancom.2017.09.002"},{"issue":"1","key":"5073_CR11","doi-asserted-by":"publisher","first-page":"190","DOI":"10.1038\/s41598-023-49700-2","volume":"14","author":"M Repe","year":"2024","unstructured":"Repe, M., Koli, S.: Novel energy efficient RND inverter using quantum dot cellular automata in nanotechnology. Sci. Rep. 14(1), 190 (2024)","journal-title":"Sci. Rep."},{"key":"5073_CR12","doi-asserted-by":"crossref","unstructured":"Das, J. C., De, D.: Quantum dot-cellular automata based cipher text design for nano-communication. In: 2012 International Conference on Radar, Communication and Computing (ICRCC), pp. 224-229 (2012). IEEE","DOI":"10.1109\/ICRCC.2012.6450583"},{"key":"5073_CR13","unstructured":"Mehta, U., Dhare, V.: Quantum-dot cellular automata (QCA): a survey. arXiv preprint arXiv:1711.08153 (2017)"},{"key":"5073_CR14","doi-asserted-by":"publisher","DOI":"10.1016\/j.nancom.2023.100482","volume":"39","author":"NK Misra","year":"2024","unstructured":"Misra, N.K., Bhoi, B.K., Kassa, S.R.: Utilizing a novel universal quantum gate in the design of fault-tolerant architecture. Nano Commun. Netw. 39, 100482 (2024)","journal-title":"Nano Commun. Netw."},{"issue":"14","key":"5073_CR15","doi-asserted-by":"publisher","first-page":"3189","DOI":"10.3390\/electronics12143189","volume":"12","author":"A Yan","year":"2023","unstructured":"Yan, A., et al.: Designs of array multipliers with an optimized delay in quantum-dot cellular automata. Electronics 12(14), 3189 (2023)","journal-title":"Electronics"},{"key":"5073_CR16","doi-asserted-by":"crossref","unstructured":"Ahmad, F., Ahmed, S., Kakkar, V., Bhat, G. M., Bahar, A. N., Wani, S.: Modular design of ultra-efficient reversible full adder-subtractor in QCA with power dissipation analysis. Int. J. Theor. Phys. 57, 2863\u20132880 (2018)","DOI":"10.1007\/s10773-018-3806-3"},{"key":"5073_CR17","unstructured":"Khan, A., Arya, R.: High performance nanocomparator: a quantum dot cellular automata-based approach. J. Supercomput. 1\u201317 (2022)"},{"key":"5073_CR18","doi-asserted-by":"crossref","unstructured":"Srivastava, S., et al.: QCAPro-an error-power estimation tool for QCA circuit design. In: 2011 IEEE international symposium of circuits and systems (ISCAS) (2011). IEEE","DOI":"10.1109\/ISCAS.2011.5938081"},{"key":"5073_CR19","doi-asserted-by":"crossref","unstructured":"Patidar, M., Gupta, N.: Optimal energy estimation of toffoli and peres gate design using quantum-dot cellular automata. Res. Sq. 1\u201316 (2021)","DOI":"10.21203\/rs.3.rs-233233\/v1"},{"issue":"2","key":"5073_CR20","doi-asserted-by":"publisher","first-page":"115","DOI":"10.1140\/epjp\/s13360-024-04901-0","volume":"139","author":"M Ebrahimy","year":"2024","unstructured":"Ebrahimy, M., et al.: A novel low-latency ALU in the one-dimensional clock scheme in QCA nanotechnology. Eur. Phys. J. Plus 139(2), 115 (2024)","journal-title":"Eur. Phys. J. Plus"},{"issue":"12","key":"5073_CR21","doi-asserted-by":"publisher","first-page":"10155","DOI":"10.1007\/s11227-020-03249-3","volume":"76","author":"S-S Ahmadpour","year":"2020","unstructured":"Ahmadpour, S.-S., Mosleh, M., Rasouli Heikalabad, S.: The design and implementation of a robust single-layer QCA ALU using a novel fault-tolerant three-input majority gate. J. Supercomput. 76(12), 10155\u201310185 (2020)","journal-title":"J. Supercomput."},{"key":"5073_CR22","doi-asserted-by":"crossref","unstructured":"Navimpour, N.J., Ahmadpour, S.-S., Yalcin, S.: An Ultra-Efficient Nano-Scale Arithmetic and Logic Unit Using a New Conservative Reversible Block and Quantum-Dots (2022)","DOI":"10.21203\/rs.3.rs-2213495\/v1"},{"issue":"1","key":"5073_CR23","doi-asserted-by":"publisher","first-page":"395","DOI":"10.1007\/s11227-023-05491-x","volume":"80","author":"NJ Navimipour","year":"2024","unstructured":"Navimipour, N.J., Ahmadpour, S.-S., Yalcin, S.: A nano-scale arithmetic and logic unit using a reversible logic and quantum-dots. J. Supercomput. 80(1), 395\u2013412 (2024)","journal-title":"J. Supercomput."},{"key":"5073_CR24","doi-asserted-by":"publisher","DOI":"10.1016\/j.ijleo.2022.169258","volume":"262","author":"A Abbasizadeh","year":"2022","unstructured":"Abbasizadeh, A., Mosleh, M., Ahmadpour, S.-S.: An optimized arithmetic logic unit in quantum-dot cellular automata (QCA) technology. Optik 262, 169258 (2022)","journal-title":"Optik"},{"key":"5073_CR25","doi-asserted-by":"publisher","DOI":"10.1016\/j.nancom.2024.100498","volume":"40","author":"S Nemattabar","year":"2024","unstructured":"Nemattabar, S., et al.: Advancing nanoscale computing: efficient reversible ALU in quantum-dot cellular automata. Nano Commun. Netw. 40, 100498 (2024)","journal-title":"Nano Commun. Netw."},{"key":"5073_CR26","unstructured":"Deivasigamani, M.: A systematic design approach for a novel energy efficient ALU for 8-bit QCA microcontroller (2024)"},{"issue":"17","key":"5073_CR27","doi-asserted-by":"publisher","first-page":"2445","DOI":"10.3390\/nano13172445","volume":"13","author":"M Alharbi","year":"2023","unstructured":"Alharbi, M., Edwards, G., Stocker, R.: Reversible quantum-dot cellular automata-based arithmetic logic unit. Nanomaterials 13(17), 2445 (2023)","journal-title":"Nanomaterials"},{"issue":"8","key":"5073_CR28","doi-asserted-by":"publisher","first-page":"8265","DOI":"10.1007\/s11227-022-05012-2","volume":"79","author":"M Patidar","year":"2023","unstructured":"Patidar, M., et al.: An ultra-area-efficient ALU design in QCA technology using synchronized clock zone scheme. J. Supercomput. 79(8), 8265\u20138294 (2023)","journal-title":"J. Supercomput."},{"issue":"12","key":"5073_CR29","doi-asserted-by":"publisher","first-page":"13601","DOI":"10.1007\/s11227-021-03767-8","volume":"77","author":"R Roy","year":"2021","unstructured":"Roy, R., Sarkar, S., Dhar, S.: Design and testing of a reversible ALU by quantum cells automata electro-spin technology. J. Supercomput. 77(12), 13601\u201313628 (2021)","journal-title":"J. Supercomput."},{"issue":"8","key":"5073_CR30","doi-asserted-by":"publisher","first-page":"1291","DOI":"10.1002\/cta.2799","volume":"48","author":"M Norouzi","year":"2020","unstructured":"Norouzi, M., Heikalabad, S.R., Salimzadeh, F.: A reversible ALU using HNG and Ferdkin gates in QCA nanotechnology. Int. J. Circuit Theory Appl. 48(8), 1291\u20131303 (2020)","journal-title":"Int. J. Circuit Theory Appl."},{"key":"5073_CR31","doi-asserted-by":"publisher","first-page":"376","DOI":"10.1016\/j.mspro.2015.11.133","volume":"11","author":"S Hashemi","year":"2015","unstructured":"Hashemi, S., Navi, K.: A novel robust QCA full-adder. Proc. Mater. Sci. 11, 376\u2013380 (2015)","journal-title":"Proc. Mater. Sci."},{"key":"5073_CR32","doi-asserted-by":"publisher","first-page":"35","DOI":"10.1016\/j.mejo.2016.02.004","volume":"50","author":"M Mohammadi","year":"2016","unstructured":"Mohammadi, M., Mohammadi, M., Gorgin, S.: An efficient design of full adder in quantum-dot cellular automata (QCA) technology. Microelectron. J. 50, 35\u201343 (2016)","journal-title":"Microelectron. J."},{"key":"5073_CR33","unstructured":"Patidar, M., Jain, A., Tiwari, A., Mandloi, D. S., Namdeo, S. K., Paranjpe, P.: An ultra-area-efficient full adder circuits design based on nanoscale QCA technology. Des. Eng. 3713\u20133728 (2021)"},{"key":"5073_CR34","doi-asserted-by":"crossref","unstructured":"Mukherjee, C., Sukla, A. S., Basu, S. S., Chakrabarty, R., Khan, A., De, D.: Layered T full adder using quantum-dot cellular automata. In: 2015 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), pp. 1-6 (2015). IEEE","DOI":"10.1109\/CONECCT.2015.7383867"},{"issue":"04","key":"5073_CR35","doi-asserted-by":"publisher","first-page":"641","DOI":"10.1142\/S0218126611007517","volume":"20","author":"RF Mirzaee","year":"2011","unstructured":"Mirzaee, R.F., et al.: A new robust and high-performance hybrid full adder cell. J. Circuits Syst. Comput. 20(04), 641\u2013655 (2011)","journal-title":"J. Circuits Syst. Comput."},{"key":"5073_CR36","doi-asserted-by":"crossref","unstructured":"Patidar, M., Bhanodia, P. K., Rajput, S., Patel, S., Gupta, K., Sethi, K. K., Khamparia, A.: Efficient design of half-adders and EXOR gates for energy-efficient quantum computing with delay analysis using quantum-dot cellular automata technology. In :International Conference on Artificial Intelligence of Things for Smart Societies, pp. 211\u2013217 (2024). Cham: Springer Nature Switzerland","DOI":"10.1007\/978-3-031-63103-0_22"},{"issue":"7","key":"5073_CR37","doi-asserted-by":"publisher","first-page":"345","DOI":"10.1109\/TCSII.2004.831429","volume":"51","author":"Y Jiang","year":"2004","unstructured":"Jiang, Y., et al.: A novel multiplexer-based low-power full adder. IEEE Trans. Circuits Syst. II Express Briefs 51(7), 345\u2013348 (2004)","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"issue":"2","key":"5073_CR38","doi-asserted-by":"publisher","first-page":"1672","DOI":"10.1007\/s11227-021-03913-2","volume":"78","author":"S-S Ahmadpour","year":"2022","unstructured":"Ahmadpour, S.-S., Mosleh, M., Rasouli Heikalabad, S.: Efficient designs of quantum-dot cellular automata multiplexer and RAM with physical proof along with power analysis. J. Supercomput. 78(2), 1672\u20131695 (2022)","journal-title":"J. Supercomput."},{"issue":"3","key":"5073_CR39","doi-asserted-by":"publisher","first-page":"602","DOI":"10.1002\/cta.2096","volume":"44","author":"G Cocorullo","year":"2016","unstructured":"Cocorullo, G., et al.: Design of efficient QCA multiplexers. Int. J. Circuit Theory Appl. 44(3), 602\u2013615 (2016)","journal-title":"Int. J. Circuit Theory Appl."},{"key":"5073_CR40","doi-asserted-by":"crossref","unstructured":"Naz, S. F., Ahmed, S., Mughal, S. N., Asger, M., Das, J. C., Mallik, S., Shah, M. A.: Optimizing fault tolerance of RAM cell through MUX based modeling and design using symmetries of QCA cells. Sci. Rep. 14(1), 8586 (2024)","DOI":"10.1038\/s41598-024-59185-2"},{"key":"5073_CR41","doi-asserted-by":"crossref","unstructured":"Khan, A., Mandal, S., Nag, S., Chakrabarty, R.: Efficient multiplexer design and analysis using quantum dot cellular automata. In: 2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), pp. 163\u2013168 (2016). IEEE","DOI":"10.1109\/DISCOVER.2016.7806233"},{"issue":"13","key":"5073_CR42","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.5070","volume":"31","author":"M Mosleh","year":"2019","unstructured":"Mosleh, M.: A novel design of multiplexer based on nano-scale quantum-dot cellular automata. Concurr. Comput. Pract. Exp. 31(13), e5070 (2019)","journal-title":"Concurr. Comput. Pract. Exp."},{"key":"5073_CR43","unstructured":"Rao, S., et al.: Implementation of ALU on FPGA. of, 2022. 6, 4"},{"key":"5073_CR44","unstructured":"Albishri, A.S.: Design & development of a high-speed performance ALU by using execution modes and multi-operand operation. Fahd Bin Sultan University (2023)"},{"issue":"3","key":"5073_CR45","doi-asserted-by":"publisher","first-page":"374","DOI":"10.1109\/TNANO.2007.894839","volume":"6","author":"H Cho","year":"2007","unstructured":"Cho, H., Swartzlander, E.E.: Adder designs and analyses for quantum-dot cellular automata. IEEE Trans. Nanotechnol. 6(3), 374\u2013383 (2007)","journal-title":"IEEE Trans. Nanotechnol."},{"key":"5073_CR46","doi-asserted-by":"crossref","unstructured":"Bishnoi, B., et al.: Ripple carry adder using five input majority gates. In: 2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC) (2012). IEEE","DOI":"10.1109\/EDSSC.2012.6482894"},{"key":"5073_CR47","unstructured":"Cho, H.: Adder and multiplier design and analysis in quantum-dot cellular automata. The University of Texas at Austin (2006)"},{"issue":"1","key":"5073_CR48","doi-asserted-by":"publisher","first-page":"105","DOI":"10.1109\/TNANO.2011.2158006","volume":"11","author":"V Pudi","year":"2011","unstructured":"Pudi, V., Sridharan, K.: Low complexity design of ripple carry and Brent-Kung adders in QCA. IEEE Trans. Nanotechnol. 11(1), 105\u2013119 (2011)","journal-title":"IEEE Trans. Nanotechnol."},{"issue":"6","key":"5073_CR49","doi-asserted-by":"publisher","first-page":"721","DOI":"10.1109\/TC.2009.21","volume":"58","author":"H Cho","year":"2009","unstructured":"Cho, H., Swartzlander, E.E.: Adder and multiplier design in quantum-dot cellular automata. IEEE Trans. Comput. 58(6), 721\u2013727 (2009)","journal-title":"IEEE Trans. Comput."},{"issue":"1","key":"5073_CR50","doi-asserted-by":"publisher","first-page":"176","DOI":"10.1109\/TCAD.2006.883921","volume":"26","author":"K Kim","year":"2006","unstructured":"Kim, K., Wu, K., Karri, R.: The robust QCA adder designs using composable QCA building blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1), 176\u2013183 (2006)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"issue":"4","key":"5073_CR51","doi-asserted-by":"publisher","first-page":"443","DOI":"10.1109\/TNANO.2004.834177","volume":"3","author":"R Zhang","year":"2004","unstructured":"Zhang, R., et al.: A method of majority logic reduction for quantum cellular automata. IEEE Trans. Nanotechnol. 3(4), 443\u2013450 (2004)","journal-title":"IEEE Trans. Nanotechnol."},{"key":"5073_CR52","unstructured":"Wang, W., Walus, K., Jullien, G.A.: Quantum-dot cellular automata adders. In: 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003 (2003). IEEE"},{"key":"5073_CR53","doi-asserted-by":"publisher","first-page":"87","DOI":"10.1007\/s11265-008-0284-5","volume":"58","author":"I H\u00e4nninen","year":"2010","unstructured":"H\u00e4nninen, I., Takala, J.: Binary adders on quantum-dot cellular automata. J. Signal Process. Syst. 58, 87\u2013103 (2010)","journal-title":"J. Signal Process. Syst."},{"issue":"2","key":"5073_CR54","doi-asserted-by":"publisher","first-page":"259","DOI":"10.1166\/jolpe.2014.1320","volume":"10","author":"S Angizi","year":"2014","unstructured":"Angizi, S., et al.: Novel robust single layer wire crossing approach for exclusive or sum of products logic design with quantum-dot cellular automata. J. Low Power Electron. 10(2), 259\u2013271 (2014)","journal-title":"J. Low Power Electron."},{"issue":"12","key":"5073_CR55","doi-asserted-by":"publisher","first-page":"820","DOI":"10.1016\/j.mejo.2010.07.003","volume":"41","author":"K Navi","year":"2010","unstructured":"Navi, K., et al.: A new quantum-dot cellular automata full-adder. Microelectron. J. 41(12), 820\u2013826 (2010)","journal-title":"Microelectron. J."},{"key":"5073_CR56","doi-asserted-by":"publisher","first-page":"42","DOI":"10.1016\/j.compeleceng.2015.05.001","volume":"45","author":"B Sen","year":"2015","unstructured":"Sen, B., et al.: Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers. Comput. Electr. Eng. 45, 42\u201354 (2015)","journal-title":"Comput. Electr. Eng."},{"key":"5073_CR57","doi-asserted-by":"crossref","unstructured":"Teod\u00f3sio, T., Sousa, L.: QCA-LG: A tool for the automatic layout generation of QCA combinational circuits. In: Norchip 2007. IEEE (2007)","DOI":"10.1109\/NORCHP.2007.4481078"},{"key":"5073_CR58","unstructured":"Mardiris, V., et al.: Design and simulation of a QCA 2 to 1 multiplexer. In: 12th WSEAS International Conference on Computers, Heraklion, Greece (2008)"},{"issue":"8","key":"5073_CR59","doi-asserted-by":"publisher","first-page":"771","DOI":"10.1002\/cta.595","volume":"38","author":"VA Mardiris","year":"2010","unstructured":"Mardiris, V.A., Karafyllidis, I.G.: Design and simulation of modular 2n to 1 quantum-dot cellular automata (QCA) multiplexers. Int. J. Circuit Theory Appl. 38(8), 771\u2013785 (2010)","journal-title":"Int. J. Circuit Theory Appl."},{"issue":"12","key":"5073_CR60","doi-asserted-by":"publisher","first-page":"929","DOI":"10.1016\/j.mejo.2012.10.007","volume":"43","author":"S Hashemi","year":"2012","unstructured":"Hashemi, S., Navi, K.: New robust QCA D flip flop and memory structures. Microelectron. J. 43(12), 929\u2013940 (2012)","journal-title":"Microelectron. J."},{"issue":"1","key":"5073_CR61","doi-asserted-by":"publisher","first-page":"34","DOI":"10.1109\/TCAD.2007.907020","volume":"27","author":"V Vankamamidi","year":"2007","unstructured":"Vankamamidi, V., Ottavi, M., Lombardi, F.: Two-dimensional schemes for clocking\/timing of QCA circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1), 34\u201344 (2007)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"5073_CR62","unstructured":"Sen, B., et al.: An efficient multiplexer in quantum-dot cellular automata. In: Progress in VLSI Design and Test: 16th International Symposium, VDAT 2012, Shibpur, India, July 1\u20134, 2012. Proceedings. Springer, Cham (2012)"},{"issue":"2","key":"5073_CR63","first-page":"35","volume":"8","author":"N Gupta","year":"2013","unstructured":"Gupta, N., Choudhary, K., Katiyal, S.: Two bit arithmetic logic unit (ALU) in QCA. Int. J. Recent Trends Eng. Technol. 8(2), 35 (2013)","journal-title":"Int. J. Recent Trends Eng. Technol."},{"key":"5073_CR64","doi-asserted-by":"crossref","unstructured":"Waje, M.G., Dakhole, P.: Design and implementation of 4-bit arithmetic logic unit using Quantum Dot Cellular Automata. In: 2013 3rd IEEE international advance computing conference (IACC) (2013). IEEE","DOI":"10.1109\/IAdCC.2013.6514367"},{"key":"5073_CR65","doi-asserted-by":"crossref","unstructured":"Teja, V.C., Polisetti, S., Kasavajjala, S.: QCA based multiplexing of 16 arithmetic & logical subsystems-a paradigm for nano computing. In: 2008 3rd IEEE International Conference on Nano\/Micro Engineered and Molecular Systems (2008). IEEE","DOI":"10.1109\/NEMS.2008.4484438"},{"key":"5073_CR66","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1016\/j.mejo.2016.11.008","volume":"60","author":"M Goswami","year":"2017","unstructured":"Goswami, M., et al.: Design of testable adder in quantum-dot cellular automata with fault secure logic. Microelectron. J. 60, 1\u201312 (2017)","journal-title":"Microelectron. J."},{"issue":"5","key":"5073_CR67","first-page":"2010","volume":"2","author":"E Ganesh","year":"1824","unstructured":"Ganesh, E.: Implementation and simulation of arithmetic logic unit, shifter and multiplier in Quantum cellular automata technology. Int. J. Comput. Sci. Eng. 2(5), 2010 (1824)","journal-title":"Int. J. Comput. Sci. Eng."},{"issue":"3","key":"5073_CR68","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/2629538","volume":"11","author":"B Sen","year":"2014","unstructured":"Sen, B., et al.: Realizing reversible computing in QCA framework resulting in efficient design of testable ALU. ACM J. Emerg. Technol. Comput. Syst. (JETC) 11(3), 1\u201322 (2014)","journal-title":"ACM J. Emerg. Technol. Comput. Syst. (JETC)"},{"key":"5073_CR69","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2020.106548","volume":"82","author":"S-S Ahmadpour","year":"2020","unstructured":"Ahmadpour, S.-S., Mosleh, M., Heikalabad, S.R.: An efficient fault-tolerant arithmetic logic unit using a novel fault-tolerant 5-input majority gate in quantum-dot cellular automata. Comput. Electr. Eng. 82, 106548 (2020)","journal-title":"Comput. Electr. Eng."},{"issue":"1","key":"5073_CR70","doi-asserted-by":"publisher","first-page":"26","DOI":"10.1109\/TNANO.2003.820815","volume":"3","author":"K Walus","year":"2004","unstructured":"Walus, K., et al.: QCADesigner: a rapid design and simulation tool for quantum-dot cellular automata. IEEE Trans. Nanotechnol. 3(1), 26\u201331 (2004)","journal-title":"IEEE Trans. Nanotechnol."}],"container-title":["Cluster Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10586-024-05073-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10586-024-05073-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10586-024-05073-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,6]],"date-time":"2025-09-06T15:05:37Z","timestamp":1757171137000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10586-024-05073-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,4,28]]},"references-count":70,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2025,8]]}},"alternative-id":["5073"],"URL":"https:\/\/doi.org\/10.1007\/s10586-024-05073-3","relation":{},"ISSN":["1386-7857","1573-7543"],"issn-type":[{"value":"1386-7857","type":"print"},{"value":"1573-7543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,4,28]]},"assertion":[{"value":"29 August 2024","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"24 December 2024","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"25 December 2024","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"28 April 2025","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}},{"value":"This paper is not applicable\u00a0to both human and\/ or animal studies.","order":3,"name":"Ethics","group":{"name":"EthicsHeading","label":"Ethical approval"}}],"article-number":"340"}}