{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,11]],"date-time":"2025-09-11T19:56:47Z","timestamp":1757620607907,"version":"3.44.0"},"reference-count":97,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T00:00:00Z","timestamp":1753833600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T00:00:00Z","timestamp":1753833600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Cluster Comput"],"published-print":{"date-parts":[[2025,9]]},"DOI":"10.1007\/s10586-025-05130-5","type":"journal-article","created":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:05:41Z","timestamp":1753884341000},"update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["An efficient low aggressiveness portion (ELAP) cache replacement policy for systems with non-volatile main memory"],"prefix":"10.1007","volume":"28","author":[{"given":"Shefaa","family":"Alzoubi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amal","family":"Rassas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohammad","family":"AlYamani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohammad","family":"Alshboul","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2025,7,30]]},"reference":[{"key":"5130_CR1","doi-asserted-by":"publisher","first-page":"154518","DOI":"10.1109\/ACCESS.2020.3017651","volume":"8","author":"L Zhan","year":"2020","unstructured":"Zhan, L., Lu, K., Cheng, Z., Wan, J.: RangeKV: an efficient key-value store based on hybrid DRAM\u2013NVM\u2013SSD storage structure. IEEE Access 8, 154518\u2013154529 (2020)","journal-title":"IEEE Access"},{"doi-asserted-by":"crossref","unstructured":"Peng, I.B., Gokhale, M.B., Green, E.W.: System evaluation of the Intel Optane byte-addressable NVM. In: Proceedings of the International Symposium on Memory Systems, 2019, pp. 304\u2013315 (2019)","key":"5130_CR2","DOI":"10.1145\/3357526.3357568"},{"issue":"4","key":"5130_CR3","doi-asserted-by":"publisher","first-page":"3355","DOI":"10.3906\/elk-1608-22","volume":"25","author":"DU Erten","year":"2017","unstructured":"Erten, D.U.: Access pattern-aware data placement for hybrid DRAM\/NVM. Turk. J. Electr. Eng. Comput. Sci. 25(4), 3355\u20133366 (2017)","journal-title":"Turk. J. Electr. Eng. Comput. Sci."},{"doi-asserted-by":"publisher","unstructured":"Van Doren, S.: Abstract\u2014HOTI 2019: compute express link. In: 2019 IEEE Symposium on High-Performance Interconnects (HOTI), 2019, p. 18 (2019). https:\/\/doi.org\/10.1109\/HOTI.2019.00017","key":"5130_CR4","DOI":"10.1109\/HOTI.2019.00017"},{"issue":"3","key":"5130_CR5","doi-asserted-by":"publisher","first-page":"1862","DOI":"10.21917\/ijme.2024.0320","volume":"10","author":"B Puviyarasi","year":"2024","unstructured":"Puviyarasi, B., Nagesh, R., Prakash, M., Kumara, S.P.: Innovations in memory devices and circuits-enhancing storage performance and efficiency in modern electronics. ICTACT J. Microelectron. 10(3), 1862\u20131870 (2024)","journal-title":"ICTACT J. Microelectron."},{"issue":"3","key":"5130_CR6","doi-asserted-by":"publisher","first-page":"1281","DOI":"10.1109\/TED.2019.2894387","volume":"66","author":"A Grossi","year":"2019","unstructured":"Grossi, A., Vianello, E., Sabry, M.M., Barlas, M., Grenouillet, L., Coignus, J., Beigne, E., Wu, T., Le, B.Q., Wootters, M.K., et al.: Resistive ram endurance: array-level characterization and correction techniques targeting deep learning applications. IEEE Trans. Electron Devices 66(3), 1281\u20131288 (2019)","journal-title":"IEEE Trans. Electron Devices"},{"doi-asserted-by":"crossref","unstructured":"Lin, K.-F., Noguchi, H., Shih, Y.-C., Yuh, P.-F., Lee, Y.-J., Chang, T.-C., Huang, S.-P., Lin, Y.-F., Lee, C.-Y., Huang, Y.-H., et al.: 15.9 A 16 nm 16 Mb embedded STT-MRAM with a 20 ns write time, a 10 12 write endurance and integrated margin-expansion schemes. In: 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, vol. 67, pp. 292\u2013294. IEEE (2024)","key":"5130_CR7","DOI":"10.1109\/ISSCC49657.2024.10454339"},{"doi-asserted-by":"crossref","unstructured":"Sivakumar, S., Mannampalli, M., Jose, J.: Enhancing lifetime of non-volatile memory caches by write-aware techniques. In: Emerging Electronic Devices, Circuits and Systems: Select Proceedings of EEDCS Workshop Held in Conjunction with ISDCS 2022, 2023, pp. 109\u2013123. Springer (2023)","key":"5130_CR8","DOI":"10.1007\/978-981-99-0055-8_10"},{"doi-asserted-by":"crossref","unstructured":"Mittal, S., Vetter, J.S., Li, D.: WriteSmoothing: improving lifetime of non-volatile caches using intra-set wear-leveling. In: Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI, 2014, pp. 139\u2013144 (2014)","key":"5130_CR9","DOI":"10.1145\/2591513.2591525"},{"key":"5130_CR10","doi-asserted-by":"publisher","first-page":"60622","DOI":"10.1109\/ACCESS.2018.2875820","volume":"6","author":"L Zhu","year":"2018","unstructured":"Zhu, L., Chen, Z., Liu, F., Xiao, N.: Wear leveling for non-volatile memory: a runtime system approach. IEEE Access 6, 60622\u201360634 (2018)","journal-title":"IEEE Access"},{"issue":"2","key":"5130_CR11","doi-asserted-by":"publisher","first-page":"129","DOI":"10.1109\/TMSCS.2016.2525999","volume":"2","author":"C Pan","year":"2016","unstructured":"Pan, C., Gu, S., Xie, M., Liu, Y., Xue, C.J., Hu, J.: Wear-leveling aware page management for non-volatile main memory on embedded systems. IEEE Trans. Multi-scale Comput. Syst. 2(2), 129\u2013142 (2016)","journal-title":"IEEE Trans. Multi-scale Comput. Syst."},{"doi-asserted-by":"crossref","unstructured":"Nath, A., Kapoor, H.K.: WELCOMF: wear leveling assisted compression using frequent words in non-volatile main memories. In: Proceedings of the ACM\/IEEE International Symposium on Low Power Electronics and Design, 2020, pp. 157\u2013162 (2020)","key":"5130_CR12","DOI":"10.1145\/3370748.3406559"},{"doi-asserted-by":"crossref","unstructured":"Qureshi, M.K., Karidis, J.P., Franceschini, M.M., Srinivasan, V., Lastras, L.A., Abali, B.: Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling. In: 2009 42nd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), 2009, pp. 14\u201323 (2009)","key":"5130_CR13","DOI":"10.1145\/1669112.1669117"},{"doi-asserted-by":"crossref","unstructured":"Garc\u00eda, A.A., Jong, R., Wang, W., Diestelhorst, S.: Composing lifetime enhancing techniques for non-volatile main memories. In: Proceedings of the International Symposium on Memory Systems. MEMSYS \u201917, 2017, pp. 363\u2013373 (2017)","key":"5130_CR14","DOI":"10.1145\/3132402.3132411"},{"issue":"10","key":"5130_CR15","doi-asserted-by":"publisher","first-page":"2516","DOI":"10.1109\/TCAD.2019.2962127","volume":"39","author":"D Feng","year":"2020","unstructured":"Feng, D., Xu, J., Hua, Y., Tong, W., Liu, J., Li, C., Chen, Y.: A low-overhead encoding scheme to extend the lifetime of nonvolatile memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10), 2516\u20132529 (2020). https:\/\/doi.org\/10.1109\/TCAD.2019.2962127","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"doi-asserted-by":"crossref","unstructured":"Palangappa, P.M., Mohanram, K.: CASTLE: compression architecture for secure low latency, low energy, high endurance NVMs. In: Proceedings of the 55th Annual Design Automation Conference, 2018, pp. 1\u20136 (2018)","key":"5130_CR16","DOI":"10.1109\/DAC.2018.8465917"},{"doi-asserted-by":"crossref","unstructured":"Dgien, D.B., Palangappa, P.M., Hunter, N.A., Li, J., Mohanram, K.: Compression architecture for bit-write reduction in non-volatile memory technologies. In: Proceedings of the 2014 IEEE\/ACM International Symposium on Nanoscale Architectures, 2014, pp. 51\u201356 (2014)","key":"5130_CR17","DOI":"10.1109\/NANOARCH.2014.6880482"},{"doi-asserted-by":"crossref","unstructured":"Xu, J., Feng, D., Hua, Y., Tong, W., Liu, J., Li, C.: Extending the lifetime of NVMs with compression. In: 2018 Design, Automation and Test in Europe Conference and Exhibition (DATE), 2018, pp. 1604\u20131609 (2018)","key":"5130_CR18","DOI":"10.23919\/DATE.2018.8342271"},{"issue":"2","key":"5130_CR19","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3289187","volume":"24","author":"M Bakhshalipour","year":"2019","unstructured":"Bakhshalipour, M., Faraji, A., Ghahani, S.A.V., Samandi, F., Lotfi-Kamran, P., Sarbazi-Azad, H.: Reducing writebacks through in-cache displacement. ACM Trans. Des. Autom. Electron. Syst. 24(2), 1\u201321 (2019)","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"issue":"2","key":"5130_CR20","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3292009","volume":"24","author":"B Pourshirazi","year":"2019","unstructured":"Pourshirazi, B., Beigi, M.V., Zhu, Z., Memik, G.: Writeback-aware LLC management for PCM-based main memory systems. ACM Trans. Des. Autom. Electron. Syst. 24(2), 1\u201319 (2019)","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"issue":"9","key":"5130_CR21","doi-asserted-by":"publisher","first-page":"2000","DOI":"10.1093\/comjnl\/bxu104","volume":"58","author":"R Rodr\u00edguez-Rodr\u00edguez","year":"2014","unstructured":"Rodr\u00edguez-Rodr\u00edguez, R., Castro, F., Chaver, D., Gonzalez-Alberquilla, R., Pi\u00f1uel, L., Tirado, F.: Write-aware replacement policies for PCM-based systems. Comput. J. 58(9), 2000\u20132025 (2014)","journal-title":"Comput. J."},{"doi-asserted-by":"crossref","unstructured":"Jia, Y., Zhou, F., Gao, X., Wu, S., Jin, H., Liao, X., Yuan, P.: VAIL: a victim-aware cache policy for improving lifetime of hybrid memory. In: Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores. PMAM\u201918, 2018, pp. 79\u201384 (2018)","key":"5130_CR22","DOI":"10.1145\/3178442.3178451"},{"issue":"11","key":"5130_CR23","doi-asserted-by":"publisher","first-page":"3627","DOI":"10.1109\/TCAD.2020.3012213","volume":"39","author":"F Wen","year":"2020","unstructured":"Wen, F., Qin, M., Gratz, P.V., Reddy, A.N.: Hardware memory management for future mobile hybrid memory systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11), 3627\u20133637 (2020)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"issue":"1","key":"5130_CR24","doi-asserted-by":"publisher","first-page":"52","DOI":"10.1166\/jolpe.2005.001","volume":"1","author":"HG Lee","year":"2005","unstructured":"Lee, H.G., Chang, N.: Low-energy heterogeneous non-volatile memory systems for mobile systems. J. Low Power Electron. 1(1), 52\u201362 (2005)","journal-title":"J. Low Power Electron."},{"issue":"11","key":"5130_CR25","doi-asserted-by":"publisher","first-page":"4374","DOI":"10.1109\/TED.2017.2746342","volume":"64","author":"SW Fong","year":"2017","unstructured":"Fong, S.W., Neumann, C.M., Wong, H.-S.P.: Phase-change memory\u2014towards a storage-class memory. IEEE Trans. Electron Devices 64(11), 4374\u20134385 (2017)","journal-title":"IEEE Trans. Electron Devices"},{"issue":"2","key":"5130_CR26","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/2463585.2463589","volume":"9","author":"D Apalkov","year":"2013","unstructured":"Apalkov, D., Khvalkovskiy, A., Watts, S., Nikitin, V., Tang, X., Lottis, D., Moon, K., Luo, X., Chen, E., Ong, A., et al.: Spin-transfer torque magnetic random access memory (STT-MRAM). ACM J. Emerg. Technol. Comput. Syst. 9(2), 1\u201335 (2013)","journal-title":"ACM J. Emerg. Technol. Comput. Syst."},{"issue":"12","key":"5130_CR27","doi-asserted-by":"publisher","first-page":"2237","DOI":"10.1109\/JPROC.2010.2070830","volume":"98","author":"H Akinaga","year":"2010","unstructured":"Akinaga, H., Shima, H.: Resistive random access memory (ReRAM) based on metal oxides. Proc. IEEE 98(12), 2237\u20132251 (2010)","journal-title":"Proc. IEEE"},{"key":"5130_CR28","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-01735-3","volume-title":"Phase Change Memory: From Devices to Systems","author":"MKA Qureshi","year":"2012","unstructured":"Qureshi, M.K.A., Gurumurthi, S., Rajendran, B.: Phase Change Memory: From Devices to Systems, vol. 18. Springer, Cham (2012)"},{"doi-asserted-by":"crossref","unstructured":"Saraf, P., Mutyam, M.: Endurance enhancement of write-optimized STT-RAM caches. In: Proceedings of the International Symposium on Memory Systems, 2019, pp. 101\u2013113 (2019)","key":"5130_CR29","DOI":"10.1145\/3357526.3357538"},{"unstructured":"Kim, Y.-B., Lee, S.R., Lee, D., Lee, C.B., Chang, M., Hur, J.H., Lee, M.-J., Park, G.-S., Kim, C.J., Chung, U.-I., et al.: Bi-layered RRAM with unlimited endurance and extremely uniform switching. In: 2011 Symposium on VLSI Technology-Digest of Technical Papers, 2011, pp. 52\u201353. IEEE (2011)","key":"5130_CR30"},{"doi-asserted-by":"crossref","unstructured":"Wang, J., Dong, X., Xie, Y., Jouppi, N.P.: i$$^2$$WAP: improving non-volatile cache lifetime by reducing inter-and intra-set write variations. In: 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), 2013, pp. 234\u2013245. IEEE (2013)","key":"5130_CR31","DOI":"10.1109\/HPCA.2013.6522322"},{"doi-asserted-by":"crossref","unstructured":"Chi, P., Li, S., Cheng, Y., Lu, Y., Kang, S.H., Xie, Y.: Architecture design with STT-RAM: opportunities and challenges. In: 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 2016, pp. 109\u2013114. IEEE (2016)","key":"5130_CR32","DOI":"10.1109\/ASPDAC.2016.7427997"},{"doi-asserted-by":"publisher","unstructured":"Bishnoi, R., Oboril, F., Ebrahimi, M., Tahoori, M.B.: Avoiding unnecessary write operations in STT-MRAM for low power implementation. In: Fifteenth International Symposium on Quality Electronic Design, 2014, pp. 548\u2013553 (2014). https:\/\/doi.org\/10.1109\/ISQED.2014.6783375","key":"5130_CR33","DOI":"10.1109\/ISQED.2014.6783375"},{"doi-asserted-by":"crossref","unstructured":"Bishnoi, R., Oboril, F., Ebrahimi, M., Tahoori, M.B.: Avoiding unnecessary write operations in STT-MRAM for low power implementation. In: Fifteenth International Symposium on Quality Electronic Design, 2014, pp. 548\u2013553. IEEE (2014)","key":"5130_CR34","DOI":"10.1109\/ISQED.2014.6783375"},{"key":"5130_CR35","doi-asserted-by":"publisher","first-page":"319","DOI":"10.1016\/j.compeleceng.2019.01.020","volume":"74","author":"F Shen","year":"2019","unstructured":"Shen, F., He, Y., Zhang, J., Li, Q., Li, J., Xu, C.: Reuse locality aware cache partitioning for last-level cache. Comput. Electr. Eng. 74, 319\u2013330 (2019)","journal-title":"Comput. Electr. Eng."},{"issue":"3","key":"5130_CR36","doi-asserted-by":"publisher","first-page":"187","DOI":"10.1016\/S0045-7906(99)00041-5","volume":"26","author":"H Khalid","year":"2000","unstructured":"Khalid, H., Obaidat, M.S.: KORA: a new cache replacement scheme. Comput. Electr. Eng. 26(3), 187\u2013206 (2000)","journal-title":"Comput. Electr. Eng."},{"doi-asserted-by":"crossref","unstructured":"Panda, P., Patil, G., Raveendran, B.: A survey on replacement strategies in cache memory for embedded systems. In: 2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), 2016, pp. 12\u201317 (2016)","key":"5130_CR37","DOI":"10.1109\/DISCOVER.2016.7806218"},{"doi-asserted-by":"crossref","unstructured":"Smaragdakis, Y.: General adaptive replacement policies. In: Proceedings of the 4th International Symposium on Memory Management, 2004, pp. 108\u2013119 (2004)","key":"5130_CR38","DOI":"10.1145\/1029873.1029887"},{"unstructured":"Wang, Z., McKinley, K.S., Rosenberg, A.L., Weems, C.C.: Using the compiler to improve cache replacement decisions. In: Proceedings. International Conference on Parallel Architectures and Compilation Techniques, 2002, pp. 199\u2013208 (2002)","key":"5130_CR39"},{"doi-asserted-by":"crossref","unstructured":"Al-Zoubi, H., Milenkovic, A., Milenkovic, M.: Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite. In: Proceedings of the 42nd Annual Southeast Regional Conference, 2004, pp. 267\u2013272 (2004)","key":"5130_CR40","DOI":"10.1145\/986537.986601"},{"issue":"4\u20135","key":"5130_CR41","doi-asserted-by":"publisher","first-page":"286","DOI":"10.1016\/j.micpro.2015.05.005","volume":"39","author":"CT Do","year":"2015","unstructured":"Do, C.T., Choi, H.-J., Kim, J.M., Kim, C.H.: A new cache replacement algorithm for last-level caches by exploiting tag-distance correlation of cache lines. Microprocess. Microsyst. 39(4\u20135), 286\u2013295 (2015)","journal-title":"Microprocess. Microsyst."},{"issue":"4","key":"5130_CR42","doi-asserted-by":"publisher","first-page":"374","DOI":"10.1145\/954339.954341","volume":"35","author":"S Podlipnig","year":"2003","unstructured":"Podlipnig, S., B\u00f6sz\u00f6rmenyi, L.: A survey of web cache replacement strategies. ACM Comput. Surv. 35(4), 374\u2013398 (2003)","journal-title":"ACM Comput. Surv."},{"issue":"4","key":"5130_CR43","doi-asserted-by":"publisher","first-page":"3309","DOI":"10.1007\/s10586-020-03089-z","volume":"23","author":"FM Talaat","year":"2020","unstructured":"Talaat, F.M., Ali, S.H., Saleh, A.I., Ali, H.A.: Effective cache replacement strategy (ECRS) for real-time fog computing environment. Clust. Comput. 23(4), 3309\u20133333 (2020)","journal-title":"Clust. Comput."},{"issue":"3","key":"5130_CR44","doi-asserted-by":"publisher","first-page":"2427","DOI":"10.1007\/s10586-023-04095-7","volume":"27","author":"L Abdo","year":"2024","unstructured":"Abdo, L., Ahmad, I., Abed, S.: A smart admission control and cache replacement approach in content delivery networks. Clust. Comput. 27(3), 2427\u20132445 (2024)","journal-title":"Clust. Comput."},{"issue":"4","key":"5130_CR45","doi-asserted-by":"publisher","first-page":"293","DOI":"10.1007\/s10586-005-4096-0","volume":"8","author":"E Otoo","year":"2005","unstructured":"Otoo, E., Rotem, D., Shoshani, A.: Impact of admission and cache replacement policies on response times of jobs on data grids. Clust. Comput. 8(4), 293\u2013303 (2005)","journal-title":"Clust. Comput."},{"issue":"2","key":"5130_CR46","doi-asserted-by":"publisher","first-page":"122","DOI":"10.1016\/j.jalgor.2003.12.002","volume":"51","author":"R Pagh","year":"2004","unstructured":"Pagh, R., Rodler, F.F.: Cuckoo hashing. J. Algorithms 51(2), 122\u2013144 (2004)","journal-title":"J. Algorithms"},{"issue":"2","key":"5130_CR47","doi-asserted-by":"publisher","first-page":"169","DOI":"10.1145\/173682.165152","volume":"21","author":"A Seznec","year":"1993","unstructured":"Seznec, A.: A case for two-way skewed-associative caches. ACM SIGARCH Comput. Archit. News 21(2), 169\u2013178 (1993)","journal-title":"ACM SIGARCH Comput. Archit. News"},{"issue":"3","key":"5130_CR48","doi-asserted-by":"publisher","first-page":"60","DOI":"10.1145\/1816038.1815971","volume":"38","author":"A Jaleel","year":"2010","unstructured":"Jaleel, A., Theobald, K.B., Steely, S.C., Jr., Emer, J.: High performance cache replacement using re-reference interval prediction (RRIP). ACM SIGARCH Comput. Archit. News 38(3), 60\u201371 (2010)","journal-title":"ACM SIGARCH Comput. Archit. News"},{"issue":"2","key":"5130_CR49","doi-asserted-by":"publisher","first-page":"381","DOI":"10.1145\/1273440.1250709","volume":"35","author":"MK Qureshi","year":"2007","unstructured":"Qureshi, M.K., Jaleel, A., Patt, Y.N., Steely, S.C., Emer, J.: Adaptive insertion policies for high performance caching. ACM SIGARCH Comput. Archit. News 35(2), 381\u2013391 (2007)","journal-title":"ACM SIGARCH Comput. Archit. News"},{"unstructured":"Gober, N., Chacon, G., Wang, L., Gratz, P.V., Jimenez, D.A., Teran, E., Pugsley, S., Kim, J.: The championship simulator: architectural simulation for education and competition. arXiv preprint (2022). arXiv:2210.14324","key":"5130_CR50"},{"unstructured":"The ChampSim Simulator (2024). https:\/\/github.com\/ChampSim\/ChampSim. Accessed Jan 2024","key":"5130_CR51"},{"unstructured":"2nd Cache replacement championship (2024). https:\/\/crc2.ece.tamu.edu\/. Accessed Jan 2024","key":"5130_CR52"},{"doi-asserted-by":"crossref","unstructured":"P\u00e9neau, P.-Y., Novo, D., Bruguier, F., Torres, L., Sassatelli, G., Gamati\u00e9, A.: Improving the performance of STT-MRAM LLC through enhanced cache replacement policy. In: Architecture of Computing Systems\u2014ARCS 2018: 31st International Conference, Proceedings 31, Braunschweig, Germany, 9\u201312 April 2018, pp. 168\u2013180. Springer (2018)","key":"5130_CR53","DOI":"10.1007\/978-3-319-77610-1_13"},{"doi-asserted-by":"crossref","unstructured":"Sharan, H., Vutukuru, M., Panda, B.: DDIOSim: a microarchitecture simulator for data direct I\/O technology. In: 30th IEEE International Conference on High Performance Computing, Data, and Analytics, 2023 (2023)","key":"5130_CR54","DOI":"10.1109\/HiPC58850.2023.00035"},{"doi-asserted-by":"crossref","unstructured":"Wu, H., Nathella, K., Sunwoo, D., Jain, A., Lin, C.: Efficient metadata management for irregular data prefetching. In: Proceedings of the 46th International Symposium on Computer Architecture, 2019, pp. 449\u2013461 (2019)","key":"5130_CR55","DOI":"10.1145\/3307650.3322225"},{"issue":"4","key":"5130_CR56","doi-asserted-by":"publisher","first-page":"737","DOI":"10.1145\/3093336.3037701","volume":"52","author":"J Kim","year":"2017","unstructured":"Kim, J., Teran, E., Gratz, P.V., Jim\u00e9nez, D.A., Pugsley, S.H., Wilkerson, C.: Kill the program counter: reconstructing program behavior in the processor cache hierarchy. ACM SIGPLAN Not. 52(4), 737\u2013749 (2017)","journal-title":"ACM SIGPLAN Not."},{"doi-asserted-by":"crossref","unstructured":"Bakhshalipour, M., Shakerinava, M., Lotfi-Kamran, P., Sarbazi-Azad, H.: Bingo spatial data prefetcher. In: 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2019, pp. 399\u2013411. IEEE (2019)","key":"5130_CR57","DOI":"10.1109\/HPCA.2019.00053"},{"doi-asserted-by":"crossref","unstructured":"Singh, A., Panda, B.: Rowhammer cache: a last-level cache for low-overhead rowhammer tracking. In: 2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2024 (2024)","key":"5130_CR58","DOI":"10.1109\/HOST55342.2024.10545410"},{"doi-asserted-by":"crossref","unstructured":"Pakalapati, S., Panda, B.: Bouquet of instruction pointers: instruction pointer classifier-based spatial hardware prefetching. In: 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, pp. 118\u2013131. IEEE (2020)","key":"5130_CR59","DOI":"10.1109\/ISCA45697.2020.00021"},{"issue":"1","key":"5130_CR60","doi-asserted-by":"publisher","first-page":"17","DOI":"10.1109\/LCA.2023.3242178","volume":"22","author":"DA Jim\u00e9nez","year":"2023","unstructured":"Jim\u00e9nez, D.A., Teran, E., Gratz, P.V.: Last-level cache insertion and promotion policy in the presence of aggressive prefetching. IEEE Comput. Archit. Lett. 22(1), 17\u201320 (2023)","journal-title":"IEEE Comput. Archit. Lett."},{"doi-asserted-by":"crossref","unstructured":"Shah, I., Jain, A., Lin, C.: Effective mimicry of Belady\u2019s MIN policy. In: 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2022, pp. 558\u2013572. IEEE (2022)","key":"5130_CR61","DOI":"10.1109\/HPCA53966.2022.00048"},{"doi-asserted-by":"crossref","unstructured":"Navarro-Torres, A., Panda, B., Alastruey-Bened\u00e9, J., Ib\u00e1\u00f1ez, P., Vi\u00f1als-Y\u00fafera, V., Ros, A.: Berti: an accurate local-delta data prefetcher. In: 2022 55th IEEE\/ACM International Symposium on Microarchitecture (MICRO), 2022, pp. 975\u2013991. IEEE (2022)","key":"5130_CR62","DOI":"10.1109\/MICRO56248.2022.00072"},{"doi-asserted-by":"crossref","unstructured":"Bhatia, E., Chacon, G., Pugsley, S., Teran, E., Gratz, P.V., Jim\u00e9nez, D.A.: Perceptron-based prefetch filtering. In: Proceedings of the 46th International Symposium on Computer Architecture, 2019, pp. 1\u201313 (2019)","key":"5130_CR63","DOI":"10.1145\/3307650.3322207"},{"doi-asserted-by":"crossref","unstructured":"Feliu, J., Perais, A., Jim\u00e9nez, D.A., Ros, A.: Rebasing microarchitectural research with industry traces. In: 2023 IEEE International Symposium on Workload Characterization (IISWC), 2023, pp. 100\u2013114. IEEE (2023)","key":"5130_CR64","DOI":"10.1109\/IISWC59245.2023.00027"},{"issue":"4","key":"5130_CR65","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1186736.1186737","volume":"34","author":"JL Henning","year":"2006","unstructured":"Henning, J.L.: SPEC CPU2006 benchmark descriptions. ACM SIGARCH Comput. Archit. News 34(4), 1\u201317 (2006)","journal-title":"ACM SIGARCH Comput. Archit. News"},{"unstructured":"ChampSim workloads (2024). https:\/\/dpc3.compas.cs.stonybrook.edu\/champsim-traces\/speccpu\/. Accessed Jan 2024","key":"5130_CR66"},{"unstructured":"ChampSim SPEC2017 workloads (2024). https:\/\/dpc3.compas.cs.stonybrook.edu\/?SW_IS. Accessed Jan 2024","key":"5130_CR67"},{"doi-asserted-by":"crossref","unstructured":"Bienia, C., Kumar, S., Singh, J.P., Li, K.: The parsec benchmark suite: characterization and architectural implications. In: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008, pp. 72\u201381 (2008)","key":"5130_CR68","DOI":"10.1145\/1454115.1454128"},{"doi-asserted-by":"crossref","unstructured":"Shun, J., Blelloch, G.E.: Ligra: a lightweight graph processing framework for shared memory. In: Proceedings of the 18th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2013, pp. 135\u2013146 (2013)","key":"5130_CR69","DOI":"10.1145\/2442516.2442530"},{"issue":"3","key":"5130_CR70","doi-asserted-by":"publisher","first-page":"78","DOI":"10.1147\/sj.52.0078","volume":"5","author":"LA Belady","year":"1966","unstructured":"Belady, L.A.: A study of replacement algorithms for virtual storage. IBM Syst. J. 5(3), 78\u2013101 (1966)","journal-title":"IBM Syst. J."},{"doi-asserted-by":"crossref","unstructured":"Lee, D., Choi, J., Kim, J.-H., Noh, S.H., Min, S.L., Cho, Y., Kim, C.S.: On the existence of a spectrum of policies that subsumes the least recently used (LRU) and least frequently used (LFU) policies. In: Proceedings of the 1999 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 1999, pp. 134\u2013143 (1999)","key":"5130_CR71","DOI":"10.1145\/301453.301487"},{"issue":"1","key":"5130_CR72","doi-asserted-by":"publisher","first-page":"80","DOI":"10.1145\/321623.321632","volume":"18","author":"AV Aho","year":"1971","unstructured":"Aho, A.V., Denning, P.J., Ullman, J.D.: Principles of optimal page replacement. J. ACM 18(1), 80\u201393 (1971)","journal-title":"J. ACM"},{"issue":"1","key":"5130_CR73","doi-asserted-by":"publisher","first-page":"106","DOI":"10.2307\/2490939","volume":"21","author":"D Morse","year":"1983","unstructured":"Morse, D., Richardson, G.: The LIFO\/FIFO decision. J. Account. Res. 21(1), 106\u2013127 (1983)","journal-title":"J. Account. Res."},{"issue":"6","key":"5130_CR74","doi-asserted-by":"publisher","first-page":"700","DOI":"10.1109\/12.2208","volume":"37","author":"K So","year":"1988","unstructured":"So, K., Rechtschaffen, R.N.: Cache operations by MRU change. IEEE Trans. Comput. 37(6), 700\u2013709 (1988)","journal-title":"IEEE Trans. Comput."},{"issue":"1","key":"5130_CR75","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3483839","volume":"21","author":"C Hakert","year":"2022","unstructured":"Hakert, C., Chen, K.-H., Schirmeier, H., Bauer, L., Genssler, P.R., Br\u00fcggen, G., Amrouch, H., Henkel, J., Chen, J.-J.: Software-managed read and write wear-leveling for non-volatile main memory. ACM Trans. Embed. Comput. Syst. 21(1), 1\u201324 (2022)","journal-title":"ACM Trans. Embed. Comput. Syst."},{"doi-asserted-by":"crossref","unstructured":"Li, W., Shuai, Z., Xue, C.J., Yuan, M., Li, Q.: A wear leveling aware memory allocator for both stack and heap management in PCM-based main memory systems. In: 2019 Design, Automation and Test in Europe Conference and Exhibition (DATE), 2019, pp. 228\u2013233. IEEE (2019)","key":"5130_CR76","DOI":"10.23919\/DATE.2019.8715132"},{"doi-asserted-by":"crossref","unstructured":"Alshboul, M., Tuck, J., Solihin, Y.: Lazy persistency: a high-performing and write-efficient software persistency technique. In: 2018 ACM\/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), 2018, pp. 439\u2013451 (2018)","key":"5130_CR77","DOI":"10.1109\/ISCA.2018.00044"},{"doi-asserted-by":"publisher","unstructured":"Pelley, S., Chen, P.M., Wenisch, T.F.: Memory persistency. In: 2014 ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA), 2014, pp. 265\u2013276 (2014). https:\/\/doi.org\/10.1109\/ISCA.2014.6853222","key":"5130_CR78","DOI":"10.1109\/ISCA.2014.6853222"},{"doi-asserted-by":"publisher","unstructured":"Alshboul, M., Tuck, J., Solihin, Y.: Lazy persistency: a high-performing and write-efficient software persistency technique. In: 2018 ACM\/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), 2018, pp. 439\u2013451 (2018). https:\/\/doi.org\/10.1109\/ISCA.2018.00044","key":"5130_CR79","DOI":"10.1109\/ISCA.2018.00044"},{"key":"5130_CR80","doi-asserted-by":"publisher","DOI":"10.1145\/3323091","author":"M Alshboul","year":"2019","unstructured":"Alshboul, M., Elnawawy, H., Elkhouly, R., Kimura, K., Tuck, J., Solihin, Y.: Efficient checkpointing with recompute scheme for non-volatile main memory. ACM Trans. Archit. Code Optim. (2019). https:\/\/doi.org\/10.1145\/3323091","journal-title":"ACM Trans. Archit. Code Optim."},{"issue":"4","key":"5130_CR81","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3371236","volume":"16","author":"R Elkhouly","year":"2019","unstructured":"Elkhouly, R., Alshboul, M., Hayashi, A., Solihin, Y., Kimura, K.: Compiler-support for critical data persistence in NVM. ACM Trans. Archit. Code Optim. 16(4), 1\u201325 (2019)","journal-title":"ACM Trans. Archit. Code Optim."},{"doi-asserted-by":"crossref","unstructured":"Qin, H., Jin, H.: Warstack: improving LLC replacement for NVM with a writeback-aware reuse stack. In: 2017 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), 2017, pp. 233\u2013236 (2017)","key":"5130_CR82","DOI":"10.1109\/PDP.2017.81"},{"issue":"1","key":"5130_CR83","doi-asserted-by":"publisher","first-page":"64","DOI":"10.1109\/LCA.2017.2762660","volume":"17","author":"A Vakil-Ghahani","year":"2017","unstructured":"Vakil-Ghahani, A., Mahdizadeh-Shahri, S., Lotfi-Namin, M.-R., Bakhshalipour, M., Lotfi-Kamran, P., Sarbazi-Azad, H.: Cache replacement policy based on expected hit count. IEEE Comput. Archit. Lett. 17(1), 64\u201367 (2017)","journal-title":"IEEE Comput. Archit. Lett."},{"doi-asserted-by":"crossref","unstructured":"Jia, Y., Zhou, F., Gao, X., Wu, S., Jin, H., Liao, X., Yuan, P.: VAIL: a victim-aware cache policy for improving lifetime of hybrid memory. In: Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores, 2018, pp. 79\u201384. Association for Computing Machinery, New York (2018)","key":"5130_CR84","DOI":"10.1145\/3178442.3178451"},{"issue":"4","key":"5130_CR85","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/2541228.2555307","volume":"10","author":"Z Wang","year":"2013","unstructured":"Wang, Z., Shan, S., Cao, T., Gu, J., Xu, Y., Mu, S., Xie, Y., Jim\u00e9nez, D.A.: WADE: writeback-aware dynamic cache management for NVM-based main memory system. ACM Trans. Archit. Code Optim. 10(4), 1\u201321 (2013)","journal-title":"ACM Trans. Archit. Code Optim."},{"doi-asserted-by":"crossref","unstructured":"Jia, Y., Zhou, F., Gao, X., Wu, S., Jin, H., Liao, X., Yuan, P.: VAIL: a victim-aware cache policy for improving lifetime of hybrid memory. In: Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores, 2018, pp. 79\u201384 (2018)","key":"5130_CR86","DOI":"10.1145\/3178442.3178451"},{"issue":"3","key":"5130_CR87","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3380732","volume":"25","author":"A Nath","year":"2020","unstructured":"Nath, A., Agarwal, S., Kapoor, H.K.: Reuse distance-based victim cache for effective utilisation of hybrid main memory system. ACM Trans. Des. Autom. Electron. Syst. 25(3), 1\u201332 (2020)","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"key":"5130_CR88","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2021.102279","volume":"120","author":"Y Hua","year":"2021","unstructured":"Hua, Y., Huang, K., Zheng, S., Huang, L.: PMSort: an adaptive sorting engine for persistent memory. J. Syst. Archit. 120, 102279 (2021)","journal-title":"J. Syst. Archit."},{"unstructured":"Mittal, S., Vetter, J.S.: $$\\{$$EqualChance$$\\}$$: addressing intra-set write variation to increase lifetime of non-volatile caches. In: 2nd Workshop on Interactions of NVM\/Flash with Operating Systems and Workloads (INFLOW 14), 2014 (2014)","key":"5130_CR89"},{"issue":"9","key":"5130_CR90","doi-asserted-by":"publisher","first-page":"1297","DOI":"10.1109\/TC.2019.2892424","volume":"68","author":"S Agarwal","year":"2019","unstructured":"Agarwal, S., Kapoor, H.K.: Improving the lifetime of non-volatile cache by write restriction. IEEE Trans. Comput. 68(9), 1297\u20131312 (2019)","journal-title":"IEEE Trans. Comput."},{"doi-asserted-by":"crossref","unstructured":"Agarwal, S., Kapoor, H.K.: Lifetime enhancement of non-volatile caches by exploiting dynamic associativity management techniques. In: VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things: 25th IFIP WG 10.5\/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Revised and Extended Selected Papers 24, Abu Dhabi, United Arab Emirates, 23\u201325 October 2017, pp. 46\u201371. Springer (2019)","key":"5130_CR91","DOI":"10.1007\/978-3-030-15663-3_3"},{"issue":"3","key":"5130_CR92","doi-asserted-by":"publisher","first-page":"954","DOI":"10.1109\/TVLSI.2015.2420954","volume":"24","author":"MR Jokar","year":"2015","unstructured":"Jokar, M.R., Arjomand, M., Sarbazi-Azad, H.: Sequoia: a high-endurance NVM-based cache architecture. IEEE Trans. Vey Large Scale Integr. Syst. 24(3), 954\u2013967 (2015)","journal-title":"IEEE Trans. Vey Large Scale Integr. Syst."},{"issue":"11","key":"5130_CR93","doi-asserted-by":"publisher","first-page":"13342","DOI":"10.1007\/s11227-022-04394-7","volume":"78","author":"N Mahdavi","year":"2022","unstructured":"Mahdavi, N., Razaghian, F., Farbeh, H.: Data block manipulation for error rate reduction in STT-MRAM based main memory. J. Supercomput. 78(11), 13342\u201313372 (2022)","journal-title":"J. Supercomput."},{"key":"5130_CR94","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2022.104462","volume":"90","author":"N Mahdavi","year":"2022","unstructured":"Mahdavi, N., Razaghian, F., Farbeh, H.: An architectural-level reliability improvement scheme in STT-MRAM main memory. Microprocess. Microsyst. 90, 104462 (2022)","journal-title":"Microprocess. Microsyst."},{"doi-asserted-by":"crossref","unstructured":"Yang, J., Li, B., Yuan, J., Shen, Z., Du, D., Lilja, D.: Work-in-progress: Expcache: online-learning based cache replacement policy for non-volatile memory. In: 2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2022, pp. 7\u20138. IEEE (2022)","key":"5130_CR95","DOI":"10.1109\/CASES55004.2022.00010"},{"doi-asserted-by":"crossref","unstructured":"Sethumurugan, S., Yin, J., Sartori, J.: Designing a cost-effective cache replacement policy using machine learning. In: 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2021, pp. 291\u2013303. IEEE (2021)","key":"5130_CR96","DOI":"10.1109\/HPCA51647.2021.00033"},{"doi-asserted-by":"crossref","unstructured":"Yang, M., Yang, C., Shao, J.: Transformer-based cache replacement policy learning. In: International Conference on Web Information Systems Engineering, 2022, pp. 493\u2013500. Springer (2022)","key":"5130_CR97","DOI":"10.1007\/978-3-031-20891-1_35"}],"container-title":["Cluster Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10586-025-05130-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10586-025-05130-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10586-025-05130-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,8]],"date-time":"2025-09-08T08:50:32Z","timestamp":1757321432000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10586-025-05130-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7,30]]},"references-count":97,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2025,9]]}},"alternative-id":["5130"],"URL":"https:\/\/doi.org\/10.1007\/s10586-025-05130-5","relation":{},"ISSN":["1386-7857","1573-7543"],"issn-type":[{"type":"print","value":"1386-7857"},{"type":"electronic","value":"1573-7543"}],"subject":[],"published":{"date-parts":[[2025,7,30]]},"assertion":[{"value":"5 November 2024","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"9 January 2025","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"13 January 2025","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"30 July 2025","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare no competing interests.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}],"article-number":"414"}}