{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,6]],"date-time":"2022-04-06T00:22:19Z","timestamp":1649204539240},"reference-count":35,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2010,1,29]],"date-time":"2010-01-29T00:00:00Z","timestamp":1264723200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Des Autom Embed Syst"],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1007\/s10617-010-9050-6","type":"journal-article","created":{"date-parts":[[2010,1,27]],"date-time":"2010-01-27T18:50:55Z","timestamp":1264618255000},"page":"21-42","source":"Crossref","is-referenced-by-count":0,"title":["Evaluation of the implementation cost of cache coherence protocols using omniscient actions"],"prefix":"10.1007","volume":"14","author":[{"given":"Pierre","family":"Guironnet\u00a0de\u00a0Massas","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fr\u00e9d\u00e9ric","family":"P\u00e9trot","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2010,1,29]]},"reference":[{"key":"9050_CR1","doi-asserted-by":"crossref","first-page":"358","DOI":"10.1145\/1250662.1250707","volume-title":"ISCA \u201907: proceedings of the 34th annual international symposium on computer architecture","author":"J Leverich","year":"2007","unstructured":"Leverich J, Arakida H, Solomatnikov A, Firoozshahian A, Horowitz M, Kozyrakis C (2007) Comparing memory systems for chip multiprocessors. In: ISCA \u201907: proceedings of the 34th annual international symposium on computer architecture. ACM, New York, pp 358\u2013368"},{"key":"9050_CR2","doi-asserted-by":"crossref","first-page":"21","DOI":"10.1109\/MM.2005.35","volume":"25","author":"P Kongetira","year":"2005","unstructured":"Kongetira P, Aingaran K, Olukotun K (2005) Niagara: a 32-way multithreaded sparc processor. Micro IEEE 25:21\u201329","journal-title":"Micro IEEE"},{"key":"9050_CR3","first-page":"282","volume-title":"ISCA \u201900: proceedings of the 27th annual international symposium on computer architecture","author":"LA Barroso","year":"2000","unstructured":"Barroso LA, Gharachorloo K, McNamara R, Nowatzyk A, Qadeer S, Sano B, Smith S, Stets R, Verghese B (2000) Piranha: a scalable architecture based on single-chip multiprocessing. In: ISCA \u201900: proceedings of the 27th annual international symposium on computer architecture. ACM, New York, pp\u00a0282\u2013293"},{"issue":"4","key":"9050_CR4","doi-asserted-by":"crossref","first-page":"273","DOI":"10.1145\/6513.6514","volume":"4","author":"J Archibald","year":"1986","unstructured":"Archibald J, Baer J-L (1986) Cache coherence protocols: evaluation using a multiprocessor simulation model. ACM Trans Comput Syst 4(4):273\u2013298","journal-title":"ACM Trans Comput Syst"},{"key":"9050_CR5","first-page":"280","volume-title":"ISCA \u201988: proceedings of the 15th annual international symposium on computer architecture","author":"A Agarwal","year":"1988","unstructured":"Agarwal A, Simoni R, Hennessy J, Horowitz M (1988) An evaluation of directory schemes for cache coherence. In: ISCA \u201988: proceedings of the 15th annual international symposium on computer architecture. IEEE Computer Society, Los Alamitos, pp 280\u2013298"},{"issue":"2","key":"9050_CR6","doi-asserted-by":"crossref","first-page":"383","DOI":"10.1145\/1151074.1151081","volume":"5","author":"M Loghi","year":"2006","unstructured":"Loghi M, Poncino M, Benini L (2006) Cache coherence tradeoffs in shared-memory mpsocs. Trans Embed Comput Syst 5(2):383\u2013407","journal-title":"Trans Embed Comput Syst"},{"key":"9050_CR7","unstructured":"Qing Yang B-CL, Bhuyan Laxmi N (1989) Analysis and comparison of cache coherence protocols for a packet-switched multiprocessor. IEEE Trans Comput 38"},{"key":"9050_CR8","first-page":"298","volume-title":"ISCA \u201991: proceedings of the 18th annual international symposium on computer architecture","author":"SV Adve","year":"1991","unstructured":"Adve SV, Adve VS, Hill MD, Vernon MK (1991) Comparison of hardware and software cache coherence schemes. In: ISCA \u201991: proceedings of the 18th annual international symposium on computer architecture. ACM, New York, pp 298\u2013308"},{"key":"9050_CR9","doi-asserted-by":"crossref","first-page":"12","DOI":"10.1109\/2.55497","volume":"23","author":"P Stenstrom","year":"1990","unstructured":"Stenstrom P (1990) A survey of cache coherence schemes for multiprocessors. Computer 23:12\u201324","journal-title":"Computer"},{"key":"9050_CR10","doi-asserted-by":"crossref","first-page":"52","DOI":"10.1109\/MM.1994.363067","volume":"14","author":"M Tomasevic","year":"1994","unstructured":"Tomasevic M, Milutinovic V (1994) Hardware approaches to cache coherence in shared-memory multiprocessors, part 1. Micro IEEE 14:52","journal-title":"Micro IEEE"},{"key":"9050_CR11","doi-asserted-by":"crossref","first-page":"1112","DOI":"10.1109\/TC.1978.1675013","volume":"C-27","author":"L Censier","year":"1978","unstructured":"Censier L, Feautrier P (1978) A new solution to coherence problems in multicache systems. IEEE Trans Comput C-27:1112\u20131118","journal-title":"IEEE Trans Comput"},{"key":"9050_CR12","first-page":"321","volume-title":"MICRO 39: proceedings of the 39th annual IEEE\/ACM international symposium on microarchitecture","author":"N Eisley","year":"2006","unstructured":"Eisley N, Peh L-S, Shang L (2006) In-network cache coherence. In: MICRO 39: proceedings of the 39th annual IEEE\/ACM international symposium on microarchitecture. IEEE Computer Society, Los Alamitos, pp 321\u2013332"},{"key":"9050_CR13","first-page":"182","volume-title":"ISCA \u201903: proceedings of the 30th annual international symposium on computer architecture","author":"MMK Martin","year":"2003","unstructured":"Martin MMK, Hill MD, Wood DA (2003) Token coherence: decoupling performance and correctness. In: ISCA \u201903: proceedings of the 30th annual international symposium on computer architecture. ACM, New York, pp 182\u2013193"},{"key":"9050_CR14","first-page":"346","volume-title":"ISCA \u201905: proceedings of the 32nd annual international symposium on computer architecture","author":"E Speight","year":"2005","unstructured":"Speight E, Shafi H, Zhang L, Rajamony R (2005) Adaptive mechanisms and policies for managing cache hierarchies in chip multiprocessors. In: ISCA \u201905: proceedings of the 32nd annual international symposium on computer architecture. IEEE Computer Society, Los Alamitos, pp 346\u2013356"},{"key":"9050_CR15","doi-asserted-by":"crossref","first-page":"97","DOI":"10.1145\/1024393.1024406","volume-title":"ASPLOS-XI: proceedings of the 11th international conference on architectural support for programming languages and operating systems","author":"J Huh","year":"2004","unstructured":"Huh J, Chang J, Burger D, Sohi GS (2004) Coherence decoupling: making use of incoherence. In: ASPLOS-XI: proceedings of the 11th international conference on architectural support for programming languages and operating systems. ACM, New York, pp 97\u2013106"},{"key":"9050_CR16","doi-asserted-by":"crossref","first-page":"48","DOI":"10.1109\/ISCA.1995.524548","volume-title":"ISCA \u201995: proceedings of the 22nd annual international symposium on computer architecture","author":"AR Lebeck","year":"1995","unstructured":"Lebeck AR, Wood DA (1995) Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors. In: ISCA \u201995: proceedings of the 22nd annual international symposium on computer architecture. ACM, New York, pp 48\u201359"},{"key":"9050_CR17","doi-asserted-by":"crossref","first-page":"139","DOI":"10.1145\/339647.339669","volume-title":"ISCA \u201900: proceedings of the 27th annual international symposium on computer architecture","author":"A-C Lai","year":"2000","unstructured":"Lai A-C, Falsafi B (2000) Selective, accurate, and timely self-invalidation using last-touch prediction. In: ISCA \u201900: proceedings of the 27th annual international symposium on computer architecture. ACM, New York, pp 139\u2013148"},{"key":"9050_CR18","doi-asserted-by":"crossref","first-page":"255","DOI":"10.1145\/285930.285984","volume-title":"ISCA \u201998: 25 years of the international symposium on computer architecture (selected papers)","author":"JR Goodman","year":"1998","unstructured":"Goodman JR (1998) Using cache memory to reduce processor-memory traffic. In: ISCA \u201998: 25 years of the international symposium on computer architecture (selected papers). ACM, New York, pp 255\u2013262"},{"key":"9050_CR19","first-page":"348","volume-title":"ISCA \u201984: proceedings of the 11th annual international symposium on computer architecture","author":"MS Papamarcos","year":"1984","unstructured":"Papamarcos MS, Patel JH (1984) A low-overhead coherence solution for multiprocessors with private cache memories. In: ISCA \u201984: proceedings of the 11th annual international symposium on computer architecture. ACM, New York, pp 348\u2013354"},{"key":"9050_CR20","first-page":"443","volume-title":"MICRO 39: proceedings of the 39th annual IEEE\/ACM international symposium on microarchitecture","author":"BM Beckmann","year":"2006","unstructured":"Beckmann BM, Marty MR, Wood DA (2006) Asr: adaptive selective replication for cmp caches. In: MICRO 39: proceedings of the 39th annual IEEE\/ACM international symposium on microarchitecture. IEEE Computer Society, Los Alamitos, pp 443\u2013454"},{"key":"9050_CR21","first-page":"77","volume-title":"CODES 2000","author":"S Yoo","year":"2000","unstructured":"Yoo S, Rha K, Cho Y, Jung J, Choi K (2000) Performance estimation of multiple-cache ip-based systems: case study of an interdependency problem and application of an extended shared memory model. In: CODES 2000. ACM, New York, pp 77\u201381"},{"key":"9050_CR22","first-page":"146","volume-title":"SIGMETRICS\u2019 93: proceedings of the 1993 ACM SIGMETRICS conference on measurement and modeling of computer systems","author":"SR Glodsmchidt","year":"1993","unstructured":"Glodsmchidt SR, Hennessy JL (1993) The accuracy of trace-driven simulations of multiprocessors. In: SIGMETRICS\u2019 93: proceedings of the 1993 ACM SIGMETRICS conference on measurement and modeling of computer systems. ACM, New York, pp 146\u2013157"},{"key":"9050_CR23","first-page":"43","volume-title":"MICRO 37: proceedings of the 37th annual IEEE\/ACM international symposium on microarchitecture","author":"DG Perez","year":"2004","unstructured":"Perez DG, Mouchard G, Temam O (2004) Microlib: A case for the quantitative comparison of micro-architecture mechanisms. In: MICRO 37: proceedings of the 37th annual IEEE\/ACM international symposium on microarchitecture, Washington, DC, USA. IEEE Computer Society, Los Alamitos, pp 43\u201354"},{"key":"9050_CR24","doi-asserted-by":"crossref","unstructured":"Beltrame G, Sciuto D, Silvano C, Lyonnard D, Pilkington C (2006) Exploiting tlm and object introspection for system-level simulation. In: DATE \u201906: proceedings of the conference on design, automation and test in Europe, Leuven, Belgium. European Design and Automation Association, pp 100\u2013105","DOI":"10.1109\/DATE.2006.244004"},{"key":"9050_CR25","doi-asserted-by":"crossref","first-page":"91","DOI":"10.1145\/1450135.1450156","volume-title":"CODES\/ISSS \u201908: proceedings of the 6th IEEE\/ACM\/IFIP international conference on hardware\/software codesign and system synthesis","author":"FE Ophelders","year":"2008","unstructured":"Ophelders FE, Chakraborty S, Corporaal H (2008) Intra- and inter-processor hybrid performance modeling for mpsoc architectures. In: CODES\/ISSS \u201908: proceedings of the 6th IEEE\/ACM\/IFIP international conference on hardware\/software codesign and system synthesis, New York, NY, USA. ACM, New York, pp 91\u201396"},{"issue":"4","key":"9050_CR26","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1145\/1105734.1105747","volume":"33","author":"MMK Martin","year":"2005","unstructured":"Martin MMK, Sorin DJ, Beckmann BM, Marty MR, Xu M, Alameldeen AR, Moore KE, Hill MD, Wood DA (2005) Multifacet\u2019s general execution-driven multiprocessor simulator (gems) toolset. SIGARCH Comput Archit News 33(4):92\u201399","journal-title":"SIGARCH Comput Archit News"},{"key":"9050_CR27","doi-asserted-by":"crossref","first-page":"108","DOI":"10.1145\/511334.511349","volume-title":"SIGMETRICS \u201902: proceedings of the 2002 ACM SIGMETRICS international conference on measurement and modeling of computer systems","author":"CJ Mauer","year":"2002","unstructured":"Mauer CJ, Hill MD, Wood DA (2002) Full-system timing-first simulation. In: SIGMETRICS \u201902: proceedings of the 2002 ACM SIGMETRICS international conference on measurement and modeling of computer systems, New York, NY, USA. ACM, New York, pp 108\u2013116"},{"issue":"1","key":"9050_CR28","doi-asserted-by":"crossref","first-page":"18","DOI":"10.1145\/160551.160553","volume":"27","author":"D Mosberger","year":"1993","unstructured":"Mosberger D (1993) Memory consistency models. SIGOPS Oper Syst Rev 27(1):18\u201326","journal-title":"SIGOPS Oper Syst Rev"},{"key":"9050_CR29","doi-asserted-by":"crossref","unstructured":"Condon A, Hill M, Plakal M, Sorin D (1999) Using lamport clocks to reason about relaxed memory models. In: Proceedings of the fifth international symposium on high-performance computer architecture, January 1999, pp\u00a0270\u2013278","DOI":"10.1109\/HPCA.1999.744379"},{"key":"9050_CR30","doi-asserted-by":"crossref","first-page":"558","DOI":"10.1145\/359545.359563","volume":"21","author":"L Lamport","year":"1978","unstructured":"Lamport L (1978) Time, clocks and the ordering of events in a distributed system. Commun ACM 21:558\u2013565","journal-title":"Commun ACM"},{"key":"9050_CR31","doi-asserted-by":"crossref","first-page":"997","DOI":"10.1145\/1403375.1403616","volume-title":"DATE \u201908: proceedings of the conference on design, automation and test in Europe","author":"PG Massas de","year":"2008","unstructured":"de Massas PG, P\u00e9trot F (2008) Comparison of memory write policies for noc based multicore cache coherent systems. In: DATE \u201908: proceedings of the conference on design, automation and test in Europe, New York, NY, USA. ACM, New York, pp 997\u20131002"},{"key":"9050_CR32","unstructured":"Soclib project. http:\/\/www.soclib.lip6.fr\/Home.html"},{"key":"9050_CR33","unstructured":"Virtual component interface standard (ocb 2 2.0), VSI Alliance (2000)"},{"key":"9050_CR34","volume-title":"ISCA \u201995: proceedings of the 22nd annual international symposium on computer architecture","author":"S Cameron","year":"1995","unstructured":"Cameron S, Moriyoshi W, Evan O, Jaswinder T, Sing P, Gupta A (1995) The splash-2 programs: characterization and methodological considerations. In: ISCA \u201995: proceedings of the 22nd annual international symposium on computer architecture. IEEE Computer Society, Los Alamitos"},{"key":"9050_CR35","doi-asserted-by":"crossref","unstructured":"Petrot F, Gomez P (2003) Lightweight implementation of the posix threads api for an on-chip mips multiprocessor with vci interconnect. In: Design, automation and test in Europe conference and exhibition, pp\u00a051\u201356","DOI":"10.1109\/DATE.2003.1253805"}],"container-title":["Design Automation for Embedded Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10617-010-9050-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10617-010-9050-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10617-010-9050-6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,30]],"date-time":"2019-05-30T15:29:34Z","timestamp":1559230174000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10617-010-9050-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,1,29]]},"references-count":35,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2010,3]]}},"alternative-id":["9050"],"URL":"https:\/\/doi.org\/10.1007\/s10617-010-9050-6","relation":{},"ISSN":["0929-5585","1572-8080"],"issn-type":[{"value":"0929-5585","type":"print"},{"value":"1572-8080","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,1,29]]}}}