{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,4]],"date-time":"2025-05-04T21:40:05Z","timestamp":1746394805140,"version":"3.40.4"},"reference-count":36,"publisher":"Springer Science and Business Media LLC","issue":"3-4","license":[{"start":{"date-parts":[[2013,9,1]],"date-time":"2013-09-01T00:00:00Z","timestamp":1377993600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Des Autom Embed Syst"],"published-print":{"date-parts":[[2013,9]]},"DOI":"10.1007\/s10617-014-9148-3","type":"journal-article","created":{"date-parts":[[2014,9,26]],"date-time":"2014-09-26T10:21:42Z","timestamp":1411726902000},"page":"485-506","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Effective file data-block placement for different types of page cache on hybrid main memory architectures"],"prefix":"10.1007","volume":"17","author":[{"given":"Penglin","family":"Dai","sequence":"first","affiliation":[]},{"given":"Qingfeng","family":"Zhuge","sequence":"additional","affiliation":[]},{"given":"Xianzhang","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Weiwen","family":"Jiang","sequence":"additional","affiliation":[]},{"given":"Edwin H.-M.","family":"Sha","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2014,9,27]]},"reference":[{"key":"9148_CR1","unstructured":"Absar MJ, Catthoor F (2005) Compiler-based approach for exploiting scratch-pad in presence of irregular array access. In: Proceedings of IEEE design, automation and test in Europe, pp 1162\u20131167"},{"issue":"1","key":"9148_CR2","doi-asserted-by":"crossref","first-page":"6","DOI":"10.1145\/581888.581891","volume":"1","author":"O Avissar","year":"2002","unstructured":"Avissar O, Barua R, Stewart D (2002) An optimal memory allocation scheme for scratch-pad-based embedded systems. ACM Trans Embed Comput Syst 1(1):6\u201326","journal-title":"ACM Trans Embed Comput Syst"},{"key":"9148_CR3","doi-asserted-by":"crossref","unstructured":"Bez R (2009) Chalcogenide pcm: a memory technology for next decade. In: IEEE international electron devices meeting (IEDM), pp 1\u20134.","DOI":"10.1109\/IEDM.2009.5424415"},{"key":"9148_CR4","volume-title":"Computer systems: a programmer\u2019s perspective","author":"R Bryant","year":"2003","unstructured":"Bryant R, David Richard O (2003) Computer systems: a programmer\u2019s perspective. Prentice Hall, Upper Saddle River"},{"issue":"2","key":"9148_CR5","first-page":"5","volume":"6","author":"YH Chang","year":"2010","unstructured":"Chang YH, Lin JH, Hsieh JW, Kuo TW (2010) A strategy to emulate nor flash with nand flash. ACM Tran Storage 6(2):5","journal-title":"ACM Tran Storage"},{"key":"9148_CR6","doi-asserted-by":"crossref","unstructured":"Chen CH, Hsiu PC, Kuo TW, Yang CL, Wang CY (2012) Age-based pcm wear leveling with nearly zero search cost. In: 49th ACM\/EDAC\/IEEE design automation conference (DAC), pp 453\u2013458.","DOI":"10.1145\/2228360.2228439"},{"key":"9148_CR7","doi-asserted-by":"crossref","unstructured":"Chen G, Ozturk O, Kandemir M, Karakoy M (2006) Dynamic scratch-pad memory management for irregular array access patterns. In: Proceedings of the conference on design, automation and test in Europe: Proceedings, European Design and Automation Association, pp 931\u2013936.","DOI":"10.1109\/DATE.2006.243810"},{"key":"9148_CR8","doi-asserted-by":"crossref","unstructured":"Dhiman G, Ayoub R, Rosing T (2009) Pdram: a hybrid pram and dram main memory system. In: 46th ACM\/IEEE DAC\u201909 design automation conference, pp 664\u2013669.","DOI":"10.1145\/1629911.1630086"},{"key":"9148_CR9","volume-title":"Understanding the Linux virtual memory manager","author":"M Gorman","year":"2004","unstructured":"Gorman M (2004) Understanding the Linux virtual memory manager. Prentice Hall, Upper Saddle River"},{"key":"9148_CR10","doi-asserted-by":"crossref","unstructured":"Guthaus MR, Ringenberg JS, Ernst D, Austin TM, Mudge T, Brown RB (2001) Mibench: a free, commercially representative embedded benchmark suite. In: IEEE international workshop on workload characterization, WWC-4, pp 3\u201314.","DOI":"10.1109\/WWC.2001.990739"},{"key":"9148_CR11","doi-asserted-by":"crossref","DOI":"10.1145\/143365.143511","volume-title":"Application-controlled physical memory using external page-cache management","author":"K Harty","year":"1992","unstructured":"Harty K, Cheriton DR (1992) Application-controlled physical memory using external page-cache management. ACM, New York"},{"key":"9148_CR12","doi-asserted-by":"crossref","unstructured":"Hosomi M, Yamagishi H, Yamamoto T, Bessho K, Higo Y, Yamane K,Yamada H, Shoji M, Hachino H, Fukumoto C, et al (2005) A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-ram. In: IEEE international electron devices meeting, 2005. IEDM Technical Digest, pp 459\u2013462","DOI":"10.1109\/IEDM.2005.1609379"},{"key":"9148_CR13","unstructured":"Hu J, Xue CJ, Zhuge Q, Tseng WC, Sha EM (2011) Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory. In: IEEE design, automation and test in Europe conference and exhibition (DATE), pp 1\u20136."},{"key":"9148_CR14","doi-asserted-by":"crossref","unstructured":"Hu J, Xie M, Pan C, Zhuge Q, Sha EM (2014) Low overhead software wear leveling for hybrid pcm + dram main memory on embedded systems. IEEE Trans Very Large Scale Syst 41:1","DOI":"10.1109\/TVLSI.2014.2321571"},{"issue":"3","key":"9148_CR15","first-page":"77","volume":"12","author":"J Hu","year":"2013","unstructured":"Hu J, Xue C, Zhuge Q, Tseng W, Sha EM (2013) Write activity reduction on non-volatile main memories for embedded chip multiprocessors. ACM Trans Embed Comput Syst 12(3):77","journal-title":"ACM Trans Embed Comput Syst"},{"key":"9148_CR16","first-page":"1","volume":"55","author":"J Hu","year":"2013","unstructured":"Hu J, Xue C, Zhuge Q, Tseng W, Sha EM (2013) Scheduling to optimize cache utilization for non-volatile main memories. IEEE Trans Comput 55:1","journal-title":"IEEE Trans Comput"},{"key":"9148_CR17","doi-asserted-by":"crossref","unstructured":"Huang PC, Chang YH, Kuo TW (2012) Joint management of ram and flash memory with access pattern considerations. In: 49th ACM\/EDAC\/IEEE design automation conference (DAC), pp 882\u2013887.","DOI":"10.1145\/2228360.2228518"},{"issue":"10","key":"9148_CR18","doi-asserted-by":"crossref","first-page":"191","DOI":"10.1145\/191081.191112","volume":"29","author":"JF Karpovich","year":"1994","unstructured":"Karpovich JF, Grimshaw AS, French JC (1994) Extensible file system (elfs): an object-oriented approach to high performance file i\/o. ACM SIGPLAN Not 29(10):191\u2013204","journal-title":"ACM SIGPLAN Not"},{"key":"9148_CR19","unstructured":"Kesavan M, Gavrilovska A, Schwan K (2010) On disk i\/o scheduling in virtual machines. In: Proceedings of the 2nd conference on I\/O virtualization, USENIX Association, p 6"},{"key":"9148_CR20","unstructured":"Liu D, Wang T, Wang Y, Qin Z, Shao Z (2012) A block-level flash memorymanagement scheme for reducing write activities in pcm-based embedded systems. In: Proceedings of the conference on design, automation and test in Europe, EDA Consortium, pp 1447\u20131450"},{"key":"9148_CR21","unstructured":"Liu D, Wang T, Wang Y, Shao Z, Zhuge Q, Sha EHM (2013) Curling-pcm: application-specific wear leveling for phase change memory based embedded systems. In: ASP-DAC, pp 279\u2013284."},{"key":"9148_CR22","doi-asserted-by":"crossref","unstructured":"Liu D, Wang T, Wang Y, Qin Z, and Shao Z (2011) Pcm-ftl: a write-activity-aware nand flash memory management scheme for pcm-based embedded systems. In 2011 IEEE real-time systems symposium (RTSS), pp 357\u2013366.","DOI":"10.1109\/RTSS.2011.40"},{"key":"9148_CR23","doi-asserted-by":"crossref","unstructured":"Liu T, Zhao Y, Xue CJ, Li M (2011) Power-aware variable partitioning for dsps with hybrid pram and dram main memory. In: 48th ACM\/EDAC\/IEEE design automation conference (DAC), pp 405\u2013410.","DOI":"10.1145\/2024724.2024819"},{"issue":"1","key":"9148_CR24","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1145\/65762.65765","volume":"23","author":"J Ousterhout","year":"1989","unstructured":"Ousterhout J, Douglis F (1989) Beating the i\/o bottleneck: a case for log-structured file systems. ACM SIGOPS Oper Syst Rev 23(1):11\u201328","journal-title":"ACM SIGOPS Oper Syst Rev"},{"key":"9148_CR25","doi-asserted-by":"crossref","unstructured":"Ozturk O, Kandemir M, Narayanan SHK (2008) A scratch-pad memory aware dynamic loop scheduling algorithm. In: 9th International symposium on IEEE quality electronic design, ISQED, pp 738\u2013743.","DOI":"10.1109\/ISQED.2008.4479830"},{"key":"9148_CR26","doi-asserted-by":"crossref","unstructured":"Panda PR, Dutt ND, Nicolau A (1997) Efficient utilization of scratch-pad memory in embedded processor applications. In: Proceedings of the 1997 European conference on design and test, IEEE computer society, p 7.","DOI":"10.1109\/EDTC.1997.582323"},{"key":"9148_CR27","doi-asserted-by":"crossref","first-page":"75","DOI":"10.1145\/2007477.1952694","volume":"46","author":"E Park","year":"2011","unstructured":"Park E, Egger B, Lee J (2011) Fast and space-efficient virtual machine checkpointing. ACM SIGPLAN Not 46:75\u201386","journal-title":"ACM SIGPLAN Not"},{"key":"9148_CR28","doi-asserted-by":"crossref","unstructured":"Park H, Yoo S, Lee S (2011) Power management of hybrid dram\/pram-based main memory. In: Proceedings of the 48th design automation conference, ACM, pp 59\u201364.","DOI":"10.1145\/2024724.2024738"},{"issue":"3","key":"9148_CR29","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1145\/1555815.1555760","volume":"37","author":"MK Qureshi","year":"2009","unstructured":"Qureshi MK, Srinivasan V, Rivers JA (2009) Scalable high performance main memory system using phase-change memory technology. ACM SIGARCH Comput Archit News 37(3):24\u201333","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"9148_CR30","doi-asserted-by":"crossref","unstructured":"Shao Z, Liu Y, Chen Y, Li T (2012) Utilizing pcm for energy optimization in embedded systems. In: IEEE computer society annual symposium on VLSI (ISVLSI), pp 398\u2013403.","DOI":"10.1109\/ISVLSI.2012.81"},{"key":"9148_CR31","doi-asserted-by":"crossref","unstructured":"Shi L, Xue CJ, Hu J, Tseng WC, Zhou X, Sha EHM (2010) Write activity reduction on flash main memory via smart victim cache. In: Proceedings of the 20th symposium on Great lakes symposium on VLSI, ACM, pp 91\u201394.","DOI":"10.1145\/1785481.1785503"},{"key":"9148_CR32","doi-asserted-by":"crossref","unstructured":"Shi L, Xue CJ, Zhou X (2011) Cooperating write buffer cache and virtual memory management for flash memory based systems. In: 17th IEEE real-time and embedded technology and applications symposium (RTAS), pp 147\u2013156.","DOI":"10.1109\/RTAS.2011.22"},{"key":"9148_CR33","doi-asserted-by":"crossref","unstructured":"Udayakumaran S, Barua R (2006) An integrated scratch-pad allocator for affine and non-affine code. In: Proceedings of the conference on design, automation and test in Europe: Proceedings, European design and automation association, pp 925\u2013930.","DOI":"10.1109\/DATE.2006.243809"},{"issue":"2","key":"9148_CR34","doi-asserted-by":"crossref","first-page":"472","DOI":"10.1145\/1151074.1151085","volume":"5","author":"S Udayakumaran","year":"2006","unstructured":"Udayakumaran S, Dominguez A, Barua R (2006) Dynamic allocation for scratch-pad memory using compile-time decisions. ACM Trans Embed Comput Syst 5(2):472\u2013511","journal-title":"ACM Trans Embed Comput Syst"},{"issue":"99","key":"9148_CR35","first-page":"1","volume":"29","author":"Y Wang","year":"2014","unstructured":"Wang Y, Shao Z, Chan H, Bathen L, Dutt N (2014) A reliability enhanced address mapping strategy for three-dimensional (3D) nand flash memory. IEEE Trans Very Large Scale Syst 29(99):1","journal-title":"IEEE Trans Very Large Scale Syst"},{"issue":"6","key":"9148_CR36","doi-asserted-by":"crossref","first-page":"3253","DOI":"10.1109\/TSP.2012.2189768","volume":"60","author":"Q Zhuge","year":"2012","unstructured":"Zhuge Q, Guo Y, Hu J, Tseng WC, Xue S, Sha EM (2012) Minimizing access cost for multiple types of memory units in embedded systems through data allocation and scheduling. IEEE Trans Signal Process 60(6):3253\u20133263","journal-title":"IEEE Trans Signal Process"}],"container-title":["Design Automation for Embedded Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10617-014-9148-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10617-014-9148-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10617-014-9148-3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,4]],"date-time":"2025-05-04T21:01:29Z","timestamp":1746392489000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10617-014-9148-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":36,"journal-issue":{"issue":"3-4","published-print":{"date-parts":[[2013,9]]}},"alternative-id":["9148"],"URL":"https:\/\/doi.org\/10.1007\/s10617-014-9148-3","relation":{},"ISSN":["0929-5585","1572-8080"],"issn-type":[{"type":"print","value":"0929-5585"},{"type":"electronic","value":"1572-8080"}],"subject":[],"published":{"date-parts":[[2013,9]]}}}