{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:53:37Z","timestamp":1780674817127,"version":"3.54.1"},"reference-count":35,"publisher":"Springer Science and Business Media LLC","issue":"1-2","license":[{"start":{"date-parts":[[2018,5,2]],"date-time":"2018-05-02T00:00:00Z","timestamp":1525219200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Des Autom Embed Syst"],"published-print":{"date-parts":[[2018,6]]},"DOI":"10.1007\/s10617-018-9207-2","type":"journal-article","created":{"date-parts":[[2018,5,2]],"date-time":"2018-05-02T09:49:40Z","timestamp":1525254580000},"page":"117-140","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":8,"title":["Inter-FPGA interconnect topologies exploration for multi-FPGA systems"],"prefix":"10.1007","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5220-4908","authenticated-orcid":false,"given":"Umer","family":"Farooq","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Habib","family":"Mehrez","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Muhammad Khurram","family":"Bhatti","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2018,5,2]]},"reference":[{"key":"9207_CR1","unstructured":"Santarini M (2005) Asic prototyping: Make versus buy, EDN, vol\u00a011"},{"key":"9207_CR2","unstructured":"Sigenics: Custom asic calculator, \n                    http:\/\/www.sigenics.com\/page\/custom-asic-cost-calculator\n                    \n                   (2017)"},{"key":"9207_CR3","unstructured":"AMD, \n                    http:\/\/techreport.com\/news\/13721\/chip-problem-limits-supply-of-quad-core-opterons\n                    \n                   (2007)"},{"key":"9207_CR4","unstructured":"Pentium, \n                    https:\/\/en.wikipedia.org\/wiki\/pentium_fdiv_bug\n                    \n                   (1994)"},{"key":"9207_CR5","unstructured":"Huang C-Y, Yin Y-F, Hsu C-J, Huang TB, Chang T-M (2011) Soc hw\/sw verification and validation. In: 16th Asia and South Pacific design automation conference (ASP-DAC 2011). IEEE, pp 297\u2013300"},{"key":"9207_CR6","unstructured":"Cadence, \n                    https:\/\/www.cadence.com\/content\/cadence-www\/global\/en_us\/home \/tools\/system-design-and-verification\/simulation-and-testbench-verification\/incisive-enterprise-simulator.html\n                    \n                   (2017)"},{"key":"9207_CR7","unstructured":"Graphics M (2017) \n                    https:\/\/www.mentor.com\/products\/fv\/modelsim\/"},{"key":"9207_CR8","unstructured":"Vcs: A functional veriifcation solution by synopsys, \n                    http:\/\/www.synopsys.com\/Tools\/Verification\/FunctionalVerification\/Pages\/VCS.aspx\n                    \n                   (2017)"},{"key":"9207_CR9","unstructured":"Series CP ( 2017) \n                    http:\/\/www.cadence.com\/products\/sd\/palladium_xp_series\/ pages \/ default.aspx"},{"key":"9207_CR10","unstructured":"Zebu-server asic emulator by synopsys, \n                    http:\/\/www.synopsys.com\/tools\/verification \/hardware-verification\/emulation\/Pages\/default.aspx\n                    \n                   (2017)"},{"key":"9207_CR11","unstructured":"Veloce MG (2017) \n                    https:\/\/www.mentor.com\/products\/fv\/emulation-systems\/"},{"key":"9207_CR12","doi-asserted-by":"crossref","unstructured":"Kuon I, Rose J (2010) Quantifying and exploring the gap between FPGAs and ASICs, vol\u00a01, Springer, Ed. Springer US","DOI":"10.1007\/978-1-4419-0739-4_1"},{"issue":"6","key":"9207_CR13","doi-asserted-by":"publisher","first-page":"609","DOI":"10.1109\/43.640619","volume":"16","author":"J Babb","year":"1997","unstructured":"Babb J, Tessier R, Dahl M, Hanono S, Hoki D, Agarwal A (1997) Logic emulation with virtual wires. IEEE Trans Comput-Aided Des Integr Circuits Syst 16(6):609\u2013626","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"9207_CR14","doi-asserted-by":"crossref","unstructured":"Krupnova H (2004) Mapping multi-million gate SoCs on FPGAs: industrial methodology and experience. In: Design, automation and test in europe conference and exhibition, 2004. proceedings, vol\u00a02. pp 1236\u20131241","DOI":"10.1109\/DATE.2004.1269065"},{"key":"9207_CR15","doi-asserted-by":"publisher","unstructured":"Asaad S, Bellofatto R, Brezzo B, Haymes C, Kapur M, Parker B, Roewer T, Saha P, Takken T, Tierno J (2012) A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. In: Proceedings of the ACM\/SIGDA international symposium on field programmable gate arrays, ser. FPGA \u201912. ACM, New York, pp 153\u2013162. [Online]. \n                    https:\/\/doi.org\/10.1145\/2145694.2145720","DOI":"10.1145\/2145694.2145720"},{"key":"9207_CR16","unstructured":"Yang S (1991) Logic synthesis and optimization benchmarks user guide, version 3.0"},{"key":"9207_CR17","doi-asserted-by":"publisher","unstructured":"Farooq U, Parvez H, Mehrez H, Marrakchi Z (2012) A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA. Microprocess Microsyst 36(8):588\u2013605. [Online]. \n                    https:\/\/doi.org\/10.1016\/j.micpro.2012.06.012","DOI":"10.1016\/j.micpro.2012.06.012"},{"issue":"9","key":"9207_CR18","doi-asserted-by":"publisher","first-page":"1011","DOI":"10.1109\/43.863641","volume":"19","author":"D Stroobandt","year":"2000","unstructured":"Stroobandt D, Verplaetse P, Van Campenhout J (2000) Generating synthetic benchmark circuits for evaluating cad tools. IEEE Trans Comput-Aided Des Integr Circuits Syst 19(9):1011\u20131022","journal-title":"IEEE Trans Comput-Aided Des Integr Circuits Syst"},{"key":"9207_CR19","unstructured":"Pouillon N, Greiner A (2010) Soc lib project. [Online]. \n                    https:\/\/www.asim.lip6.fr\/trac\/dsx\/"},{"key":"9207_CR20","doi-asserted-by":"crossref","unstructured":"Panades IM, Greiner A, Sheibanyrad A (2006) A low cost network-on-chip with guaranteed service well suited to the gals approach. In: Nano-networks and workshops, 2006. NanoNet \u201906. 1st international conference on, 1\u20135","DOI":"10.1109\/NANONET.2006.346219"},{"key":"9207_CR21","unstructured":"Certify, \n                    http:\/\/www.synopsys.com\/Prototyping\/FPGA BasedPrototyping\/Pages\/Certify.aspx\n                    \n                   (2017)"},{"key":"9207_CR22","doi-asserted-by":"crossref","unstructured":"Inagi M, Takashima Y, Nakamura Y (2009) Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems. In: Field programmable logic and applications, 2009. FPL 2009. International conference on, pp 212\u2013217","DOI":"10.1109\/FPL.2009.5272309"},{"key":"9207_CR23","unstructured":"Turki M, Marrakchi Z, Mehrez H, Abid M (2013) 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25\u201327, 2013. Springer, ch. Iterative routing algorithm of inter-FPGA signals for multi-FPGA prototyping platform, 201\u2013217"},{"key":"9207_CR24","unstructured":"DiniGroup, \n                    http:\/\/www.dinigroup.com\/\n                    \n                   (2017)"},{"key":"9207_CR25","doi-asserted-by":"crossref","unstructured":"Tang Q, Mehrez H, Tuna M (Oct 2013) Routing algorithm for multi-FPGA based systems using multi-point physical tracks. In: Rapid system prototyping (RSP), 2013 international symposium on, pp 2\u20138","DOI":"10.1109\/RSP.2013.6683951"},{"key":"9207_CR26","doi-asserted-by":"crossref","unstructured":"Farooq U, Chotin-Avot R, Azeem M, Ravoson M, Turki M, Mehrez H (2016) Inter-FPGA routing environment for performance exploration of multi-FPGA systems. In: Proceedings of the 27th international symposium on rapid system prototyping, ser. RSP \u201916. New York: ACM, pp 107\u2013113","DOI":"10.1145\/2990299.2990317"},{"issue":"5","key":"9207_CR27","doi-asserted-by":"publisher","first-page":"560","DOI":"10.1109\/43.506143","volume":"15","author":"C Kim","year":"1996","unstructured":"Kim C, Shin H (1996) A performance-driven logic emulation system: FPGA network design and performance-driven partitioning. IEEE Trans Comput Aided Des Integr Circuits Syst 15(5):560\u2013568","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"9207_CR28","doi-asserted-by":"crossref","unstructured":"Hauck S, Borriello G, Ebeling C (1994) Mesh routing topologies for multi-FPGA systems. In: Proceedings 1994 IEEE international conference on computer design: VLSI in computers and processors, 170\u2013177","DOI":"10.1109\/ICCD.1994.331882"},{"issue":"1","key":"9207_CR29","doi-asserted-by":"publisher","first-page":"30","DOI":"10.1109\/92.820759","volume":"8","author":"MAS Khalid","year":"2000","unstructured":"Khalid MAS, Rose J (2000) A novel and efficient routing architecture for multi-FPGA systems. IEEE Trans Very Large Scale Integr VLSI Syst 8(1):30\u201339","journal-title":"IEEE Trans Very Large Scale Integr VLSI Syst"},{"key":"9207_CR30","doi-asserted-by":"publisher","first-page":"135","DOI":"10.1561\/1000000005","volume":"2","author":"I Kuon","year":"2008","unstructured":"Kuon I, Tessier R, Rose J (2008) Fpga architecture: survey and challenges. Found Trends Electron Des Autom 2:135\u2013253","journal-title":"Found Trends Electron Des Autom"},{"key":"9207_CR31","doi-asserted-by":"crossref","unstructured":"McMurchie L, Ebeling C (1995) Pathfinder: a negotiation-based performance-driven router for FPGAs. In: ACM international symposium on field-programmable gate arrays. ACM Press, New York, 111\u2013117","DOI":"10.1109\/FPGA.1995.242049"},{"issue":"1","key":"9207_CR32","doi-asserted-by":"publisher","first-page":"269","DOI":"10.1007\/BF01386390","volume":"1","author":"EW Dijkstra","year":"1959","unstructured":"Dijkstra EW (1959) A note on two problems in connexion with graphs. Numer Math 1(1):269\u2013271","journal-title":"Numer Math"},{"key":"9207_CR33","unstructured":"Xilinx, \n                    http:\/\/www.xilinx.com\n                    \n                   (2017)"},{"key":"9207_CR34","unstructured":"Altera, \n                    http:\/\/www.altera.com\n                    \n                   (2017)"},{"key":"9207_CR35","unstructured":"Amos D, Lesea A, Richter R (2011) FPGA-based prototyping methodology manual: best practices in design-for-prototyping, Synopsys, Ed. Synopsys"}],"container-title":["Design Automation for Embedded Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10617-018-9207-2\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10617-018-9207-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10617-018-9207-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T19:27:00Z","timestamp":1556738820000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10617-018-9207-2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,5,2]]},"references-count":35,"journal-issue":{"issue":"1-2","published-print":{"date-parts":[[2018,6]]}},"alternative-id":["9207"],"URL":"https:\/\/doi.org\/10.1007\/s10617-018-9207-2","relation":{},"ISSN":["0929-5585","1572-8080"],"issn-type":[{"value":"0929-5585","type":"print"},{"value":"1572-8080","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,5,2]]},"assertion":[{"value":"14 August 2017","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"20 April 2018","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"2 May 2018","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}