{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T07:25:27Z","timestamp":1740122727491,"version":"3.37.3"},"reference-count":45,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2018,8,7]],"date-time":"2018-08-07T00:00:00Z","timestamp":1533600000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Des Autom Embed Syst"],"published-print":{"date-parts":[[2018,12]]},"DOI":"10.1007\/s10617-018-9214-3","type":"journal-article","created":{"date-parts":[[2018,8,7]],"date-time":"2018-08-07T04:11:42Z","timestamp":1533615102000},"page":"293-314","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["The Agamid design-space exploration framework"],"prefix":"10.1007","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1412-797X","authenticated-orcid":false,"given":"Daniel","family":"Gregorek","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alberto","family":"Garcia-Ortiz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2018,8,7]]},"reference":[{"key":"9214_CR1","doi-asserted-by":"crossref","unstructured":"Ahn JH, Li S, Seongil O, Jouppi NP (2013) Mcsima+: a manycore simulator with application-level+ simulation and detailed microarchitecture modeling. In: 2013 IEEE international symposium on performance analysis of systems and software (ISPASS), IEEE, pp 74\u201385","DOI":"10.1109\/ISPASS.2013.6557148"},{"key":"9214_CR2","doi-asserted-by":"crossref","unstructured":"Bergamaschi R, Nair I, Dittmann G, Patel H, Janssen G, Dhanwada N, Buyuktosunoglu A, Acar E, Nam GJ, Kucar D, et al (2007) Performance modeling for early analysis of multi-core systems. In: Proceedings of the 5th IEEE\/ACM international conference on Hardware\/software codesign and system synthesis, ACM, pp 209\u2013214","DOI":"10.1145\/1289816.1289868"},{"issue":"2","key":"9214_CR3","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/2024716.2024718","volume":"39","author":"N Binkert","year":"2011","unstructured":"Binkert N, Beckmann B, Black G, Reinhardt SK, Saidi A, Basu A, Hestness J, Hower DR, Krishna T, Sardashti S et al (2011) The gem5 simulator. ACM SIGARCH Comput Arch News 39(2):1\u20137","journal-title":"ACM SIGARCH Comput Arch News"},{"key":"9214_CR4","unstructured":"Cai L, Gajski D (2003) Transaction level modeling: an overview. In: Proceedings of the 1st IEEE\/ACM\/IFIP international conference on Hardware\/software codesign and system synthesis, ACM, pp 19\u201324"},{"key":"9214_CR5","unstructured":"Cain HW, Lepak KM, Schwartz BA, Lipasti MH (2002) Precise and accurate processor simulation. In: Workshop on computer architecture evaluation using commercial workloads, HPCA, vol 8"},{"key":"9214_CR6","doi-asserted-by":"crossref","unstructured":"Carvalho E, Calazans N, Moraes F (2007) Heuristics for dynamic task mapping in noc-based heterogeneous MPSOCS. In: 18th IEEE\/IFIP international workshop on rapid system prototyping, 2007. RSP 2007, IEEE, pp 34\u201340","DOI":"10.1109\/RSP.2007.26"},{"key":"9214_CR7","doi-asserted-by":"crossref","unstructured":"Cho S, Demetriades S, Evans S, Jin L, Lee H, Lee K, Moeng M (2008) TPTS: a novel framework for very fast manycore processor architecture simulation. In: 37th international conference on parallel processing, ICPP\u201908, IEEE, pp 446\u2013453","DOI":"10.1109\/ICPP.2008.7"},{"key":"9214_CR8","doi-asserted-by":"crossref","unstructured":"Cosnard M, Loi M (1995) Automatic task graph generation techniques. In: Proceedings of the Twenty-Eighth Hawaii international conference on system sciences, IEEE, vol\u00a02, pp 113\u2013122","DOI":"10.1109\/HICSS.1995.375471"},{"key":"9214_CR9","doi-asserted-by":"crossref","unstructured":"Dick RP, Rhodes DL, Wolf W (1998) TGFF: task graphs for free. In: Proceedings of the 6th international workshop on Hardware\/software codesign, IEEE Computer Society, pp. 97\u2013101","DOI":"10.1145\/278241.278309"},{"key":"9214_CR10","doi-asserted-by":"crossref","unstructured":"Esmaeilzadeh H, Blem E, Amant RS, Sankaralingam K, Burger D (2011) Dark silicon and the end of multicore scaling. In: 38th annual international symposium on computer architecture (ISCA), IEEE, pp. 365\u2013376","DOI":"10.1145\/2000064.2000108"},{"key":"9214_CR11","doi-asserted-by":"crossref","unstructured":"Fraboulet A, Risset T, Scherrer A (2004) Cycle accurate simulation model generation for soc prototyping. In: International workshop on embedded computer systems, Springer, pp. 453\u2013462","DOI":"10.1007\/978-3-540-27776-7_47"},{"key":"9214_CR12","unstructured":"Gailliard G (2010) Towards a common hardware\/software specification and implementation approach for distributed, rel time and embedded systems, based on middlewares and object-oriented components. Ph.D. thesis, Universit\u00e9 de Cergy Pontoise"},{"issue":"10","key":"9214_CR13","doi-asserted-by":"publisher","first-page":"1517","DOI":"10.1109\/TCAD.2009.2026356","volume":"28","author":"A Gerstlauer","year":"2009","unstructured":"Gerstlauer A, Haubelt C, Pimentel AD, Stefanov TP, Gajski DD, Teich J (2009) Electronic system-level synthesis methodologies. IEEE Trans Comput Aided Des Integr Circuits Syst 28(10):1517\u20131530","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"issue":"5","key":"9214_CR14","doi-asserted-by":"publisher","first-page":"519","DOI":"10.1007\/BF02577777","volume":"22","author":"M Girkar","year":"1994","unstructured":"Girkar M, Polychronopoulos CD (1994) The hierarchical task graph as a universal intermediate representation. Int J Parallel Program 22(5):519\u2013551","journal-title":"Int J Parallel Program"},{"key":"9214_CR15","volume-title":"Introduction to parallel computing","author":"A Grama","year":"2003","unstructured":"Grama A (2003) Introduction to parallel computing. Pearson Education, London"},{"key":"9214_CR16","doi-asserted-by":"crossref","unstructured":"Gregorek D, Garcia-Ortiz A (2014) A transaction-level framework for design-space exploration of hardware-enhanced operating systems. In: International symposium on system-on-chip (SOC 2014). IEEE","DOI":"10.1109\/ISSOC.2014.6972432"},{"key":"9214_CR17","doi-asserted-by":"crossref","unstructured":"Gregorek D, Garcia-Ortiz A (2015) The DRACON embedded many-core: hardware-enhanced run-time management using a network of dedicated control nodes. In: International symposium on VLSI (ISVLSI)","DOI":"10.1109\/ISVLSI.2015.90"},{"key":"9214_CR18","unstructured":"Gregorek D, Schmidt R, Garc\u00eda-Ortiz A (2015) Transaction level analysis for a clustered and hardware-enhanced task manager on homogeneous many-core systems. In: HIP3ES. \n                    arXiv:1502.02852"},{"key":"9214_CR19","volume-title":"System design with systemC $$^{{\\rm TM}}$$","author":"T Gr\u00f6tker","year":"2002","unstructured":"Gr\u00f6tker T, Liao S, Martin G, Swan S (2002) System design with systemC\n                    \n                      \n                    \n                    $$^{{\\rm TM}}$$\n                    \n                      \n                        \n                          \n                          TM\n                        \n                      \n                    \n                  . Springer, Berlin"},{"key":"9214_CR20","doi-asserted-by":"crossref","unstructured":"Gupta N, Mandal S, Malave J, Mandal A, Mahapatra R (2010) A hardware scheduler for real time multiprocessor system on chip. In: 23rd international conference on VLSI design, 2010. VLSID\u201910, IEEE, pp 264\u2013269","DOI":"10.1109\/VLSI.Design.2010.43"},{"key":"9214_CR21","doi-asserted-by":"crossref","unstructured":"Haririan P, Garcia-Ortiz A (2014) Non-intrusive DVFS emulation in GEM5 with application to self-aware architectures. In: 2014 9th international symposium on reconfigurable and communication-centric systems-on-chip (ReCoSoC), IEEE, pp 1\u20137","DOI":"10.1109\/ReCoSoC.2014.6861356"},{"key":"9214_CR22","unstructured":"IEEE Design Automation Standards Committee (2011) IEEE std 1666-2011, IEEE standard for standard systemc\n                    \n                      \n                    \n                    $$\\textregistered $$\n                    \n                      \n                        \u00ae\n                      \n                    \n                   language reference manual"},{"issue":"12","key":"9214_CR23","doi-asserted-by":"publisher","first-page":"1523","DOI":"10.1109\/43.898830","volume":"19","author":"K Keutzer","year":"2000","unstructured":"Keutzer K, Rabaey JM, Sangiovanni-Vincentelli A et al (2000) System-level design: orthogonalization of concerns and platform-based design. IEEE Trans Comput Aided Des Integr Circuits Syst 19(12):1523\u20131543","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"9214_CR24","doi-asserted-by":"crossref","unstructured":"Kinsy MA, Pellauer M, Devadas S (2013) Heracles: a tool for fast RTL-based design space exploration of multicore processors. In: Proceedings of the ACM\/SIGDA international symposium on Field programmable gate arrays, ACM, pp. 125\u2013134","DOI":"10.1145\/2435264.2435287"},{"key":"9214_CR25","unstructured":"Kuz I, Anderson Z, Shinde P, Roscoe T (2011) Multicore os benchmarks: we can do better. In: Proceedings of the 13th USENIX conference on Hot topics in operating systems, USENIX Association, pp 10"},{"issue":"3","key":"9214_CR26","doi-asserted-by":"publisher","first-page":"381","DOI":"10.1006\/jpdc.1999.1578","volume":"59","author":"YK Kwok","year":"1999","unstructured":"Kwok YK, Ahmad I (1999) Benchmarking and comparison of the task graph scheduling algorithms. J Parallel Distrib Comput 59(3):381\u2013422","journal-title":"J Parallel Distrib Comput"},{"issue":"6","key":"9214_CR27","doi-asserted-by":"publisher","first-page":"1080","DOI":"10.1109\/TVLSI.2012.2202699","volume":"21","author":"J Lee","year":"2013","unstructured":"Lee J, Nicopoulos C, Lee HG, Panth S, Lim SK, Kim J (2013) Isonet: hardware-based job queue management for many-core architectures. IEEE Trans Very Large Scale Integr (VLSI) Syst 21(6):1080\u20131093. \n                    https:\/\/doi.org\/10.1109\/TVLSI.2012.2202699","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"9214_CR28","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-6175-4","volume-title":"Processor and system-on-chip simulation","author":"R Leupers","year":"2010","unstructured":"Leupers R, Temam O (2010) Processor and system-on-chip simulation. Springer, Berlin"},{"key":"9214_CR29","doi-asserted-by":"crossref","unstructured":"Lindh L (1991) Fastchart-a fast time deterministic CPU and hardware based real-time-kernel. In: Proceedings of Euromicro\u201991 workshop on real time systems, IEEE, pp 36\u201340","DOI":"10.1109\/EMWRT.1991.144077"},{"key":"9214_CR30","doi-asserted-by":"crossref","unstructured":"Liu W, Xu J, Wu X, Ye Y, Wang X, Zhang W, Nikdast M, Wang Z (2011) A NOC traffic suite based on real applications. In: IEEE computer society annual symposium on VLSI (ISVLSI), IEEE, pp 66\u201371","DOI":"10.1109\/ISVLSI.2011.49"},{"issue":"6","key":"9214_CR31","doi-asserted-by":"publisher","first-page":"190","DOI":"10.1145\/1064978.1065034","volume":"40","author":"Chi-Keung Luk","year":"2005","unstructured":"Luk CK, Cohn R, Muth R, Patil H, Klauser A, Lowney G, Wallace S, Reddi VJ, Hazelwood K (2005) Pin: building customized program analysis tools with dynamic instrumentation. In: ACM sigplan notices, ACM, vol 40, pp 190\u2013200","journal-title":"ACM SIGPLAN Notices"},{"key":"9214_CR32","unstructured":"Mariani G, Palermo G, Zaccaria V, Silvano C (2012) Evaluating run-time resource management policies for multi-core embedded platforms with the EMME evaluation framework. In: ARCS workshops (ARCS), IEEE, pp 1\u20136"},{"key":"9214_CR33","doi-asserted-by":"crossref","unstructured":"Miller JE, Kasture H, Kurian G, Gruenwald III C, Beckmann N, Celio C, Eastep J, Agarwal A (2010) Graphite: a distributed parallel simulator for multicores. In: 2010 IEEE 16th international symposium on high performance computer architecture (HPCA), IEEE, pp 1\u201312","DOI":"10.1109\/HPCA.2010.5416635"},{"issue":"2","key":"9214_CR34","doi-asserted-by":"publisher","first-page":"251","DOI":"10.1007\/s11265-008-0305-4","volume":"60","author":"V Nollet","year":"2010","unstructured":"Nollet V, Verkest D, Corporaal H (2010) A safari through the MPSOC run-time management jungle. J Signal Process Syst 60(2):251\u2013268","journal-title":"J Signal Process Syst"},{"key":"9214_CR35","doi-asserted-by":"crossref","unstructured":"Perez JM, Badia RM, Labarta J (2008) A dependency-aware task-based programming environment for multi-core architectures. In: 2008 IEEE international conference on cluster computing, IEEE, pp 142\u2013151","DOI":"10.1109\/CLUSTR.2008.4663765"},{"key":"9214_CR36","unstructured":"Podobas A, Brorsson M (2010) A comparison of some recent task-based parallel programming models. In: MULTIPROG\u20192010, Jan 2010, Pisa"},{"key":"9214_CR37","unstructured":"Rhoads S (2006) Plasma-most MIPS i (tm) opcodes: overview. Internet: \n                    http:\/\/opencores.org\/project\n                    \n                  , plasma, 2 May 2012"},{"issue":"4","key":"9214_CR38","doi-asserted-by":"publisher","first-page":"34","DOI":"10.1109\/88.473612","volume":"3","author":"M Rosenblum","year":"1995","unstructured":"Rosenblum M, Herrod S, Witchel E, Gupta A et al (1995) Complete computer system simulation: the simos approach. IEEE Parallel Distrib Technol Syst Appl 3(4):34\u201343","journal-title":"IEEE Parallel Distrib Technol Syst Appl"},{"issue":"3","key":"9214_CR39","doi-asserted-by":"publisher","first-page":"475","DOI":"10.1145\/2508148.2485963","volume":"41","author":"Daniel Sanchez","year":"2013","unstructured":"Sanchez D, Kozyrakis C (2013) ZSIM: fast and accurate microarchitectural simulation of thousand-core systems. In: ACM SIGARCH computer architecture news, ACM, vol 41, pp 475\u2013486","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"9214_CR40","doi-asserted-by":"publisher","DOI":"10.1002\/0470121173","volume-title":"Task scheduling for parallel systems","author":"O Sinnen","year":"2007","unstructured":"Sinnen O (2007) Task scheduling for parallel systems, vol 60. Wiley, New York"},{"issue":"5","key":"9214_CR41","doi-asserted-by":"publisher","first-page":"379","DOI":"10.1002\/jos.116","volume":"5","author":"T Tobita","year":"2002","unstructured":"Tobita T, Kasahara H (2002) A standard task graph set for fair evaluation of multiprocessor scheduling algorithms. J Sched 5(5):379\u2013394","journal-title":"J Sched"},{"key":"9214_CR42","doi-asserted-by":"publisher","first-page":"46","DOI":"10.1109\/MM.2007.39","volume":"2","author":"J Wawrzynek","year":"2007","unstructured":"Wawrzynek J, Patterson D, Oskin M, Lu SL, Kozyrakis C, Hoe JC, Chiou D, Asanovi\u0107 K (2007) Ramp: research accelerator for multiple processors. IEEE Micro 2:46\u201357","journal-title":"IEEE Micro"},{"key":"9214_CR43","unstructured":"Weichslgartner A, Heisswolf J, Zaib A, Wild T, Herkersdorf A, Becker J, Teich J (2015) Position paper: towards hardware-assisted decentralized mapping of applications for heterogeneous NOC architectures. In: ARCS 2015-The 28th international conference on proceedings of architecture of computing systems, VDE, pp 1\u20134"},{"issue":"PARSA\u2013ARTICLE\u20132","key":"9214_CR44","first-page":"19","volume":"26","author":"TF Wenisch","year":"2006","unstructured":"Wenisch TF, Wunderlich RE, Ferdman M, Ailamaki A, Falsafi B, Hoe JC (2006) Simflex: statistical sampling of computer system simulation. IEEE MICRO Spec Issue Comput Arch Simul Model 26(PARSA\u2013ARTICLE\u20132007\u2013001):19\u201331","journal-title":"IEEE MICRO Spec Issue Comput Arch Simul Model"},{"issue":"2\u20133","key":"9214_CR45","doi-asserted-by":"publisher","first-page":"157","DOI":"10.1007\/s10617-006-9589-4","volume":"10","author":"T Wild","year":"2005","unstructured":"Wild T, Herkersdorf A, Lee GY (2005) TAPES\u2014trace-based architecture performance evaluation with systemc. Des Autom Embed Syst 10(2\u20133):157\u2013179","journal-title":"Des Autom Embed Syst"}],"container-title":["Design Automation for Embedded Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10617-018-9214-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10617-018-9214-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10617-018-9214-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T19:24:44Z","timestamp":1565119484000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10617-018-9214-3"}},"subtitle":["Task-accurate simulation of hardware-enhanced run-time management for many-core"],"short-title":[],"issued":{"date-parts":[[2018,8,7]]},"references-count":45,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2018,12]]}},"alternative-id":["9214"],"URL":"https:\/\/doi.org\/10.1007\/s10617-018-9214-3","relation":{},"ISSN":["0929-5585","1572-8080"],"issn-type":[{"type":"print","value":"0929-5585"},{"type":"electronic","value":"1572-8080"}],"subject":[],"published":{"date-parts":[[2018,8,7]]},"assertion":[{"value":"12 December 2016","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"18 July 2018","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"7 August 2018","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}