{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T18:18:19Z","timestamp":1649009899074},"reference-count":18,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2007,5,21]],"date-time":"2007-05-21T00:00:00Z","timestamp":1179705600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Int J Parallel Prog"],"published-print":{"date-parts":[[2008,2]]},"DOI":"10.1007\/s10766-007-0041-6","type":"journal-article","created":{"date-parts":[[2007,5,20]],"date-time":"2007-05-20T15:55:45Z","timestamp":1179676545000},"page":"93-113","source":"Crossref","is-referenced-by-count":0,"title":["Using FORAY Models to Enable MPSoC Memory Optimizations"],"prefix":"10.1007","volume":"36","author":[{"given":"Ilya","family":"Issenin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nikil","family":"Dutt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2007,5,21]]},"reference":[{"key":"41_CR1","doi-asserted-by":"crossref","unstructured":"R. Banakar, S. Steinke, B. Lee, M. Balakrishnan, and P. Marwedel, Scratchpad Memory: Design Alternative for Cache On-chip Memory in Embedded Systems in Proc. of the 10th International Workshop on Hardware\/Software Codesign, Estes Park (Colorado) (2002).","DOI":"10.1145\/774789.774805"},{"key":"41_CR2","unstructured":"E. Brockmeyer, M. Miranda, H. Corporaal, and F. Catthoor, Layer Assignment Techniques for Low Energy in Multi-layered Memory organizations in Proc. of Design, Automation and Test in Europe Conference (2003)."},{"key":"41_CR3","doi-asserted-by":"crossref","unstructured":"D. Burger, and T. M. Austin, The SimpleScalar tool set, version 2.0 in Technical Report 1342, University of Wisconsin-Madison, CS Department (1997).","DOI":"10.1145\/268806.268810"},{"key":"41_CR4","unstructured":"H. Falk and P. Marwedel, Control Flow driven Splitting of Loop Nests at the Source Code Level, in Proceedings of DATE, Munich, Germany (2003)."},{"key":"41_CR5","doi-asserted-by":"crossref","unstructured":"B. Franke, and M. O\u2019Boyle, Compiler Transformation of Pointers to Explicit Array Accesses in DSP Applications in Proc. of International Conference on Compiler Construction (2001).","DOI":"10.1007\/3-540-45306-7_6"},{"key":"41_CR6","unstructured":"M. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown, MiBench: A Free, Commercially Representative Embedded Benchmark Suite in prof. of the 4th Annual Workshop on Workload Characterization (2001)."},{"key":"41_CR7","doi-asserted-by":"crossref","unstructured":"I. Issenin, E. Brockmeyer, B. Durinck, and N. Dutt, Multiprocessor System-on-Chip Data Reuse Analysis for Exploring Customized Memory Hierarchies in Proc. of Design Automation Conference (2006).","DOI":"10.1145\/1146909.1146925"},{"key":"41_CR8","unstructured":"I. Issenin, E. Brockmeyer, M. Miranda, and N. Dutt, Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies in Proc. of Design, Automation and Test in Europe Conference (2004)."},{"key":"41_CR9","unstructured":"I. Issenin, and N. Dutt, FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations in Proceedings of DATE, Munich, Germany (2005)."},{"key":"41_CR10","doi-asserted-by":"crossref","unstructured":"I. Issenin, and N. Dutt, Data Reuse Driven Energy-Aware MPSoC Co-Synthesis of Memory and Communication Architecture for Streaming Applications in Proc. of CODES+ISSS (2006).","DOI":"10.1145\/1176254.1176326"},{"key":"41_CR11","doi-asserted-by":"crossref","unstructured":"M. Kandemir, and A. Choudhary, Compiler-Directed Scratch Pad Memory Hierarchy Design and Management in Proc. of Design Automation Conference (2002).","DOI":"10.1145\/513918.514077"},{"key":"41_CR12","doi-asserted-by":"crossref","unstructured":"M. Kandemir J. Ramanujam, M. J. Irwin, N. Vijaykrishnan I. Kadayif, and A. Parikh, Dynamic Management of Scratch-Pad Memory Space in Proc. of Design Automation Conference (2001).","DOI":"10.1145\/378239.379049"},{"key":"41_CR13","unstructured":"K. Masselos, F. Catthoor, A. Kakarudas, C.E. Goutis, and H. De Man, Memory Hierarchy Layer Assignment for Data re-use Exploitation in Multimedia Algorithms Realized on Predefined Processor Architectures in Proc. of the 8th IEEE International Conference on Electronics, Circuits and Systems (2001)."},{"key":"41_CR14","unstructured":"P. Shivakumar, N. Jouppi, CACTI 3.0: An Integrated Cache Timing, Power, and Area Model. WRL Technical Report 2001\/2 (2001)."},{"key":"41_CR15","unstructured":"S. Steinke, L. Wehmeyer, B. Lee, and P. Marwedel, Assigning Program and Data Objects to Scratchpad for Energy Reduction in Proc. of Design, Automation and Test in Europe Conference (2002)."},{"key":"41_CR16","doi-asserted-by":"crossref","unstructured":"S. Udayakumaran, and R. Barua, Compiler-Decided Dynamic Memory Allocation for Scratch-Pad Based Embedded Systems. In Proc. of International Conference on Compilers, Architecture and Synthesis for Embedded Systems (2003).","DOI":"10.1145\/951710.951747"},{"key":"41_CR17","doi-asserted-by":"crossref","unstructured":"M. Verma, S. Steinke, and P. Marwedel, Data Partitioning for Maximal Scratchpad Usage in Proc. of Asia South Pacific Design Automated Conference (2003).","DOI":"10.1145\/1119772.1119788"},{"key":"41_CR18","doi-asserted-by":"crossref","unstructured":"M.E. Wolf, and M. S. Lam, A Loop Transformation Theory and an Algorithm to Maximize Parallelism, in Proc. of the IEEE Transactions on Parallel and Distributed Systems (1991).","DOI":"10.1109\/71.97902"}],"container-title":["International Journal of Parallel Programming"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10766-007-0041-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10766-007-0041-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10766-007-0041-6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,30]],"date-time":"2019-05-30T23:59:25Z","timestamp":1559260765000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10766-007-0041-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,5,21]]},"references-count":18,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2008,2]]}},"alternative-id":["41"],"URL":"https:\/\/doi.org\/10.1007\/s10766-007-0041-6","relation":{},"ISSN":["0885-7458","1573-7640"],"issn-type":[{"value":"0885-7458","type":"print"},{"value":"1573-7640","type":"electronic"}],"subject":[],"published":{"date-parts":[[2007,5,21]]}}}