{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:16:49Z","timestamp":1758892609107,"version":"3.33.0"},"reference-count":35,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2007,7,10]],"date-time":"2007-07-10T00:00:00Z","timestamp":1184025600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Int J Parallel Prog"],"published-print":{"date-parts":[[2008,8]]},"DOI":"10.1007\/s10766-007-0052-3","type":"journal-article","created":{"date-parts":[[2007,7,16]],"date-time":"2007-07-16T23:09:08Z","timestamp":1184627348000},"page":"361-385","source":"Crossref","is-referenced-by-count":4,"title":["The Impact of Speculative Execution on SMT Processors"],"prefix":"10.1007","volume":"36","author":[{"given":"Dongsoo","family":"Kang","sequence":"first","affiliation":[]},{"given":"Chen","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Jean-Luc","family":"Gaudiot","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2007,7,10]]},"reference":[{"key":"52_CR1","doi-asserted-by":"crossref","unstructured":"Marcuello, P., Gonz\u00e1lez, A.: Exploiting speculative thread-level parallelism on a SMT processor. Proc. Int\u2019l Conference on High Performance Computing and Networking, pp. 754\u2013763 (Apr. 1999)","DOI":"10.1007\/BFb0100636"},{"key":"52_CR2","doi-asserted-by":"crossref","unstructured":"Eggers, S., Emer, J., Levy, H., Lo, J., Stamm, R., Tullsen, D.: Simultaneous multithreading: a platform for next-generation processors. IEEE Micro. 17(5), 12\u201319 (Sept.\/Oct. 1997)","DOI":"10.1109\/40.621209"},{"key":"52_CR3","volume-title":"Computer Architecture: A Quantitative Approach","author":"J. Hennessy","year":"2002","unstructured":"Hennessy J., Patterson D. (2002). Computer Architecture: A Quantitative Approach. 3rd edn. Morgan Kaufmann, San Francisco, CA","edition":"3"},{"key":"52_CR4","unstructured":"Marr, D., Binns, F., Hill, D., Hinton, G., Koufaty, D., Miller, J., Upton, M.: Hyper-threading technology architecture and microarchitecture. Intel Technol. J. 06(01), 4\u201315 (Feb. 2002)"},{"key":"52_CR5","doi-asserted-by":"crossref","unstructured":"Tullsen, D., Eggers, S., Emer, J., Levy, H., Lo, J., Stamm, R.: Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor. Proc. 23rd Annual Int\u2019l Symposium on Computer Architecture, pp. 191\u2013202 (May 1996)","DOI":"10.1145\/232973.232993"},{"key":"52_CR6","volume-title":"Digital Integrated Circuits: A Design Perspective","author":"J. Rabaey","year":"1996","unstructured":"Rabaey J. (1996). Digital Integrated Circuits: A Design Perspective. Prentice Hall, Upper Saddle River, NJ"},{"key":"52_CR7","doi-asserted-by":"crossref","unstructured":"Grunwald, D., Klauser, A., Manne, S., Pleszkun, A.: Confidence estimation for speculation control. Proc. 25th Annual Int\u2019l Symposium on Computer Architecture (1998)","DOI":"10.1109\/ISCA.1998.694768"},{"key":"52_CR8","doi-asserted-by":"crossref","unstructured":"Jacobsen, E., Rotenberg, E., Smith, J.: Assigning confidence to conditional branch predictions. Proc. 29th Annual Int\u2019l Symposium on Microarchitecture, pp. 142\u2013152 (Dec. 1996)","DOI":"10.1109\/MICRO.1996.566457"},{"key":"52_CR9","doi-asserted-by":"crossref","unstructured":"Tullsen, D., Brown, J.: Handling long-latency loads in a simultaneous multithreading processor. Proc. 34th Int\u2019l Symposium on Microarchitecture, pp. 318\u2013327 (Dec. 2001)","DOI":"10.1109\/MICRO.2001.991129"},{"key":"52_CR10","unstructured":"Raasch, S.E., Reinhardt, S.K.: Applications of thread prioritization in SMT processors. Proc. Workshop on Multithreaded Execution and Compilation (Jan. 1999)"},{"key":"52_CR11","doi-asserted-by":"crossref","unstructured":"El-Mousry, A., Albonesi, D.H.: Front-end policies for improved issue efficiency in SMT processors. Proc. 9th Int\u2019l Symposium on High-Performance Computer Architecture, pp. 31\u201340 (Feb. 2003)","DOI":"10.1109\/HPCA.2003.1183522"},{"key":"52_CR12","unstructured":"Cazorla, F.J., Ramirez, A., Valero, M., Fernandez, E.: DCache warn: an I-Fetch policy to increase SMT efficiency. Proc. 18th Int\u2019l Parallel & Distributed Processing Symposium (2004)"},{"key":"52_CR13","doi-asserted-by":"crossref","unstructured":"Liu, C., Gaudiot, J-L.: Static partitioning vs dynamic sharing of resources in simultaneous multithreading microarchitectures. Proc. 6th Int\u2019l Workshop on Advanced Parallel Processing Technologies (Oct. 2005)","DOI":"10.1007\/11573937_11"},{"key":"52_CR14","doi-asserted-by":"crossref","unstructured":"Raasch, S., Reinhardt, S.: The impact of resource partitioning on SMT processors. Proc. 12th Int\u2019l Conference on Parallel Architectures and Compilation Techniques, pp. 15\u201325 (2003)","DOI":"10.1109\/PACT.2003.1237998"},{"key":"52_CR15","doi-asserted-by":"crossref","unstructured":"Cazorla, F.J., Ramirez, A., Valero, M., Fernandez, E.: Dynamically controlled resource allocation in SMT processors. Proc. 37th Int\u2019l Symposium on Micoarchitecture, pp. 171\u2013182 (Dec. 2004)","DOI":"10.1109\/MICRO.2004.17"},{"key":"52_CR16","doi-asserted-by":"crossref","unstructured":"Choi, S., Yeung, D.: Learning-based SMT processor resource distribution via hill-climbing. Proc. 33rd Int\u2019l Symposium on Computer Architecture, pp. 239\u2013251 (2006)","DOI":"10.1145\/1150019.1136507"},{"key":"52_CR17","doi-asserted-by":"crossref","unstructured":"Arag\u00f3n, J., Gonz\u00e1lez, J., Garc\u00eda, J., Gonz\u00e1lez, A.: Confidence estimation for branch prediction reversal. Proc. 8th Int\u2019l Conference on High Performance Computing, pp. 214\u2013223 (Dec. 2001)","DOI":"10.1007\/3-540-45307-5_19"},{"key":"52_CR18","unstructured":"Burtscher, M., Zorn, B.: Prediction outcome history-based confidence estimation for load value prediction. J. Instruction-Level Parallelism 1 (May 1999)"},{"key":"52_CR19","unstructured":"Heil, T., Smith, J.: Selective dual path execution. Univ. of Wisconsin \u2013 Madison, Technical Report (Nov. 1996)."},{"key":"52_CR20","doi-asserted-by":"crossref","unstructured":"Luo, K., Franklin, M., Mukherjee, S., S\u00e9znec, A.: Boosting SMT performance by speculation control. Proc. 15th Int\u2019l Parallel and Distributed Processing Symposium (2001)","DOI":"10.1109\/IPDPS.2001.924929"},{"key":"52_CR21","doi-asserted-by":"crossref","unstructured":"Manne, S., Klauser, A., Grunwald, D.: Pipeline gating: speculation control for energy reduction. Proc. 25th Annual Int\u2019l Symposium on Computer Architecture, pp. 132\u2013141, (1998)","DOI":"10.1145\/279361.279377"},{"key":"52_CR22","doi-asserted-by":"crossref","unstructured":"Wall, D.: Limits of instruction-level parallelism. Proc. 4th Int\u2019l Conf. on Architectural Support for Programming Languages and Operating System, pp.176\u2013189 (1991)","DOI":"10.1145\/106972.106991"},{"key":"52_CR23","doi-asserted-by":"crossref","unstructured":"Gon\u00e7alves, R., Pilla, M., Pizzol, G., Santos, T., Santos, R., Navaux, P.: Evaluating the effects of branch prediction accuracy on the performance of SMT architectures. Euromicro Workshop on Parallel and Distributed Processing, pp. 355\u2013362 (Feb. 2001)","DOI":"10.1109\/EMPDP.2001.905062"},{"key":"52_CR24","doi-asserted-by":"crossref","unstructured":"Yeh, T., Patt, Y.: Alternative implementations of two-level adaptive branch prediction. Proc. 19th Annual Int\u2019l Symposium on Computer Architecture, pp. 124\u2013134, (May 1992)","DOI":"10.1145\/146628.139709"},{"key":"52_CR25","doi-asserted-by":"crossref","unstructured":"Knijnenburg, P., Ramirez, A., Latorre, F., Larrriba, J., Valero, M.: Branch classification to control instruction fetch in simultaneous multithreaded architectures. Proc. Int\u2019l Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, pp. 67\u201376 (Aug. 2002)","DOI":"10.1109\/IWIA.2002.1035020"},{"key":"52_CR26","doi-asserted-by":"crossref","unstructured":"Seng, J.S., Tullsen, D.M., Cai, G.Z.N.: Power-sensitive multithreaded architecture. Proc. Int\u2019l Conference on Computer Design, pp. 199\u2013206 (Sep. 2000)","DOI":"10.1109\/ICCD.2000.878286"},{"issue":"3","key":"52_CR27","doi-asserted-by":"crossref","first-page":"314","DOI":"10.1145\/859716.859720","volume":"21","author":"S. Swanson","year":"2003","unstructured":"Swanson S., McDowell L., Swift M., Eggers S., Levy H. (Aug. 2003). An evaluation of speculative instruction execution on simultaneous multithreaded processors. ACM Trans. Comput. Syst. 21(3): 314\u2013340","journal-title":"ACM Trans. Comput. Syst."},{"key":"52_CR28","doi-asserted-by":"crossref","unstructured":"Hilly, S., S\u00e9znec, A.: Branch prediction and simultaneous multithreading. 5th Proc. Int\u2019l Conference on Parallel Architectures and Compilation Techniques, pp. 169\u2013173 (1996)","DOI":"10.1109\/PACT.1996.552664"},{"key":"52_CR29","doi-asserted-by":"crossref","unstructured":"Burger, D., Austin, T.: The SimpleScalar Tool Set, Version 2.0. Univ. of Wisconsin-Madison Computer Science Department Technical Report #1342 (June 1997)","DOI":"10.1145\/268806.268810"},{"issue":"3","key":"52_CR30","doi-asserted-by":"crossref","first-page":"349","DOI":"10.1109\/12.48865","volume":"39","author":"G. Sohi","year":"1990","unstructured":"Sohi G. (Mar. 1990). Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers. IEEE Trans. Comput. 39(3): 349\u2013359","journal-title":"IEEE Trans. Comput."},{"key":"52_CR31","unstructured":"McFarling, S.: Combining branch predictors. WRL Technical Note TN-36 (Jun. 1993)"},{"key":"52_CR32","doi-asserted-by":"crossref","unstructured":"Henning, J.: SPEC CPU2000: measuring CPU performance in the new millennium. IEEE Compu. pp. 28\u201335 (July 2000)","DOI":"10.1109\/2.869367"},{"key":"52_CR33","doi-asserted-by":"crossref","unstructured":"KleinOsowski, A., Lilja, D.: MinneSPEC: A new SPEC benchmark workload for simulation-based computer architecture research. Computer Architecture Letters (June 2002)","DOI":"10.1109\/L-CA.2002.8"},{"key":"52_CR34","doi-asserted-by":"crossref","unstructured":"Sazeides, Y., Juan, T.: How to compare the performance of two SMT microarchitectures. Proc. Int\u2019l Symposium on Performance Analysis of Systems and Software, pp. 180\u2013183 (Nov. 2001)","DOI":"10.1109\/ISPASS.2001.990697"},{"issue":"4","key":"52_CR35","doi-asserted-by":"crossref","first-page":"18","DOI":"10.1145\/1186736.1186738","volume":"34","author":"D. Citron","year":"2006","unstructured":"Citron D., Hurani A., Gnadrey A. (Sep. 2006). The harmonic or geometric mean: does it really matter?. Comput. Architect. News 34(4): 18\u201325","journal-title":"Comput. Architect. News"}],"container-title":["International Journal of Parallel Programming"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10766-007-0052-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10766-007-0052-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10766-007-0052-3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,19]],"date-time":"2025-01-19T14:02:25Z","timestamp":1737295345000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10766-007-0052-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,7,10]]},"references-count":35,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2008,8]]}},"alternative-id":["52"],"URL":"https:\/\/doi.org\/10.1007\/s10766-007-0052-3","relation":{},"ISSN":["0885-7458","1573-7640"],"issn-type":[{"type":"print","value":"0885-7458"},{"type":"electronic","value":"1573-7640"}],"subject":[],"published":{"date-parts":[[2007,7,10]]}}}