{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,27]],"date-time":"2025-01-27T05:16:58Z","timestamp":1737955018744,"version":"3.33.0"},"reference-count":19,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2008,1,24]],"date-time":"2008-01-24T00:00:00Z","timestamp":1201132800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Int J Parallel Prog"],"published-print":{"date-parts":[[2008,4]]},"DOI":"10.1007\/s10766-007-0064-z","type":"journal-article","created":{"date-parts":[[2008,1,23]],"date-time":"2008-01-23T20:59:24Z","timestamp":1201121964000},"page":"166-183","source":"Crossref","is-referenced-by-count":1,"title":["Dual-thread Speculation: A Simple Approach to Uncover Thread-level Parallelism on a Simultaneous Multithreaded Processor"],"prefix":"10.1007","volume":"36","author":[{"given":"Fredrik","family":"Warg","sequence":"first","affiliation":[]},{"given":"Per","family":"Stenstrom","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2008,1,24]]},"reference":[{"issue":"2","key":"64_CR1","doi-asserted-by":"crossref","first-page":"40","DOI":"10.1109\/MM.2004.1289290","volume":"24","author":"J. Kalla","year":"2004","unstructured":"Kalla, J., Sinharoy, B., Tendler, J.: IBM power5 chip: a dual-core multithreaded processor. IEEE Micro. 24(2), 40\u201347 (2004)","journal-title":"IEEE Micro."},{"issue":"2","key":"64_CR2","doi-asserted-by":"crossref","first-page":"21","DOI":"10.1109\/MM.2005.35","volume":"25","author":"P. Kongetira","year":"2005","unstructured":"Kongetira, P., Aingaran, K., Olukotun, K.: Niagara: a 32-way multithreaded sparc processor. IEEE Micro. 25(2), 21\u201329 (2005)","journal-title":"IEEE Micro."},{"key":"64_CR3","doi-asserted-by":"crossref","unstructured":"Tullsen, D., Eggers, S., Levy, H.: Simultaneous multithreading: maximizing on-chip parallelism. In: Proceedings of the 22th Annual International Symposium on Computer Architecture (ISCA \u201995), pp. 392\u2013403. ACM Press (1995)","DOI":"10.1145\/223982.224449"},{"key":"64_CR4","doi-asserted-by":"crossref","unstructured":"Codrescu, L., Wills, D.S.: Architecture of the atlas chip-multiprocessor: dynamically parallelizing irregular applications. In: Proceedings of the 1999 International Conference on Computer Design (ICCD \u201999), pp. 428\u2013435. IEEE Computer Society (October 1999)","DOI":"10.1109\/ICCD.1999.808577"},{"key":"64_CR5","doi-asserted-by":"crossref","unstructured":"Hammond, L., Willey, M., Olukotun, K.: Data speculation support for a chip multiprocessor. In: Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII \u201998), pp. 58\u201369. ACM Press (October 1998)","DOI":"10.1145\/291069.291020"},{"issue":"9","key":"64_CR6","doi-asserted-by":"crossref","first-page":"866","DOI":"10.1109\/12.795218","volume":"48","author":"V. Krishnan","year":"1999","unstructured":"Krishnan, V., Torrellas, J.: A chip-multiprocessor architecture with speculative multithreading. IEEE Trans. Comput. 48(9), 866\u2013880 (1999)","journal-title":"IEEE Trans. Comput."},{"key":"64_CR7","doi-asserted-by":"crossref","unstructured":"Ohsawa,T., Takagi, M., Kawahara, S., Matsushita, S.: Pinot: speculative multi-threading processor architecture exploiting parallelism over a wide range of granularities. In: Proceedings of the 38th annual IEEE\/ACM International Symposium on Microarchitecture (MICRO \u201905), pp. 81\u201392, Washington, DC, USA, 2005. IEEE Computer Society","DOI":"10.1109\/MICRO.2005.26"},{"key":"64_CR8","doi-asserted-by":"crossref","unstructured":"Sohi, G.S., Breach, S.E., Vijaykumar, T.N.: Multiscalar processors. In: Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA \u201995), pp. 414\u2013425. ACM Press (June 1995)","DOI":"10.1145\/223982.224451"},{"key":"64_CR9","doi-asserted-by":"crossref","unstructured":"Steffan, J.G., Mowry, T.C.: The potential for using thread-level data speculation to facilitate automatic parallelization. In: Proceedings of the Fourth International Symposium on High-Performance Computer Architecture (HPCA \u201998), pp. 2\u201313. IEEE Computer Society (February 1998)","DOI":"10.1109\/HPCA.1998.650541"},{"key":"64_CR10","doi-asserted-by":"crossref","unstructured":"Renau, J., Strauss, K., Ceze, L., Liu, W., Sarangi, S., Tuck, J., Torrellas, J.: Thread-level speculation on a cmp can be energy efficient. In: Proceedings of the International Conference on Supercomputing (ICS \u201905). ACM (June 2005)","DOI":"10.1145\/1088149.1088178"},{"key":"64_CR11","doi-asserted-by":"crossref","unstructured":"Akkary, H., Driscoll, M.A.: A dynamic multithreading processor. In: Proceedings of the 31st Annual International Symposium on Microarchitecture (MICRO \u201998), pp. 226\u2013236. IEEE Computer Society (December 1998)","DOI":"10.1109\/MICRO.1998.742784"},{"key":"64_CR12","doi-asserted-by":"crossref","unstructured":"Park, I., Vijaykumar, T.N.: Implicitly-multithreaded processors. In: Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA \u201903), pp. 39\u201350. IEEE Computer Society (June 2003)","DOI":"10.1145\/859618.859624"},{"key":"64_CR13","doi-asserted-by":"crossref","unstructured":"Marcuello, P., Gonz\u00e1lez, A.: Exploiting speculative thread-level parallelism on a SMT processor. In: Proceedings of the International Conference on High Performance Computing and Networking (HPCN \u201999), pp. 754\u2013763 (April 1999)","DOI":"10.1007\/BFb0100636"},{"key":"64_CR14","doi-asserted-by":"crossref","unstructured":"Gopal, S., Vijaykumar,T., Smith, J., Sohi, G.: Speculative versioning cache. In: Proceedings of the Fourth International Symposium on High-Performance Computer Architecture (HPCA \u201998), pp. 195\u2013206. IEEE Computer Society (February 1998)","DOI":"10.1109\/HPCA.1998.650559"},{"key":"64_CR15","doi-asserted-by":"crossref","unstructured":"Renau, J., Tuck, J., Liu, W., Ceze, L., Strauss, K., Torrellas, J.: Tasking with out-of-order spawn in tls chip multiprocessors: microarchitecture and compilation. In: Proceedings of the International Conference on Supercomputing (ICS \u201905). ACM (June 2005)","DOI":"10.1145\/1088149.1088173"},{"key":"64_CR16","doi-asserted-by":"crossref","unstructured":"Magnusson, P.S., Christensson, M., Eskilson, J., Forsgren, D., H\u00e5llberg, G., H\u00f6gberg, J., Larsson, F., Moestedt, A., Werner, B.: Simics: a full system simulation plattform. IEEE Computer, pp. 50\u201358 (February 2002)","DOI":"10.1109\/2.982916"},{"key":"64_CR17","doi-asserted-by":"crossref","unstructured":"Warg, F., Stenstrom, P.: Improving speculative thread-level parallelism through module run-length prediction. In: Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS \u201903). IEEE Computer Society (April 2003)","DOI":"10.1109\/IPDPS.2003.1213089"},{"key":"64_CR18","doi-asserted-by":"crossref","unstructured":"Wallace, S., Calder, B., Tullsen D.: Threaded multiple path execution. In Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA \u201998), pp. 238\u2013249. ACM Press (June 1998)","DOI":"10.1109\/ISCA.1998.694778"},{"key":"64_CR19","doi-asserted-by":"crossref","unstructured":"\u00d6zer, E., Conte, T.M., Sharma S.: Weld: a multithreading technique towards latency-tolerant VLIW processors. In: Proceedings of the 8th International Conference on High Performance Computing (HiPC \u201901), pp. 192\u2013203. Springer (Dec 2001)","DOI":"10.1007\/3-540-45307-5_17"}],"container-title":["International Journal of Parallel Programming"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10766-007-0064-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10766-007-0064-z\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10766-007-0064-z","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,26]],"date-time":"2025-01-26T06:00:22Z","timestamp":1737871222000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10766-007-0064-z"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,1,24]]},"references-count":19,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2008,4]]}},"alternative-id":["64"],"URL":"https:\/\/doi.org\/10.1007\/s10766-007-0064-z","relation":{},"ISSN":["0885-7458","1573-7640"],"issn-type":[{"type":"print","value":"0885-7458"},{"type":"electronic","value":"1573-7640"}],"subject":[],"published":{"date-parts":[[2008,1,24]]}}}