{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,5,6]],"date-time":"2022-05-06T08:52:36Z","timestamp":1651827156020},"reference-count":26,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2008,4,24]],"date-time":"2008-04-24T00:00:00Z","timestamp":1208995200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Int J Parallel Prog"],"published-print":{"date-parts":[[2008,6]]},"DOI":"10.1007\/s10766-008-0075-4","type":"journal-article","created":{"date-parts":[[2008,4,23]],"date-time":"2008-04-23T14:58:58Z","timestamp":1208962738000},"page":"347-360","source":"Crossref","is-referenced-by-count":4,"title":["Performance Advantage of Reconfigurable Cache Design on Multicore Processor Systems"],"prefix":"10.1007","volume":"36","author":[{"given":"Jie","family":"Tao","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marcel","family":"Kunze","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fabian","family":"Nowak","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rainer","family":"Buchty","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wolfgang","family":"Karl","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2008,4,24]]},"reference":[{"key":"75_CR1","unstructured":"Chandra, R. et al.: Parallel Programming in OpenMP. Number 978-1-55860-671-5 in ISBN. Morgan Kaufmann (2000)"},{"key":"75_CR2","unstructured":"Pacheco, P.: Parallel Programming with MPI. Number 978-1-55860-339-4 in ISBN. Morgan Kaufmann (1996)"},{"key":"75_CR3","doi-asserted-by":"crossref","unstructured":"Fung, S.: Improving Cache Locality for Thread-Level Speculation. Master\u2019s thesis, University of Toronto (2005)","DOI":"10.1109\/IPDPS.2006.1639271"},{"key":"75_CR4","doi-asserted-by":"crossref","unstructured":"Wang, Z., Sha, E., Hu, X.: Combined partitioning and data padding for scheduling multiple loop nests. In: Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp. 67\u201375 (2001)","DOI":"10.1145\/502217.502228"},{"issue":"11","key":"75_CR5","doi-asserted-by":"crossref","first-page":"228","DOI":"10.1145\/291006.291051","volume":"33","author":"G. Somnath","year":"1998","unstructured":"Somnath G., Margaret M. and Sharad M. (1998). Precise miss analysis for program transformations with caches of arbitrary associativity. ACM SIG-PLAN Notices 33(11): 228\u2013239","journal-title":"ACM SIG-PLAN Notices"},{"key":"75_CR6","unstructured":"Liu, C., Sivasubramaniam, A., Kandemir, M.: Organizing the last line of defense before hitting the memory wall for CMPs. In: Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA\u201904), pp. 176\u2013185, Madrid, Spain, February 2004"},{"key":"75_CR7","doi-asserted-by":"crossref","unstructured":"Molnos, A.M., Cotofana, S.D., Heijligers, M.J.M., van Eijndhoven, J.T.J.: Static cache partitioning robustness analysis for embedded on-chip multi-processors. In: Proceedings of the 3rd Conference on Computing Frontiers (CF\u201906), pp. 353\u2013360, Ischia, Italy, May 2006","DOI":"10.1145\/1128022.1128069"},{"key":"75_CR8","doi-asserted-by":"crossref","unstructured":"Benitez, D., Moure, J.C., Rexachs, D.I., Luque, E.: Evaluation of the field-programmable cache: performance and energy consumption. In: Proceedings of the 3rd Conference on Computing frontiers (CF\u201906), pp. 361\u2013372, Ischia, Italy, May 2006","DOI":"10.1145\/1128022.1128070"},{"key":"75_CR9","doi-asserted-by":"crossref","unstructured":"Carvalho, M.B., Goes, L., Martins, C.: Dynamically reconfigurable cache architecture using adaptive block allocation policy. In: Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS), April 2006","DOI":"10.1109\/IPDPS.2006.1639487"},{"key":"75_CR10","doi-asserted-by":"crossref","unstructured":"Gibson, J., Kunz, R., Ofelt, D., Horowitz, M., Hennessy, J., Heinrich, M.: FLASH vs. (simulated) FLASH: closing the simulation loop. In: Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 49\u201358, November 2000","DOI":"10.1145\/378993.379000"},{"key":"75_CR11","unstructured":"Herrod, S.A.: Using Complete Machine Simulation to Understand Computer System Behavior. Ph.D. thesis, Stanford University, February 1998"},{"key":"75_CR12","doi-asserted-by":"crossref","unstructured":"Magnusson, P.S., Werner, B.: Efficient Memory Simulation in SimICS. In: Proceedings of the 8th Annual Simulation Symposium. Phoenix, Arizona, USA, April 1995","DOI":"10.1109\/SIMSYM.1995.393593"},{"issue":"2","key":"75_CR13","doi-asserted-by":"crossref","first-page":"59","DOI":"10.1109\/2.982917","volume":"35","author":"T. Austin","year":"2002","unstructured":"Austin T., Larson E. and Ernst D. (2002). SimpleScalar: an infrastructure for computer system modeling. Computer 35(2): 59\u201367","journal-title":"Computer"},{"key":"75_CR14","unstructured":"Curtis-Maury, M., Ding, X., Antonopoulos, C., Nikolopoulos, D.: An evaluation of OpenMP on current and emerging multithreaded\/multicore processors. In: Proceedings of the First International Workshop on OpenMP (IWOMP), Eugene, Oregon USA, June 2005"},{"key":"75_CR15","unstructured":"WWW.Cachegrind: a Cache-miss Profiler. Available at http:\/\/developer.kde.org\/sewardj\/docs-2.2.0\/cg_main.html#cg-top"},{"key":"75_CR16","unstructured":"Nethercote, N., Seward, J.: Valgrind: a program supervision framework. In: Proceedings of the Third Workshop on Runtime Verification (RV\u201903), Boulder, Colorado, USA, July 2003. Available at http:\/\/developer.kde.org\/sewardj"},{"issue":"4","key":"75_CR17","doi-asserted-by":"crossref","first-page":"32","DOI":"10.1109\/2.375175","volume":"28","author":"M. Martonosi","year":"1995","unstructured":"Martonosi M., Gupta A. and Anderson T. (1995). Tuning memory performance of sequential and parallel programs. Computer 28(4): 32\u201340","journal-title":"Computer"},{"key":"75_CR18","doi-asserted-by":"crossref","unstructured":"Benitez, D., Moure, J.C., Rexachs, D.I., Luque, E.: Evaluation of the field-programmable cache: performance and energy consumption. In: CF \u201906: Proceedings of the 3rd Conference on Computing Frontiers, pp. 361\u2013372 (2006)","DOI":"10.1145\/1128022.1128070"},{"key":"75_CR19","doi-asserted-by":"crossref","unstructured":"Gordon-Ross, A., Vahid, F., Dutt, N.: Fast configurable-cache tuning with a unified second-level cache. In: ISLPED \u201905: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, pp. 323\u2013326 (2005)","DOI":"10.1145\/1077603.1077681"},{"issue":"1","key":"75_CR20","doi-asserted-by":"crossref","first-page":"55","DOI":"10.1145\/1061267.1061271","volume":"2","author":"J. Abella","year":"2005","unstructured":"Abella J., Gonz\u00e1lez A., Vera X. and O\u2019Boyle M. (2005). IATAC: a smart predictor to turn-off L2 cache lines. ACM Trans Arch Code Optim 2(1): 55\u201377","journal-title":"ACM Trans Arch Code Optim"},{"key":"75_CR21","doi-asserted-by":"crossref","unstructured":"Ishihara, T., Fallah, F.: A non-uniform cache architecture for low power system design. In: ISLPED \u201905: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, pp. 363\u2013368 (2005)","DOI":"10.1145\/1077603.1077690"},{"key":"75_CR22","doi-asserted-by":"crossref","unstructured":"Saito, H. et al.: Large system performance of SPEC OMP2001 benchmarks. In Zima, H.P., Joe, K., Sato, M., Seo, Y., Shimasaki, M. (eds.) High performance computing: 4th International Symposium, ISHPC 2002. Proceedings, Volume 2327 of Lecture Notes in Computer Science, pp. 370\u2013379, May 2002","DOI":"10.1007\/3-540-47847-7_34"},{"key":"75_CR23","unstructured":"Bailey, D. et al.: The NAS Parallel Benchmarks. Technical Report RNR-94-007, Department of Mathematics and Computer Science, Emory University, March 1994"},{"key":"75_CR24","unstructured":"Jin, H., Frumkin, M., Yan, J.: The OpenMP Implementation of NAS Parallel Benchmarks and Its Performance. Technical Report NAS-99-011, NASA Ames Research Center, October 1999"},{"key":"75_CR25","unstructured":"Nowak, F., Buchty, R., Karl, W.: Adaptive cache infrastructure: supporting dynamic program changes following dynamic program behavior. In: Proceedings of the 9th Workshop on Parallel Systems and Algorithms (PASA 2008), Dresden, Germany, February 2008"},{"key":"75_CR26","unstructured":"Buchty, R., Nowak, F., Karl, W.: A Run-time Reconfigurable Cache Architecture. In: Proceedings of the International Conference ParCo 2007, Volume 15 of Advances in Parallel Computing, ISBN 978-3-9810843-4-4, pp. 757\u2013766. IOS Press, Juelich, Germany, September 2007"}],"container-title":["International Journal of Parallel Programming"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10766-008-0075-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10766-008-0075-4\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10766-008-0075-4","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,30]],"date-time":"2019-05-30T23:59:25Z","timestamp":1559260765000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10766-008-0075-4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,4,24]]},"references-count":26,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2008,6]]}},"alternative-id":["75"],"URL":"https:\/\/doi.org\/10.1007\/s10766-008-0075-4","relation":{},"ISSN":["0885-7458","1573-7640"],"issn-type":[{"value":"0885-7458","type":"print"},{"value":"1573-7640","type":"electronic"}],"subject":[],"published":{"date-parts":[[2008,4,24]]}}}