{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T05:16:29Z","timestamp":1649135789008},"reference-count":27,"publisher":"Springer Science and Business Media LLC","issue":"5","license":[{"start":{"date-parts":[[2012,5,10]],"date-time":"2012-05-10T00:00:00Z","timestamp":1336608000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Int J Parallel Prog"],"published-print":{"date-parts":[[2012,10]]},"DOI":"10.1007\/s10766-012-0196-7","type":"journal-article","created":{"date-parts":[[2012,5,9]],"date-time":"2012-05-09T11:13:33Z","timestamp":1336562013000},"page":"488-513","source":"Crossref","is-referenced-by-count":0,"title":["Combining Height Reduction and Scheduling for VLIW Machines Enhanced with Three-Argument Arithmetic Operations"],"prefix":"10.1007","volume":"40","author":[{"given":"Fadi","family":"Abboud","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yosi","family":"Ben-Asher","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yousef","family":"Shajrawi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Esti","family":"Stein","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2012,5,10]]},"reference":[{"key":"196_CR1","unstructured":"Arm instruction set, arm7tdmi data sheet. Technical report(2009)"},{"key":"196_CR2","doi-asserted-by":"crossref","unstructured":"Ben Asher, Y., Stein, E.: Extending booth algorithm to multiplications of three numbers on the fpga. In: IEEE International Conference on Field-Programmable Technology, Taiwan (2008)","DOI":"10.1109\/FPT.2008.4762411"},{"key":"196_CR3","unstructured":"Cortadella, J.: Bi-decomposition and tree-height reduction for timing optimization. In: IEEE\/ACM International Workshop on Logic and Synthesis (2002)"},{"issue":"12","key":"196_CR4","doi-asserted-by":"crossref","first-page":"1480","DOI":"10.1006\/jpdc.2000.1661","volume":"60","author":"A.F. De Souza","year":"2000","unstructured":"De Souza A.F., Rounce P.: Dynamically scheduling VLIW instructions. J. Parallel Distrib. Comput. 60(12), 1480\u20131511 (2000)","journal-title":"J. Parallel Distrib. Comput."},{"key":"196_CR5","unstructured":"Freescale Semiconductor, Inc., SC140 DSP Core Reference Manual (2005)"},{"issue":"4","key":"196_CR6","doi-asserted-by":"crossref","first-page":"687","DOI":"10.1137\/0217044","volume":"17","author":"G.L. Miller","year":"1988","unstructured":"Miller G.L., Ramachandran V., Kaltofen E.: Efficient parallel evaluation of straight-line code and arithmetic circuits. SIAM J. Comput. 17(4), 687\u2013695 (1988)","journal-title":"SIAM J. Comput."},{"key":"196_CR7","doi-asserted-by":"crossref","unstructured":"Ghuloum, A.M., Fisher, A.L.: Parallelizing complex scans and reductions, pp. 135\u2013146 (1994)","DOI":"10.1145\/773473.178255"},{"key":"196_CR8","unstructured":"Haney, R., Meuse, T., Kepner, J., Lebak, J.: Hpec challenge overview. In: Ninth Anuual High-Performance Embedded Computing Workshop (2005)"},{"key":"196_CR9","unstructured":"Intel 64 and ia-32 architectures, software developers manual, instruction set reference. Technical report, Intel (2011)"},{"key":"196_CR10","volume-title":"An Introduction to Parallel Algorithms","author":"J. Jaja","year":"1992","unstructured":"Jaja J.: An Introduction to Parallel Algorithms. Addison-Wesley, Boston (1992)"},{"key":"196_CR11","doi-asserted-by":"crossref","unstructured":"Lattner, C., Adve, V. LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation. In: Proceedings of the 2004 International Symposium on Code Generation and Optimization (CGO\u201904), Palo Alto, California (2004)","DOI":"10.1109\/CGO.2004.1281665"},{"key":"196_CR12","unstructured":"Lee, C., Lee, J.K., Hwang, T.T., Tsai, S.C.: Compiler optimization on instruction scheduling for low power. In: International Symposium on System Synthesis (ISSS), p 55, IEEE Computer Society (2000)"},{"key":"196_CR13","unstructured":"Mangalam, G.N., Narayan, S., van Besouw, P., Avra, L., Mathur, A., Saluja, S.: Graph transformations for improved tree height reduction. In: VLSID \u201903: Proceedings of the 16th International Conference on VLSI Design (2003)"},{"key":"196_CR14","unstructured":"McMahon, F.H.: The livermore Fortran Kernels Test of the Numerical Performance Range. Performance Evaluation of Supercomputers. Elsevier, New York, pp. 143\u2013186 (1988)"},{"key":"196_CR15","volume-title":"Advanced Compiler Design and Implementation","author":"S. Muchnick","year":"1997","unstructured":"Muchnick S.: Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers, Waltham (1997)"},{"key":"196_CR16","doi-asserted-by":"crossref","unstructured":"Nakatani, T., Ebcioglu, K.: Combining as a compilation technique for vliw architectures. In: Proceedings of MICRO-22, pp. 43\u201355 (1989)","DOI":"10.1145\/75395.75401"},{"key":"196_CR17","doi-asserted-by":"crossref","unstructured":"Nicolau, A., Potasmann, R.: Incremental tree height reduction for high level synthesis. In: DAC \u201991: Proceedings of the 28th conference on ACM\/IEEE design automation, pp. 770\u2013774 (1991)","DOI":"10.1145\/127601.127767"},{"key":"196_CR18","volume-title":"Synthesis of Parallel Algorithms","author":"J. Reif","year":"1993","unstructured":"Reif J.: Synthesis of Parallel Algorithms. Morgan Kaufmann, Waltham (1993)"},{"key":"196_CR19","doi-asserted-by":"crossref","first-page":"133","DOI":"10.1016\/0304-3975(95)00252-9","volume":"162","author":"N. Revol","year":"1996","unstructured":"Revol N., Roch J.: Parallel evaluation of arithmetic circuits. Theor. Comput. Sci. 162, 133\u2013150 (1996)","journal-title":"Theor. Comput. Sci."},{"issue":"21","key":"196_CR20","first-page":"3465","volume":"14","author":"R. Santos","year":"2008","unstructured":"Santos R., Azevedo R., Araujo G.: Instruction scheduling based on subgraph isomorphism for a high performance computer processor. J. Univers. Comput. Sci. 14(21), 3465\u20133480 (2008)","journal-title":"J. Univers. Comput. Sci."},{"key":"196_CR21","doi-asserted-by":"crossref","unstructured":"Schlansker, M., Kathail, V., Anik, S.: Height reduction of control recurrences for ilp processors. In: MICRO 27: Proceedings of the 27th Annual International Symposium on Microarchitecture (1994)","DOI":"10.1145\/192724.192729"},{"key":"196_CR22","unstructured":"Sethi, R., Aho, A.V., Lam, M.S., Ullman, J.D.: Compilers: Principles, Techniques, and Tools. Addison-Wesley, Boston, 1986 (2006)"},{"issue":"4","key":"196_CR23","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1498690.1498694","volume":"5","author":"G. Shobaki","year":"2009","unstructured":"Shobaki G., Wilken K., Heffernan M.: Optimal trace scheduling using enumeration. ACM Trans. Architect. Code Optim. (TACO) 5(4), 1\u201332 (2009)","journal-title":"ACM Trans. Architect. Code Optim. (TACO)"},{"key":"196_CR24","unstructured":"Steven, F.L., Potter, R.D., Steven, G.B., Vintan, L., Romania, S.: Static data dependence collapsing in a high performance superscalar architecture. In: The 3-rd International Conference on Massively Parallel Computing Systems (MPCS \u201998) (1998)"},{"key":"196_CR25","doi-asserted-by":"crossref","unstructured":"Stpiczynski, P.: Parallel algorithms for solving linear recurrence systems. Parallel Processing: CONPAR 92-VAPP V. In: Second Joint International Conference on Vector and Parallel Processing, pp. 343\u2013348 (1992)","DOI":"10.1007\/3-540-55895-0_428"},{"key":"196_CR26","unstructured":"Texas Instruments, Inc., TMS320C67x\/C67x CPU and Instruction Set Reference Guide (2006)"},{"key":"196_CR27","unstructured":"Zory, J., Coelho, F.: Using algebraic transformations to optimize expression evaluation in scientific code. In: PACT \u201998: Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques (1998)"}],"container-title":["International Journal of Parallel Programming"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10766-012-0196-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10766-012-0196-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10766-012-0196-7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,28]],"date-time":"2019-06-28T12:30:15Z","timestamp":1561725015000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10766-012-0196-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,5,10]]},"references-count":27,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2012,10]]}},"alternative-id":["196"],"URL":"https:\/\/doi.org\/10.1007\/s10766-012-0196-7","relation":{},"ISSN":["0885-7458","1573-7640"],"issn-type":[{"value":"0885-7458","type":"print"},{"value":"1573-7640","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,5,10]]}}}