{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T07:26:59Z","timestamp":1649057219769},"reference-count":26,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2013,10,25]],"date-time":"2013-10-25T00:00:00Z","timestamp":1382659200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Int J Parallel Prog"],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1007\/s10766-013-0291-4","type":"journal-article","created":{"date-parts":[[2013,10,24]],"date-time":"2013-10-24T05:22:16Z","timestamp":1382592136000},"page":"59-85","source":"Crossref","is-referenced-by-count":3,"title":["Revisiting Cache Resizing"],"prefix":"10.1007","volume":"43","author":[{"given":"Georgios","family":"Keramidas","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chrysovalantis","family":"Datsios","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2013,10,25]]},"reference":[{"key":"291_CR1","unstructured":"Abella, J., Gonzalez, A., Vera, X., O\u2019Boyle, M.F.P.: IATAC: a smart predictor to turn-off L2 cache lines. ACM Trans. Archit. Code Optim. 2, 55\u201377 (2005)"},{"key":"291_CR2","doi-asserted-by":"crossref","unstructured":"Albonesi, D.H.: Selective cache ways: on-demand cache resource allocation. In: Proceedings of the International Symposium on Microarchitecture (1999)","DOI":"10.1109\/MICRO.1999.809463"},{"key":"291_CR3","doi-asserted-by":"crossref","unstructured":"Balasubramonian, R., Albonesi, D.H., Buyuktosunoglu, A., Dwarkadas, S.: Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. In: Proceedings of the International Symposium on Computer Architecture (2000)","DOI":"10.1109\/MICRO.2000.898075"},{"key":"291_CR4","doi-asserted-by":"crossref","unstructured":"Balasubramonian, R., Dwarkadas, S., Albonesi, D.H.: Dynamically managing the communication-parallelism trade-off in future clustered processors. In: Proceedings of the International Symposium on Computer Architecture (2003)","DOI":"10.1145\/859618.859650"},{"key":"291_CR5","doi-asserted-by":"crossref","unstructured":"Burd, T., Brodersen, R.: Design issues for dynamic voltage scaling. In: Proceedings of the International Symposium on Low Power Electronics and Design (2000)","DOI":"10.1145\/344166.344181"},{"key":"291_CR6","doi-asserted-by":"crossref","unstructured":"Collins, J., Tullsen, D.M.: Hardware identification of cache conflict misses. In: Proceedings of the International Symposium on Microarchitecture (1999)","DOI":"10.1109\/MICRO.1999.809450"},{"key":"291_CR7","doi-asserted-by":"crossref","unstructured":"Dhodapkar, A.S., Smith, J.E.: Managing multi-configuration hardware via dynamic working prediction. In: Proceedings of the International Symposium on Computer Architecture (2002)","DOI":"10.1145\/545214.545241"},{"key":"291_CR8","doi-asserted-by":"crossref","unstructured":"Flautner, K., Kim, N.S., Martin, S., Blaauw, D., Mudge, T.: Drowsy caches: simple techniques for reducing leakage power. In: Proceedings of the International Symposium on Computer Architecture (2002)","DOI":"10.1145\/545214.545232"},{"key":"291_CR9","doi-asserted-by":"crossref","unstructured":"Hu, Z., Kaxiras, S., Martonosi, M.: Timekeeping in the memory system: predicting and optimizing memory behavior. In: Proceedings of the International Symposium on Computer Architecture (2002)","DOI":"10.1145\/545214.545239"},{"key":"291_CR10","doi-asserted-by":"crossref","unstructured":"Kaxiras, S., Hu, Z., Martonosi, M.: Cache decay: exploiting generational behavior to reduce cache leakage power. In: Proceedings of the International Symposium on Computer Architecture (2001)","DOI":"10.1145\/379240.379268"},{"key":"291_CR11","unstructured":"Keramidas, G., Xekalakis, P., Kaxiras, S.: Recruiting decay for dynamic power reduction in set-associative caches. Trans. High Perform. Embed. Archit. Compil. 5470, 4\u201322 (2009)"},{"key":"291_CR12","doi-asserted-by":"crossref","unstructured":"Keramidas, G., Datsios, C., Kaxiras, S.: A Framework for Efficient Cache Resizing. In: Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and, Simulation (2012)","DOI":"10.1109\/SAMOS.2012.6404160"},{"key":"291_CR13","unstructured":"Kharbutli, M., Solihin, Y.: Counter-based cache replacement and bypassing algorithms. IEEE Trans. Comput. 57, 433\u2013447 (2008)"},{"key":"291_CR14","doi-asserted-by":"crossref","unstructured":"Kuroda, T., Suzuki, K., Mita, S., Fujita, T., Yamane, F., Sano, F., Chiba, A., Watanabe, Y., Matsuda, K., Maeda, T., Sakurai, T., Furuyama, T.: Variable supply-voltage scheme for low-power high-speed CMOS digital design. J. Solid-State Circuits 33, 454\u2013462 (1998)","DOI":"10.1109\/4.661211"},{"key":"291_CR15","doi-asserted-by":"crossref","unstructured":"Lai, A.C., Fide, C., Falsafi, B.: Dead-block prediction & dead block correlating prefetchers. In: Proceedings of the International Symposium on Computer Architecture (2001)","DOI":"10.1145\/379240.379259"},{"key":"291_CR16","doi-asserted-by":"crossref","unstructured":"Liu, H., Ferdman, M., Huh, J., Burger, D.: Cache bursts: a new approach for eliminating dead blocks and increasing cache efficiency. In: Proceedings of the International Symposium on Microarchitecture (2008)","DOI":"10.1109\/MICRO.2008.4771793"},{"key":"291_CR17","unstructured":"Mattson, R.L., Gecsei, J., Slutz, D.R., Traiger, I.L.: Evaluation techniques for storage hierarchies. IBM Syst. J. 9, 78\u2013117 (1970)"},{"key":"291_CR18","unstructured":"Muralimanohar, N., Balasubramonian, R., Jouppi, N.P. : CACTI 6.0: a tool to model large caches. HP Technical, Report (2009)"},{"key":"291_CR19","doi-asserted-by":"crossref","unstructured":"Powell, M., Yang, S.H., Falsafi, B., Roy, K., Vijaykumar, T.N.: Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories. In: Proceedings of the International Symposium on Low Power Electronics and Design (2000)","DOI":"10.1145\/344166.344526"},{"key":"291_CR20","unstructured":"Spanberger, A.: Designing a Dynamically Reconfigurable Cache for High Performance and Low Power. PhD Thesis, University of Virginia (2002)"},{"key":"291_CR21","unstructured":"Srinivasan, J.R.: Improving Cache Utilization. University of Cambridge, Technical Report (2011)"},{"key":"291_CR22","doi-asserted-by":"crossref","unstructured":"Sundararajan, K.T., Jones, T.M., Tophamet, N.: Smart Cache: a self adaptive cache architecture for energy efficiency. In: Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and, Simulation (2011)","DOI":"10.1109\/SAMOS.2011.6045443"},{"key":"291_CR23","doi-asserted-by":"crossref","unstructured":"Yang, S.H., Falsafi, B., Powell, M.D.,Roy, K., Vijaykumar, T.N.: An integrated circuit\/architecture approach to reducing leakage in deep-submicron high-performance i-caches. In: Proceedings of the High-Performance Computer Architecture Conference (2001)","DOI":"10.1109\/HPCA.2001.903259"},{"key":"291_CR24","unstructured":"Yang, S.H., Falsafi, B., Powell, M.D., Vijaykumar, T.N.: Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay. In: Proceedings of the High Performance Computer Architecture Conference (2002)"},{"key":"291_CR25","doi-asserted-by":"crossref","unstructured":"Ye, Y., Borkar, S., De, V.: A new technique for standby leakage reduction in high performance circuits. In: Proceedings of the International Symposium on VLSI Circuits (1998)","DOI":"10.1109\/VLSIC.1998.687996"},{"key":"291_CR26","doi-asserted-by":"crossref","unstructured":"Zhang, C., Vahid, F., Najjar, W.: A highly configurable cache architecture for embedded systems. In: Proceedings of the International Conference on Computer Architecture (2003)","DOI":"10.1145\/859618.859635"}],"container-title":["International Journal of Parallel Programming"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10766-013-0291-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10766-013-0291-4\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10766-013-0291-4","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,3,10]],"date-time":"2022-03-10T12:11:48Z","timestamp":1646914308000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10766-013-0291-4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10,25]]},"references-count":26,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2015,2]]}},"alternative-id":["291"],"URL":"https:\/\/doi.org\/10.1007\/s10766-013-0291-4","relation":{},"ISSN":["0885-7458","1573-7640"],"issn-type":[{"value":"0885-7458","type":"print"},{"value":"1573-7640","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,10,25]]}}}