{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T07:44:35Z","timestamp":1740123875109,"version":"3.37.3"},"reference-count":25,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2021,1,24]],"date-time":"2021-01-24T00:00:00Z","timestamp":1611446400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,1,24]],"date-time":"2021-01-24T00:00:00Z","timestamp":1611446400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Int J Parallel Prog"],"published-print":{"date-parts":[[2021,6]]},"DOI":"10.1007\/s10766-021-00691-5","type":"journal-article","created":{"date-parts":[[2021,1,24]],"date-time":"2021-01-24T14:02:23Z","timestamp":1611496943000},"page":"326-346","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["A Power-Aware Hybrid Cache for Chip-Multi Processors Based on Neural Network Prediction Technique"],"prefix":"10.1007","volume":"49","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3876-3746","authenticated-orcid":false,"given":"Furat","family":"Al-Obaidy","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arghavan","family":"Asad","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Farah A.","family":"Mohammadi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2021,1,24]]},"reference":[{"issue":"1","key":"691_CR1","doi-asserted-by":"publisher","first-page":"101","DOI":"10.1109\/TCAD.2018.2878168","volume":"39","author":"S Pagani","year":"2020","unstructured":"Pagani, S., Manoj, P.D.S., Jantsch, A., Henkel, J.: Machine learning for power, energy, and thermal management on multicore processors: a survey. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1), 101\u2013116 (2020). https:\/\/doi.org\/10.1109\/TCAD.2018.2878168","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"issue":"4","key":"691_CR2","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3323055","volume":"15","author":"J Dinakarrao","year":"2019","unstructured":"Dinakarrao, J., Pudukotai, S.M., Joseph, A., Haridass, A., Shafique, M., Henkel, J., Homayoun, H.: Application and thermal-reliability-aware reinforcement learning based multi-core power management. ACM J. Emerg. Technol. Comput. Syst. (JETC) 15(4), 1\u201319 (2019)","journal-title":"ACM J. Emerg. Technol. Comput. Syst. (JETC)"},{"issue":"7","key":"691_CR3","doi-asserted-by":"publisher","first-page":"468","DOI":"10.1016\/j.sysarc.2013.03.011","volume":"59","author":"M Modarressi","year":"2013","unstructured":"Modarressi, M., Asadinia, M., Sarbazi-Azad, H.: Using task migration to improve non-contiguous processor allocation in NoC-based CMPs. J. Syst. Arch. 59(7), 468\u2013481 (2013)","journal-title":"J. Syst. Arch."},{"key":"691_CR4","unstructured":"Shen, H.: Adaptive power management for computers and mobile devices. Ph.D. Dissertation, Syracuse University (2014)"},{"issue":"7","key":"691_CR5","doi-asserted-by":"publisher","first-page":"1736","DOI":"10.1109\/TC.2013.67","volume":"63","author":"K Ma","year":"2014","unstructured":"Ma, K., Wang, X., Wang, Y.: DPPC: dynamic power partitioning and control for improved chip multiprocessor performance. IEEE Trans. Comput. 63(7), 1736\u20131750 (2014). https:\/\/doi.org\/10.1109\/TC.2013.67","journal-title":"IEEE Trans. Comput."},{"issue":"3","key":"691_CR6","doi-asserted-by":"publisher","first-page":"930","DOI":"10.1109\/TED.2017.2653838","volume":"64","author":"J Wang","year":"2017","unstructured":"Wang, J., Chen, Z., Guo, J., Li, Y., Lu, Z.: ACO-based thermal-aware thread-to-core mapping for dark-silicon-constrained CMPs. IEEE Trans. Electron. Dev. 64(3), 930\u2013937 (2017). https:\/\/doi.org\/10.1109\/TED.2017.2653838","journal-title":"IEEE Trans. Electron. Dev."},{"key":"691_CR7","doi-asserted-by":"publisher","unstructured":"Turakhia, Y., Raghunathan, B., Garg, S., Marculescu, D.: HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors. In: 2013 50th ACM\/EDAC\/IEEE Design Automation Conference (DAC), Austin, pp. 1\u20137 (2013). https:\/\/doi.org\/10.1145\/2463209.2488948","DOI":"10.1145\/2463209.2488948"},{"key":"691_CR8","unstructured":"Wang, L., Skadron, K.: Dark versus dim silicon and near-threshold computing extended results. Department of Computer Science, University of Virginia, Technical Report TR-2013 1 (2012)"},{"key":"691_CR9","doi-asserted-by":"crossref","unstructured":"Karpuzcu, U.R., Sinkar, A., Kim, N.S., Torrellas, J.: Energy smart: toward energy-efficient many cores for near-threshold computing. In: Proceedings of HPCA, pp. 542\u2013553. IEEE (2013)","DOI":"10.1109\/HPCA.2013.6522348"},{"key":"691_CR10","doi-asserted-by":"publisher","unstructured":"Chen, Y., Wong, W., Li, H., Koh, C.: Processor caches built using multi-level spin-transfer torque RAM cells. In: IEEE\/ACM International Symposium on Low Power Electronics and Design, Fukuoka, pp. 73\u201378 (2011). https:\/\/doi.org\/10.1109\/ISLPED.2011.5993610","DOI":"10.1109\/ISLPED.2011.5993610"},{"key":"691_CR11","doi-asserted-by":"publisher","unstructured":"Sundararajan, K.T., Jones, T.M., Topham, N.: Smart cache: a self-adaptive cache architecture for energy efficiency. In: 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, Samos, pp. 41\u201350 (2011). https:\/\/doi.org\/10.1109\/SAMOS.2011.6045443","DOI":"10.1109\/SAMOS.2011.6045443"},{"key":"691_CR12","doi-asserted-by":"publisher","unstructured":"Joseph, P.J., Vaswani, K., Thazhuthaveetil, M.J.: Construction and use of linear regression models for processor performance analysis. In: The Twelfth International Symposium on High-Performance Computer Architecture, 2006, Austin, pp. 99\u2013108 (2006). https:\/\/doi.org\/10.1109\/HPCA.2006.1598116","DOI":"10.1109\/HPCA.2006.1598116"},{"issue":"11","key":"691_CR13","doi-asserted-by":"publisher","first-page":"195","DOI":"10.1145\/1168918.1168882","volume":"41","author":"E \u00cfpek","year":"2006","unstructured":"\u00cfpek, E., Mckee, S.A., Caruana, R., Supinski, B.R.D., Schulz, M.: Efficiently exploring architectural design spaces via predictive modeling. ACM SIGPLAN Not. 41(11), 195\u2013206 (2006)","journal-title":"ACM SIGPLAN Not."},{"key":"691_CR14","doi-asserted-by":"publisher","unstructured":"AL-Obaidy, F., Asad, A., Mohammadi, F.: Reconfigurable hybrid cache hierarchy in 3D chip-multi processors based on a convex optimization method. In: 2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE), Edmonton, pp. 1\u20136 (2019). https:\/\/doi.org\/10.1109\/CCECE.2019.8861876","DOI":"10.1109\/CCECE.2019.8861876"},{"key":"691_CR15","unstructured":"Ge, F., Wang, L., Lu, H.: STT-RAM based energy-efficient hybrid cache architecture for 3D chip multiprocessors. Eng. Lett. 27(1) (2019)"},{"key":"691_CR16","doi-asserted-by":"crossref","unstructured":"Asad, A., Al-Obaidy, F., Mohammadi, F.: Efficient power consumption using hybrid emerging memory technology for 3D CMPs. In: 2020 IEEE 11th Latin American Symposium on Circuits and Systems (LASCAS), pp. 1\u20134. IEEE (2020)","DOI":"10.1109\/LASCAS45839.2020.9069014"},{"key":"691_CR17","doi-asserted-by":"publisher","DOI":"10.1115\/1.861OPT","volume-title":"Engineering Optimization: Applications, Methods and Analysis","author":"RR Rhinehart","year":"2018","unstructured":"Rhinehart, R.R.: Engineering Optimization: Applications, Methods and Analysis. Wiley, New York (2018)"},{"issue":"5","key":"691_CR18","first-page":"60","volume":"7","author":"SP Mishra","year":"2017","unstructured":"Mishra, S.P., Sarkar, U.: Multivariate statistical data analysis-principal component analysis (PCA). Int. J. Liv. Res. 7(5), 60\u201378 (2017)","journal-title":"Int. J. Liv. Res."},{"issue":"4","key":"691_CR19","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1328195.1328196","volume":"4","author":"E Ipek","year":"2008","unstructured":"Ipek, E., McKee, S.A., et al.: Efficient architectural design space exploration via predictive modeling. ACM Trans. Architect. Code Optim. (TACO) 4(4), 1\u201334 (2008)","journal-title":"ACM Trans. Architect. Code Optim. (TACO)"},{"key":"691_CR20","doi-asserted-by":"crossref","unstructured":"Klug, T., Ott, M., Weidendorfer, J., Trinitis, C.: AUTOPIN\u2014automated optimization of thread-to-core pinning on multicore systems. In: Transactions on High-Performance Embedded Architectures and Compilers III, pp. 219\u2013235. Springer, Berlin (2011)","DOI":"10.1007\/978-3-642-19448-1_12"},{"key":"691_CR21","unstructured":"Hasan, M.: Multi-core Architectures for Feed-forward Neural Networks. PhD dissertation, University of Dayton (2014)"},{"key":"691_CR22","doi-asserted-by":"publisher","unstructured":"Binkert, N., Beckmann, B., et al.: The gem5 simulator. In: ACM SIGARCH Computer Architecture News, vol. 39, No. 2 (2011). https:\/\/doi.org\/10.1145\/2024716.202471","DOI":"10.1145\/2024716.202471"},{"issue":"3","key":"691_CR23","doi-asserted-by":"publisher","first-page":"23","DOI":"10.3390\/jlpea7030023","volume":"7","author":"S Mittal","year":"2017","unstructured":"Mittal, S., Wang, R., Vetter, J.: Destiny: a comprehensive tool with 3D and multi-level cell memory modeling capability. J. Low Power Electron. Appl. 7(3), 23 (2017)","journal-title":"J. Low Power Electron. Appl."},{"key":"691_CR24","doi-asserted-by":"publisher","unstructured":"Catania, V., Mineo, A., Monteleone, S., Palesi, M., Patti, D.: Noxim: an open, extensible and cycle-accurate network on chip simulator. In: 2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Toronto, pp. 162\u2013163 (2015). https:\/\/doi.org\/10.1109\/ASAP.2015.7245728","DOI":"10.1109\/ASAP.2015.7245728"},{"key":"691_CR25","doi-asserted-by":"crossref","unstructured":"Bienia, C., Kumar, S., Singh, J.P., Li, K.: The PARSEC benchmark suite: characterization and architectural implications. In: 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT), Toronto, pp. 72\u201381 (2008)","DOI":"10.1145\/1454115.1454128"}],"container-title":["International Journal of Parallel Programming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10766-021-00691-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10766-021-00691-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10766-021-00691-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,5,7]],"date-time":"2021-05-07T13:09:12Z","timestamp":1620392952000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10766-021-00691-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1,24]]},"references-count":25,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2021,6]]}},"alternative-id":["691"],"URL":"https:\/\/doi.org\/10.1007\/s10766-021-00691-5","relation":{},"ISSN":["0885-7458","1573-7640"],"issn-type":[{"type":"print","value":"0885-7458"},{"type":"electronic","value":"1573-7640"}],"subject":[],"published":{"date-parts":[[2021,1,24]]},"assertion":[{"value":"16 September 2020","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"11 January 2021","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"24 January 2021","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}