{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,21]],"date-time":"2025-12-21T07:11:46Z","timestamp":1766301106230,"version":"3.37.3"},"reference-count":15,"publisher":"Springer Science and Business Media LLC","issue":"5","license":[{"start":{"date-parts":[[2021,4,2]],"date-time":"2021-04-02T00:00:00Z","timestamp":1617321600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,4,2]],"date-time":"2021-04-02T00:00:00Z","timestamp":1617321600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Int J Parallel Prog"],"published-print":{"date-parts":[[2021,10]]},"DOI":"10.1007\/s10766-021-00700-7","type":"journal-article","created":{"date-parts":[[2021,4,2]],"date-time":"2021-04-02T12:02:40Z","timestamp":1617364960000},"page":"745-760","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["A Configurable Hardware Architecture for Runtime Application of Network Calculus"],"prefix":"10.1007","volume":"49","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3403-9339","authenticated-orcid":false,"given":"Xiao","family":"Hu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhonghai","family":"Lu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2021,4,2]]},"reference":[{"issue":"1","key":"700_CR1","doi-asserted-by":"publisher","first-page":"114","DOI":"10.1109\/18.61109","volume":"37","author":"RL Cruz","year":"1991","unstructured":"Cruz, R.L.: A calculus for network delay, part I: network elements in isolation; part II: network analysis. IEEE Trans. Inf. Theory 37(1), 114\u2013131 (1991)","journal-title":"IEEE Trans. Inf. Theory"},{"key":"700_CR2","volume-title":"Network Calculus: A Theory of Deterministic Queuing Systems for the Internet (LNCS 2050)","author":"J-YL Boudec","year":"2004","unstructured":"Boudec, J.-Y.L., Thiran, P.: Network Calculus: A Theory of Deterministic Queuing Systems for the Internet (LNCS 2050). Springer, Heidelberg, Germany (2004)"},{"key":"700_CR3","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4471-0459-9","volume-title":"Performance Guarantees in Communication Networks","author":"C-S Chang","year":"2000","unstructured":"Chang, C.-S.: Performance Guarantees in Communication Networks. Springer-Verlag, London, U.K. (2000)"},{"key":"700_CR4","volume-title":"Stochastic Network Calculus","author":"Y Jiang","year":"2008","unstructured":"Jiang, Y., Liu, Y.: Stochastic Network Calculus. Springer, London, U.K. (2008)"},{"issue":"5","key":"700_CR5","doi-asserted-by":"publisher","first-page":"802","DOI":"10.1109\/TCAD.2010.2043572","volume":"29","author":"Y Qian","year":"2010","unstructured":"Qian, Y., Lu, Z., Dou, W.: Analysis of worst-case delay bounds for on-chip packet-switching networks. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (TCAD) 29(5), 802\u2013815 (2010)","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (TCAD)"},{"key":"700_CR6","doi-asserted-by":"crossref","unstructured":"Huang, K., Chen, G., Buckl, C., Knoll, A.: Conforming the runtime inputs for hard real-time embedded systems. In: Proceeding of the 49th Design Automation Conference (DAC), (2012)","DOI":"10.1145\/2228360.2228436"},{"issue":"2","key":"700_CR7","doi-asserted-by":"publisher","first-page":"364","DOI":"10.1109\/TCAD.2017.2706561","volume":"37","author":"Z Lu","year":"2018","unstructured":"Lu, Z., Zhao, X.: xMAS-based QoS analysis methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2), 364\u2013377 (2018)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"700_CR8","doi-asserted-by":"crossref","unstructured":"de Dinechin, B. D., Durand, Y., van Amstel, D., Ghiti, A.: Guaranteed services of the NoC of a manycore processor. In Proc. of Int. Workshop on Network on Chip Architecture, Cambridge, U.K., pp. 11\u201316 (2014)","DOI":"10.1145\/2685342.2685344"},{"key":"700_CR9","doi-asserted-by":"publisher","first-page":"649","DOI":"10.1007\/s10009-006-0019-5","volume":"8","author":"E Wandeler","year":"2006","unstructured":"Wandeler, E., Thiele, L., et al.: System architecture evaluation using modular performance analysis\u2014A case study. Softw. Tools Technol. Transf. 8, 649\u2013667 (2006)","journal-title":"Softw. Tools Technol. Transf."},{"key":"700_CR10","doi-asserted-by":"crossref","unstructured":"Du, G., Li, M., et al.: An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs. In: Proc. of Int. Symposium on Networks-on-Chip (NOCS), Sept. (2014)","DOI":"10.1109\/NOCS.2014.7008761"},{"key":"700_CR11","doi-asserted-by":"crossref","unstructured":"Du, G., Ou, Y. et al.: OLITS: an ohm\u2019s law-like traffic splitting model based on congestion prediction. In: Proc. of 2016 Design, Automation and Test in Europe Conference, March (2016)","DOI":"10.3850\/9783981537079_0711"},{"key":"700_CR12","unstructured":"Lu, Z., Millberg, M. et al.: Flow Regulation for On-Chip Communication. In: Proc. of 2009 Design, Automation and Test in Europe Conference (DATE), Nice, France, April (2009)"},{"key":"700_CR13","doi-asserted-by":"crossref","unstructured":"Lu, Z., Wang, Y.: Dynamic flow regulation for ip integration on network-on-chip. In: The 6th ACM\/IEEE International Symposium on Networks-on-Chip (NOCS), May (2012)","DOI":"10.1109\/NOCS.2012.21"},{"issue":"2","key":"700_CR14","doi-asserted-by":"publisher","first-page":"556","DOI":"10.1109\/TVLSI.2016.2584781","volume":"25","author":"Z Lu","year":"2017","unstructured":"Lu, Z., Yao, Y.: Dynamic traffic regulation in NoC-based systems. IEEE Trans. VLSI Syst. 25(2), 556\u2013569 (2017)","journal-title":"IEEE Trans. VLSI Syst."},{"issue":"3","key":"700_CR15","doi-asserted-by":"publisher","first-page":"28","DOI":"10.1145\/3313869","volume":"15","author":"G Du","year":"2019","unstructured":"Du, G., Liu, G., et al.: SSS: self-aware system on chip using a static-dynamic hybrid method. ACM J. Emerg. Technol. Comput. Syst. 15(3), 28 (2019)","journal-title":"ACM J. Emerg. Technol. Comput. Syst."}],"container-title":["International Journal of Parallel Programming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10766-021-00700-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10766-021-00700-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10766-021-00700-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,8,24]],"date-time":"2021-08-24T21:07:14Z","timestamp":1629839234000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10766-021-00700-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4,2]]},"references-count":15,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2021,10]]}},"alternative-id":["700"],"URL":"https:\/\/doi.org\/10.1007\/s10766-021-00700-7","relation":{},"ISSN":["0885-7458","1573-7640"],"issn-type":[{"type":"print","value":"0885-7458"},{"type":"electronic","value":"1573-7640"}],"subject":[],"published":{"date-parts":[[2021,4,2]]},"assertion":[{"value":"23 December 2020","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"27 February 2021","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"2 April 2021","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}