{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,28]],"date-time":"2026-02-28T18:18:49Z","timestamp":1772302729697,"version":"3.50.1"},"reference-count":25,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2020,2,10]],"date-time":"2020-02-10T00:00:00Z","timestamp":1581292800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2020,2,10]],"date-time":"2020-02-10T00:00:00Z","timestamp":1581292800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Int J Speech Technol"],"published-print":{"date-parts":[[2020,6]]},"DOI":"10.1007\/s10772-020-09683-1","type":"journal-article","created":{"date-parts":[[2020,2,10]],"date-time":"2020-02-10T18:02:35Z","timestamp":1581357755000},"page":"259-264","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":34,"title":["ASIC implementation of distributed arithmetic based FIR filter using RNS for high speed DSP systems"],"prefix":"10.1007","volume":"23","author":[{"given":"Grande Naga","family":"Jyothi","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9450-9574","authenticated-orcid":false,"given":"Kishore","family":"Sanapala","sequence":"additional","affiliation":[]},{"given":"A.","family":"Vijayalakshmi","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2020,2,10]]},"reference":[{"key":"9683_CR1","doi-asserted-by":"crossref","unstructured":"Bernocchi, G. L., et al. (2006). A hybrid RNS adaptive filter for channel equalization. In IEEE fortieth asilomar conference on signals, systems and computers.","DOI":"10.1109\/ACSSC.2006.355052"},{"issue":"10","key":"9683_CR2","doi-asserted-by":"publisher","first-page":"1296","DOI":"10.1109\/TCSI.2003.817789","volume":"50","author":"B Cao","year":"2003","unstructured":"Cao, B., Chang, C.-H., & Srikanthan, T. (2003). An efficient reverse converter for the 4-moduli set 2n\u20131, 2n, 2n+1, 22n+1 based on the new Chinese remainder theorem. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications,50(10), 1296\u20131303.","journal-title":"IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications"},{"issue":"4","key":"9683_CR3","doi-asserted-by":"publisher","first-page":"26","DOI":"10.1109\/MCAS.2015.2484118","volume":"15","author":"CH Chang","year":"2015","unstructured":"Chang, C. H., et al. (2015). Residue number systems: A new paradigm to datapath optimization for low-power and high-performance digital signal processing applications. IEEE Circuits and Systems Magazine,15(4), 26\u201344.","journal-title":"IEEE Circuits and Systems Magazine"},{"issue":"8","key":"9683_CR4","doi-asserted-by":"publisher","first-page":"617","DOI":"10.1109\/TCSII.2006.875373","volume":"53","author":"K-H Chen","year":"2006","unstructured":"Chen, K.-H., & Chiueh, T.-D. (2006). A low-power digit-based reconfigurable FIR filter. IEEE Transactions on Circuits and Systems II,53(8), 617\u2013621.","journal-title":"IEEE Transactions on Circuits and Systems II"},{"key":"9683_CR5","doi-asserted-by":"crossref","unstructured":"Fayed, A., & Bayoumi, M. A. (2002). A merged multiplier accumulator for high speed signal processing applications. In 2002 IEEE international conference on acoustics, speech, and signal processing.","DOI":"10.1109\/ICASSP.2002.1005371"},{"key":"9683_CR6","unstructured":"Ghamkhari, S. F., & Ghaznavi-Ghoushchi, M. B. (2012). In 20th Iranian conference on electrical engineering (ICEE2012)"},{"issue":"10","key":"9683_CR7","doi-asserted-by":"publisher","first-page":"677","DOI":"10.1109\/82.539000","volume":"43","author":"R Hartley","year":"1996","unstructured":"Hartley, R. (1996). Subexpression sharing in filters using canonic signed digit multipliers. IEEE Transactions on Circuits and Systems II,43(10), 677\u2013688.","journal-title":"IEEE Transactions on Circuits and Systems II"},{"key":"9683_CR8","doi-asserted-by":"crossref","unstructured":"Kamal, R., Chandravanshi, P., & Jain, N. (2014). Efficient VLSI architecture for FIR filter using DA-RNS. In IEEE international conference on electronics, communication and computational engineering (ICECCE).","DOI":"10.1109\/ICECCE.2014.7086656"},{"issue":"1","key":"9683_CR9","doi-asserted-by":"publisher","first-page":"869","DOI":"10.1109\/4.509877","volume":"3","author":"K-Y Khoo","year":"1996","unstructured":"Khoo, K.-Y., et al. (1996). A programmable FIR digital filter using CSD coefficients. IEEE Journal of Solid-State Circuits,3(1), 869\u2013874.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"9683_CR10","doi-asserted-by":"crossref","unstructured":"Kucherov, N. N., et al. (2018). A high-speed residue-to-binary converter based on approximate Chinese Remainder Theorem. In IEEE conference of Russian young researchers in electrical and electronic engineering (EIConRus).","DOI":"10.1109\/EIConRus.2018.8317098"},{"key":"9683_CR11","unstructured":"Matutino, P. M., Chaves, R., & Sousa, L. (2014). ROM-less RNS-to-binary converter moduli 22n-1, 22n+1, 2n-3, 2n+3. In IEEE 14th international symposium on integrated circuits (ISIC)."},{"issue":"3","key":"9683_CR12","doi-asserted-by":"publisher","first-page":"603","DOI":"10.1109\/TVLSI.2014.2314174","volume":"23","author":"PM Matutino","year":"2015","unstructured":"Matutino, P. M., Chaves, R., & Sousa, L. (2015). Arithmetic-based binary-to-RNS converter modulo 2n\u00b1k for JN-bit dynamic range. IEEE Transactions on VLSI System,23(3), 603\u2013607.","journal-title":"IEEE Transactions on VLSI System"},{"issue":"7","key":"9683_CR13","doi-asserted-by":"publisher","first-page":"3009","DOI":"10.1109\/TSP.2007.914926","volume":"56","author":"PK Meher","year":"2008","unstructured":"Meher, P. K., Chandrasekaran, S., & Amira, A. (2008). FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic. IEEE Transactions on Signal Processing,56(7), 3009\u20133017.","journal-title":"IEEE Transactions on Signal Processing"},{"key":"9683_CR14","doi-asserted-by":"crossref","unstructured":"Menon, S., & Chang, C.-H. (2006). A reconfigurable multi-modulus modulo multiplier. In IEEE Asia Pacific conference on circuits and systems.","DOI":"10.1109\/APCCAS.2006.342349"},{"issue":"1","key":"9683_CR15","doi-asserted-by":"publisher","first-page":"115","DOI":"10.1023\/A:1008167323437","volume":"28","author":"U Meyer-Base","year":"2001","unstructured":"Meyer-Base, U., Garc\u00eda, A., & Taylor, F. (2001). Implementation of a communications channelizer using FPGAs and RNS arithmetic. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology,28(1), 115\u2013128.","journal-title":"Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology"},{"key":"9683_CR16","unstructured":"Mohanty, B. K., & Meher, P. K. (2016). A high-performance energy-efficient architecture for FIR adaptive filter based on new distributed arithmetic formulation of block LMS algorithm. IEEE Transaction on Very Large Scale Integration Systems, 24(5)"},{"key":"9683_CR17","unstructured":"Naga Jyothi, G., & Sri Devi, S. (2017). Distributed arithmetic architectures for FIR filters: A comparative review. IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET)."},{"issue":"23","key":"9683_CR25","doi-asserted-by":"publisher","first-page":"32679","DOI":"10.1007\/s11042-018-7038-6","volume":"78","author":"G Naga Jyothi","year":"2019","unstructured":"Naga Jyothi, G., & Sridevi, S. (2019). High speed and low area decision feed-back equalizer with novel memory less distributed arithmetic filter. Multimedia Tools and Applications,78(23), 32679\u201332693.","journal-title":"Multimedia Tools and Applications"},{"key":"9683_CR18","volume-title":"VLSI digital signal processing systems: Design and implementation","author":"K Parhi","year":"2007","unstructured":"Parhi, K. (2007). VLSI digital signal processing systems: Design and implementation. New Delhi: Wiley."},{"key":"9683_CR19","doi-asserted-by":"crossref","unstructured":"Petrousov, G., & Dasygenis, M. (2014). A unique network EDA tool to create optimized ad hoc binary to residue number system converters. IEEE 24th international workshop on power and timing modeling, optimization and simulation (PATMOS).","DOI":"10.1109\/PATMOS.2014.6951866"},{"key":"9683_CR20","volume-title":"Digital signal processing: Principles algorithms and applications","author":"JG Proakis","year":"2001","unstructured":"Proakis, J. G. (2001). Digital signal processing: Principles algorithms and applications. New Delhi: Pearson Education India."},{"key":"9683_CR21","unstructured":"Rahul Narasimhan, A. (2015). High speed multiply-accumulator coprocessor realized for digital filters. IEEE international conference on electrical, computer and communication technologies (ICECCT)."},{"key":"9683_CR24","series-title":"Lecture notes in electrical engineering","doi-asserted-by":"publisher","first-page":"217","DOI":"10.1007\/978-981-10-7329-8_22","volume-title":"Microelectronics, electromagnetics and telecommunications","author":"K Sanapala","year":"2018","unstructured":"Sanapala, K., Shree, L. R., & Sakthivel, R. (2018). Design of ultralow voltage-hybrid full adder circuit using GLBB scheme for energy-efficient arithmetic applications. In J. Anguera, S. Satapathy, V. Bhateja, & K. Sunitha (Eds.), Microelectronics, electromagnetics and telecommunications. Lecture notes in electrical engineering (pp. 217\u2013223). Singapore: Springer."},{"issue":"4","key":"9683_CR22","first-page":"620","volume":"30","author":"S Shanthala","year":"2009","unstructured":"Shanthala, S., & Kulkarni, S. Y. (2009). VLSI design and implementation of low power MAC unit with block enabling technique. European Journal of Scientific Research,30(4), 620\u2013630.","journal-title":"European Journal of Scientific Research"},{"issue":"8","key":"9683_CR23","doi-asserted-by":"publisher","first-page":"2139","DOI":"10.1109\/TCSI.2013.2239164","volume":"60","author":"CH Vun","year":"2013","unstructured":"Vun, C. H., Premkumar, A. B., & Zhang, W. (2013). A new RNS based DA approach for inner product computation. IEEE Transactions on Circuits and Systems I,60(8), 2139\u20132152.","journal-title":"IEEE Transactions on Circuits and Systems I"}],"container-title":["International Journal of Speech Technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10772-020-09683-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10772-020-09683-1\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10772-020-09683-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,2,10]],"date-time":"2021-02-10T00:01:10Z","timestamp":1612915270000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10772-020-09683-1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,2,10]]},"references-count":25,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2020,6]]}},"alternative-id":["9683"],"URL":"https:\/\/doi.org\/10.1007\/s10772-020-09683-1","relation":{},"ISSN":["1381-2416","1572-8110"],"issn-type":[{"value":"1381-2416","type":"print"},{"value":"1572-8110","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,2,10]]},"assertion":[{"value":"6 November 2019","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"31 January 2020","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"10 February 2020","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}