{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,22]],"date-time":"2026-07-22T16:26:44Z","timestamp":1784737604769,"version":"3.55.0"},"reference-count":36,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T00:00:00Z","timestamp":1761523200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"},{"start":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T00:00:00Z","timestamp":1761523200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Discov Computing"],"abstract":"<jats:title>Abstract<\/jats:title>\n                  <jats:p>Network-on-Chip (NoC) is a promising technology that uses a network of interconnected processing elements to improve performance and reduce communication costs in complex systems. However, faults can occur in NoC systems due to various factors such as manufacturing defects, aging, and environmental factors. To address this challenge, fault-tolerant techniques are necessary to ensure the reliable and efficient operation of NoC systems. One such technique is fault-tolerant application mapping, in which application cores are assigned to processing elements to reduce the system performance degradation caused by the failures. However, the application mapping for NoC systems, including fault tolerance, is a complex task. This paper presents a novel approach consisting of a transformer-based reinforcement learning algorithm for application mapping in mesh topology based NoC. This allows NoC to communicate efficiently in the presence of faults. The proposed approach is compared with other state-of-the-art techniques. The findings demonstrate that the proposed approach outperforms the average communication cost encompassing 2, 5, and 7 percent more than RL-MAP, NMA, and PSO, respectively, and also has less run-time. Also, it is observed that the introduced technique excels against the remaining techniques with respect to the average network latency decrease by 3, 5, and 6 percent for RL-MAP, NMA, and PSO correspondingly. The approach in this method is thus helpful in the design of NoC systems that are energy efficient as well as reliable for targeted applications.<\/jats:p>","DOI":"10.1007\/s10791-025-09704-0","type":"journal-article","created":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T10:23:27Z","timestamp":1761560607000},"update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Enhancing fault-tolerant application mapping in network-on-chip through transformer network based reinforcement learning approach"],"prefix":"10.1007","volume":"28","author":[{"given":"Jagadheesh","family":"Samala","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bindu Bhargavi","family":"Mekala","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Soumya","family":"J","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2025,10,27]]},"reference":[{"key":"9704_CR1","doi-asserted-by":"publisher","unstructured":"Ababei C, Katti R. Achieving network on chip fault tolerance by adaptive remapping. In: 2009 IEEE International Symposium on Parallel and Distributed Processing, 2009;1\u20134, https:\/\/doi.org\/10.1109\/IPDPS.2009.5161202","DOI":"10.1109\/IPDPS.2009.5161202"},{"key":"9704_CR2","doi-asserted-by":"publisher","DOI":"10.1016\/j.jnca.2023.103729","volume":"219","author":"W Amin","year":"2023","unstructured":"Amin W, Hussain F, Anjum S, et al. Efficient application mapping approach based on grey wolf optimization for network on chip. J Netw Comput Appl. 2023;219: 103729. https:\/\/doi.org\/10.1016\/j.jnca.2023.103729.","journal-title":"J Netw Comput Appl"},{"issue":"1","key":"9704_CR3","doi-asserted-by":"publisher","first-page":"70","DOI":"10.1109\/2.976921","volume":"35","author":"L Benini","year":"2002","unstructured":"Benini L, De Micheli G. Networks on chips: a new soc paradigm. Computer. 2002;35(1):70\u20138. https:\/\/doi.org\/10.1109\/2.976921.","journal-title":"Computer"},{"key":"9704_CR4","doi-asserted-by":"publisher","first-page":"14","DOI":"10.1016\/j.sysarc.2016.04.011","volume":"66\u201367","author":"A Benmessaoud Gabis","year":"2016","unstructured":"Benmessaoud Gabis A, Koudil M. Noc routing protocols objective-based classification. J Syst Architect. 2016;66\u201367:14\u201332. https:\/\/doi.org\/10.1016\/j.sysarc.2016.04.011.","journal-title":"J Syst Architect"},{"key":"9704_CR5","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3269983","volume":"15","author":"PV Bhanu","year":"2019","unstructured":"Bhanu PV, Kulkarni PV, J S. Fault-tolerant network-on-chip design with flexible spare core placement. J Emerg Technol Comput Syst. 2019;15:1.","journal-title":"J Emerg Technol Comput Syst"},{"key":"9704_CR6","unstructured":"Bresson X, Laurent T. The transformer network for the traveling salesman problem. arXiv preprint arXiv:2103.03012 2021"},{"key":"9704_CR7","doi-asserted-by":"crossref","unstructured":"Chen Q, Huang W, Zhang Y, et\u00a0al. An IP core mapping algorithm based on neural networks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2020;1\u201314. DOI: 10\/ghnc2t, URL: 10\/ghnc2t, conference Name: IEEE Transactions on Very Large Scale Integration (VLSI) Systems","DOI":"10.1109\/TVLSI.2006.886504"},{"issue":"9","key":"9704_CR8","doi-asserted-by":"publisher","first-page":"1638","DOI":"10.1109\/TVLSI.2021.3097712","volume":"29","author":"Q Chen","year":"2021","unstructured":"Chen Q, Huang W, Peng Y, et al. A reinforcement learning-based framework for solving the ip mapping problem. IEEE Trans Very Large Scale Integr VLSI Syst. 2021;29(9):1638\u201351. https:\/\/doi.org\/10.1109\/TVLSI.2021.3097712.","journal-title":"IEEE Trans Very Large Scale Integr VLSI Syst"},{"key":"9704_CR9","doi-asserted-by":"publisher","unstructured":"Chou CL, Marculescu R. Farm: Fault-aware resource management in noc-based multiprocessor platforms. In: 2011 Design, Automation and Test in Europe, 2011;1\u20136, https:\/\/doi.org\/10.1109\/DATE.2011.5763113","DOI":"10.1109\/DATE.2011.5763113"},{"key":"9704_CR10","doi-asserted-by":"publisher","unstructured":"Choudhary J, J S, Cenkeramaddi LR. Raman: Reinforcement learning inspired algorithm for mapping applications onto mesh network-on-chip. In: 2021 ACM\/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 2021;52\u201358, https:\/\/doi.org\/10.1109\/SLIP52707.2021.00019","DOI":"10.1109\/SLIP52707.2021.00019"},{"key":"9704_CR11","doi-asserted-by":"crossref","unstructured":"Dally W, Towles B. Route packets, not wires: on-chip interconnection networks. In: Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232), 2001;684\u2013689","DOI":"10.1145\/378239.379048"},{"key":"9704_CR12","doi-asserted-by":"crossref","unstructured":"Dick R, Rhodes D, Wolf W. TGFF: task graphs for free. In: Proceedings of the Sixth International Workshop on Hardware\/Software Codesign. (CODES\/CASHE\u201998), 1998;97\u2013101, DOI: 10\/bsqt2m, URL: 10\/bsqt2m, ISSN: 1092-6100","DOI":"10.1145\/278241.278309"},{"key":"9704_CR13","doi-asserted-by":"publisher","unstructured":"Feng C, Lu Z, Jantsch A, et\u00a0al. Fon: Fault-on-neighbor aware routing algorithm for networks-on-chip. In: 23rd IEEE International SOC Conference, 2010;441\u2013446, https:\/\/doi.org\/10.1109\/SOCC.2010.5784672","DOI":"10.1109\/SOCC.2010.5784672"},{"key":"9704_CR14","doi-asserted-by":"publisher","first-page":"6","DOI":"10.1145\/3510381","volume":"27","author":"S Jagadheesh","year":"2022","unstructured":"Jagadheesh S, Bhanu PV, J. S. Noc application mapping optimization using reinforcement learning. ACM Trans Des Autom Electron Syst. 2022;27:6. https:\/\/doi.org\/10.1145\/3510381.","journal-title":"ACM Trans Des Autom Electron Syst"},{"issue":"3","key":"9704_CR15","doi-asserted-by":"publisher","first-page":"706","DOI":"10.1109\/30.793577","volume":"45","author":"E Jaspers","year":"1999","unstructured":"Jaspers E, de With P. Chip-set for video display of multimedia information. IEEE Trans Consum Electron. 1999;45(3):706\u201315. https:\/\/doi.org\/10.1109\/30.793577.","journal-title":"IEEE Trans Consum Electron"},{"key":"9704_CR16","doi-asserted-by":"publisher","first-page":"39","DOI":"10.1016\/j.sysarc.2018.10.001","volume":"92","author":"N Kadri","year":"2019","unstructured":"Kadri N, Koudil M. A survey on fault-tolerant application mapping techniques for network-on-chip. J Syst Architect. 2019;92:39\u201352. https:\/\/doi.org\/10.1016\/j.sysarc.2018.10.001.","journal-title":"J Syst Architect"},{"key":"9704_CR17","doi-asserted-by":"publisher","first-page":"39","DOI":"10.1016\/j.sysarc.2018.10.001","volume":"92","author":"N Kadri","year":"2019","unstructured":"Kadri N, Koudil M. A survey on fault-tolerant application mapping techniques for network-on-chip. J Syst Architect. 2019;92:39\u201352. https:\/\/doi.org\/10.1016\/j.sysarc.2018.10.001.","journal-title":"J Syst Architect"},{"issue":"16","key":"9704_CR18","doi-asserted-by":"publisher","first-page":"18153","DOI":"10.1007\/s11227-022-04590-5","volume":"78","author":"N Kadri","year":"2022","unstructured":"Kadri N, Chenine A, Laib Z, et al. Reliability-aware intelligent mapping based on reinforcement learning for networks-on-chips. J Supercomput. 2022;78(16):18153\u201388. https:\/\/doi.org\/10.1007\/s11227-022-04590-5.","journal-title":"J Supercomput"},{"issue":"6","key":"9704_CR19","doi-asserted-by":"publisher","first-page":"238","DOI":"10.1049\/iet-cdt.2013.0032","volume":"7","author":"F Khalili","year":"2013","unstructured":"Khalili F, Zarandi HR. A fault-tolerant core mapping technique in networks-on-chip. IET Comput Digit Tech. 2013;7(6):238\u201345. https:\/\/doi.org\/10.1049\/iet-cdt.2013.0032.","journal-title":"IET Comput Digit Tech"},{"issue":"3","key":"9704_CR20","doi-asserted-by":"publisher","first-page":"163","DOI":"10.1504\/IJHPSA.2008.021797","volume":"1","author":"S Kundu","year":"2008","unstructured":"Kundu S, Chattopadhyay S. Network-on-chip architecture design based on mesh-of-tree deterministic routing topology. Int J High Perform Syst Archit. 2008;1(3):163. https:\/\/doi.org\/10.1504\/IJHPSA.2008.021797.","journal-title":"Int J High Perform Syst Archit"},{"issue":"6","key":"9704_CR21","doi-asserted-by":"publisher","first-page":"471","DOI":"10.1016\/j.micpro.2012.05.012","volume":"36","author":"S Kundu","year":"2012","unstructured":"Kundu S, Soumya J, Chattopadhyay S. Design and evaluation of mesh-of-tree based network-on-chip using virtual channel router. Microprocess Microsyst. 2012;36(6):471\u201388. https:\/\/doi.org\/10.1016\/j.micpro.2012.05.012.","journal-title":"Microprocess Microsyst"},{"key":"9704_CR22","doi-asserted-by":"publisher","first-page":"896","DOI":"10.1109\/DATE.2004.1269002","volume":"2","author":"S Murali","year":"2004","unstructured":"Murali S, De Micheli G. Bandwidth-constrained mapping of cores onto noc architectures. Proc Des Autom Test Europe Conf Exhib. 2004;2:896\u2013901. https:\/\/doi.org\/10.1109\/DATE.2004.1269002.","journal-title":"Proc Des Autom Test Europe Conf Exhib"},{"key":"9704_CR23","doi-asserted-by":"publisher","unstructured":"Ogras UY, Hu J, Marculescu R. Key research problems in noc design: a holistic perspective. In: Proceedings of the 3rd IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis. Association for Computing Machinery, New York, NY, USA, CODES+ISSS \u201905, 2005;69-74, https:\/\/doi.org\/10.1145\/1084834.1084856","DOI":"10.1145\/1084834.1084856"},{"issue":"8","key":"9704_CR24","doi-asserted-by":"publisher","first-page":"1487","DOI":"10.1109\/JPROC.2006.879797","volume":"94","author":"M Pedram","year":"2006","unstructured":"Pedram M, Nazarian S. Thermal modeling, analysis, and management in vlsi circuits: Principles and methods. Proc IEEE. 2006;94(8):1487\u2013501. https:\/\/doi.org\/10.1109\/JPROC.2006.879797.","journal-title":"Proc IEEE"},{"key":"9704_CR25","doi-asserted-by":"publisher","unstructured":"Romanov A, Myachin N, Sukhov A. Fault-tolerant routing in networks-on-chip using self-organizing routing algorithms. In: IECON 2021 47th Annual Conference of the IEEE Industrial Electronics Society, 2021;1\u20136, https:\/\/doi.org\/10.1109\/IECON48115.2021.9589829","DOI":"10.1109\/IECON48115.2021.9589829"},{"issue":"1","key":"9704_CR26","doi-asserted-by":"publisher","first-page":"60","DOI":"10.1016\/j.sysarc.2012.10.004","volume":"59","author":"PK Sahu","year":"2013","unstructured":"Sahu PK, Chattopadhyay S. A survey on application mapping strategies for network-on-chip design. J Syst Architect. 2013;59(1):60\u201376.","journal-title":"J Syst Architect"},{"key":"9704_CR27","doi-asserted-by":"publisher","first-page":"88","DOI":"10.1016\/j.micpro.2018.10.008","volume":"64","author":"PK Sharma","year":"2019","unstructured":"Sharma PK, Biswas S, Mitra P. Energy efficient heuristic application mapping for 2-d mesh-based network-on-chip. Microprocess Microsyst. 2019;64:88\u2013100. https:\/\/doi.org\/10.1016\/j.micpro.2018.10.008.","journal-title":"Microprocess Microsyst"},{"key":"9704_CR28","doi-asserted-by":"publisher","unstructured":"Shen WT, Chao CH, Lien YK, et\u00a0al. A new binomial mapping and optimization algorithm for reduced-complexity mesh-based on-chip network. In: First International Symposium on Networks-on-Chip (NOCS\u201907), 2007;317\u2013322, https:\/\/doi.org\/10.1109\/NOCS.2007.5","DOI":"10.1109\/NOCS.2007.5"},{"key":"9704_CR29","doi-asserted-by":"publisher","first-page":"1","DOI":"10.3390\/sym16010127","volume":"16","author":"AM Sukhov","year":"2024","unstructured":"Sukhov AM, Romanov AY, Selin MP. Virtual coordinate system based on a circulant topology for routing in networks-on-chip. Symmetry. 2024;16:1. https:\/\/doi.org\/10.3390\/sym16010127.","journal-title":"Symmetry"},{"issue":"1","key":"9704_CR30","doi-asserted-by":"publisher","first-page":"97","DOI":"10.1162\/089120103321337458","volume":"29","author":"C Tillmann","year":"2003","unstructured":"Tillmann C, Ney H. Word reordering and a dynamic programming beam search algorithm for statistical machine translation. Comput Linguist. 2003;29(1):97\u2013133. https:\/\/doi.org\/10.1162\/089120103321337458.","journal-title":"Comput Linguist"},{"key":"9704_CR31","unstructured":"Vaswani A, Shazeer N, Parmar N, et\u00a0al. Attention is all you need. In: Proceedings of the 31st International Conference on Neural Information Processing Systems. Curran Associates Inc., Red Hook, NY, USA, NIPS\u201917, 2017;6000-6010."},{"key":"9704_CR32","doi-asserted-by":"publisher","first-page":"86","DOI":"10.54254\/2755-2721\/2025.21360","volume":"138","author":"Z Wang","year":"2025","unstructured":"Wang Z. Accelerating transformer models: Fpga-based hardware optimization and heterogeneous computing strategies. Appl Comput Eng. 2025;138:86\u201392. https:\/\/doi.org\/10.54254\/2755-2721\/2025.21360.","journal-title":"Appl Comput Eng"},{"key":"9704_CR33","doi-asserted-by":"publisher","unstructured":"Wells PM, Chakraborty K, Sohi GS. Adapting to intermittent faults in future multicore systems. In: 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007). 2007;431\u2013431. https:\/\/doi.org\/10.1109\/PACT.2007.4336259.","DOI":"10.1109\/PACT.2007.4336259"},{"issue":"1","key":"9704_CR34","doi-asserted-by":"publisher","first-page":"4","DOI":"10.1109\/TNNLS.2020.2978386","volume":"32","author":"Z Wu","year":"2021","unstructured":"Wu Z, Pan S, Chen F, et al. A comprehensive survey on graph neural networks. IEEE Trans Neural Netw Learn Syst. 2021;32(1):4\u201324. https:\/\/doi.org\/10.1109\/TNNLS.2020.2978386.","journal-title":"IEEE Trans Neural Netw Learn Syst"},{"key":"9704_CR35","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2024.106323","volume":"151","author":"C Xu","year":"2024","unstructured":"Xu C, Shi X, Yang H, et al. 3d network-on-chip data acquisition system mapping based on reinforcement learning and improved attention mechanism. Microelectron J. 2024;151: 106323. https:\/\/doi.org\/10.1016\/j.mejo.2024.106323.","journal-title":"Microelectron J"},{"issue":"10","key":"9704_CR36","doi-asserted-by":"publisher","first-page":"3027","DOI":"10.1109\/TVLSI.2016.2535359","volume":"24","author":"L Yang","year":"2016","unstructured":"Yang L, Liu W, Jiang W, et al. Application mapping and scheduling for network-on-chip-based multiprocessor system-on-chip with fine-grain communication optimization. IEEE Trans Very Large Scale Integr VLSI Syst. 2016;24(10):3027\u201340. https:\/\/doi.org\/10.1109\/TVLSI.2016.2535359.","journal-title":"IEEE Trans Very Large Scale Integr VLSI Syst"}],"container-title":["Discover Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10791-025-09704-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10791-025-09704-0\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10791-025-09704-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T10:23:31Z","timestamp":1761560611000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10791-025-09704-0"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10,27]]},"references-count":36,"journal-issue":{"issue":"1","published-online":{"date-parts":[[2025,12]]}},"alternative-id":["9704"],"URL":"https:\/\/doi.org\/10.1007\/s10791-025-09704-0","relation":{},"ISSN":["2948-2992"],"issn-type":[{"value":"2948-2992","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,10,27]]},"assertion":[{"value":"11 April 2025","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"8 August 2025","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"27 October 2025","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"Not applicable.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Ethical approval and Consent to participate"}},{"value":"Not applicable.","order":3,"name":"Ethics","group":{"name":"EthicsHeading","label":"Consent for publication"}},{"value":"The authors declare no Conflict of interest.","order":4,"name":"Ethics","group":{"name":"EthicsHeading","label":"Competing interests"}}],"article-number":"235"}}